JPH06350028A - Method of increasing capacity of ic storage cell and semiconductor storage element - Google Patents

Abstract

PURPOSE:To increase memory capacity simply by forming a thin insulating layer onto a first capacitor electrode formed onto a rough surface, shaping a second capacitor electrode onto the thin insulating layer and forming a capacitance between the first and second capacitor electrodes. CONSTITUTION:A first capacitor electrode 1 is formed onto a silicon substrate 2, and an oxide layer with a surface having unevenness is shaped onto the first capacitor electrode 1. The first capacitor electrode 1 is formed on a rough surface by using the surface of the oxide layer as an etching pattern. The first capacitor electrode 1 is formed completely, the oxide layer is removed, and a thin insulating film 4 is shaped onto the first capacitor electrode 1. A second capacitor electrode 3 is formed onto the thin insulating film 4, and a capacitance is formed between the first and second capacitor electrodes 1, 3. Accordingly, memory capacity can be increased through a simple method.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a storage capacitor for use in a memory cell.

[0002]

2. Description of the Related Art Storage capacitors that use two opposing electrodes to form a capacitance have long been used for memory devices. The first storage capacitor was formed using two opposing electrodes separated by a dielectric. It has been found that it is necessary to increase the surface area of at least one electrode in order to increase the storage capacity. One of the methods used to increase surface area has involved etching the device substrate of one electrode to form a channel. Then, the surface area of the electrode was increased by forming many small nodes on the electrode surface. The additional formation of four sides significantly increased the surface area of these nodes, which increased the surface area by a factor of about 5.

Recent improvements in storage capacitors include making the surface of the node very rough. That is, a node is formed on the node. The larger the number of nodes on a node, ie the rougher the node surface, the larger the surface area. "Production of storage capacitance, improved capacitor with rough electrodes"
(Nikkei Microdevices, November 1990, Solid State Devices and Materials 1990 International Conference), these nodes on nodes are
It is formed by depositing a polysilicon film on the storage electrode node at a temperature in the range of ° C to 640 ° C. The degree of roughness on the node depends on the temperature at which the polysilicon is deposited. Maximum roughness appears to occur at 580 ° C.

[0004]

As is readily apparent from the prior art, recent efforts to make storage electrodes more coarsely rely heavily on temperature. In any case, a temperature change of about 20 ° C. drastically affects the roughness of the deposited film. If very little attention is paid to temperature control, the effect of adhesion will be completely lost.

Therefore, there is a need for a method of increasing the roughness of storage electrode nodes that is less temperature sensitive and is less expensive than current processing techniques. What is needed is a process that can be easily incorporated into existing device processes and that does not require the extreme control required by those already proposed processes.

[0006]

SUMMARY OF THE INVENTION A simple means proposed by the present invention to increase the roughness of the electrode node of a storage capacitor is to etch very small grooves and incisions in the surface of the polysilicon node. It is to be. The etching mask used is a simple oxide with natural unevenness. Due to this oxide unevenness, it is possible to etch grooves or notches in the node surface. The control for this process is not in a narrow temperature window, such as when forming a polysilicon layer, but in the normal deposition and time etching processes that are standard in most device manufacturing processes. .

[0007]

The present invention distinguishes itself from the prior art in several respects. First, the present invention utilizes prior art nodes to increase the total surface area of capacitor electrodes. Moreover, the present invention further increases the surface area by forming grooves or incisions in the surface of the node, greatly increasing the total storage capacity in addition to the surface area of the node.

Second, the process of the present invention is simpler to use and distinguishes it from recent prototypes in that it utilizes standard semiconductor device processes to create surface roughness. Is. In contrast, the conventional technology is
Strict temperature control is required to ensure proper roughness of the node surface. Using the prior art, a temperature change of about 20 ° C. would change the roughness of the node at all.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 shows an embodiment of the present invention.
Reference numeral 1 is a first electrode, 2 is a silicon substrate, 3 is a second electrode, 4 is an insulating film for insulating the first electrode from the second electrode 3, and 5 is an oxide layer.

The first and second electrodes 1 and 3 are connected to the insulating film 4.
Separation and applying charge to the electrodes creates a capacitance between the first and second electrodes 1 and 3. Such cells are often used for memory applications. In order to increase the capacity of the memory cell, in other words to increase the capacitance between the first and second electrodes 1 and 3, the surface area of one or both electrodes must be increased. The larger the surface area between the two electrodes, the greater the capacitance.

In the present invention, the surface area of both the first and second electrodes 1 and 3 is increased by increasing the roughness of the first electrode 1. Specifically, the generally smooth surface of the first electrode 1 is usually etched to form a large number of grooves and cuts in the first electrode 1. The insulating film 4 follows the new contour of the first electrode 1.
Similarly, when the second electrode 3 is formed, this also follows the contour left by the insulating film 4. In this way, the first
And the surface area between the second electrodes 1 and 3 is increased, resulting in an increase in capacitance. This also increases the storage capacity.

FIG. 2 illustrates a process for practicing the present invention. As shown in a), the first electrode 1 is formed on the oxide layer 5 and the silicon substrate 2 from which the oxide layer 5 has been removed by etching. In the preferred embodiment,
The first electrode is polysilicon provided by the CVD process. This polysilicon is then etched, preferably by a photoetching process, into the desired pattern as shown in b).

After etching the first electrode 1 to the desired shape, an oxide layer of less than 300 Å is deposited by CVD.
Formed by the process. This oxide layer has a surface of natural roughness when formed. In other words, the oxide layer shown in c) forms a mask of natural roughness. Using this naturally rough mask, the first electrode 1 is etched to its roughness state to form a surface having a significantly large surface area (d). In this way, the first electrode 1
Etching is standard in most device processes,
By the usual process of deposition and time etching,
It will be achieved.

Next, the remaining oxide layer is removed (e), and an insulating film 4 preferably made of silicon nitride is provided on the first electrode 1. Since the insulating film follows the contour of the first electrode 1, the rough surface and the increased surface area are retained.

Finally, the second electrode 3 is formed on the first electrode 1 and the insulating film 4. The second electrode 3 is a material that forms a capacitance with the polysilicon of the first electrode 1. In the preferred embodiment, the second electrode 3 is made of polysilicon or molybdenum.
or tungsten).

[0016]

As mentioned above, the present invention provides a simple way to increase the surface area of the capacitor electrode and hence the memory capacity using standard methods. The simple method of the present invention, namely the advantage of using the oxide layer as a mask and photoetching the first electrode prior to depositing the insulating film, makes the difficult and uncontrollable method used by the prior art. , Will be completely overwhelmed. Whereas temperature was extremely critical in the prior art, standard device processes are used in the present invention to produce capacitance comparable to that in the prior art.

[Brief description of drawings]

FIG. 1 shows a capacitor element with increased surface area according to the present invention.

FIG. 2 is a diagram showing a series of steps for manufacturing the capacitor element of FIG. 1 using the process of the present invention.

[Explanation of symbols]

 1 1st electrode 2 Silicon substrate 3 2nd electrode 4 Insulating film 5 Oxide layer

Claims (5)

[Claims] 1. A method of forming a semiconductor element storage capacitor having an increased surface area and increasing the storage capacity of the capacitor, the method comprising: forming a first capacitor electrode on a substrate of the semiconductor element; Forming a small oxide layer having a natural uneven surface on the capacitor electrode; using the natural uneven surface of the small oxide layer as a mask or etching pattern to remove the first capacitor electrode. Etching to form a rough surface; removing the remaining small oxide layer after the etching process of the first capacitor electrode is complete; thin insulating layer, such as nitrous oxide, on the first capacitor. Forming a second capacitor electrode on the thin insulating layer to form the first and second electrodes; Forming a capacitance between the capacitor electrodes. 2. A method of forming a storage capacitor of a semiconductor device having an increased surface area according to claim 1, and increasing the storage capacity of the capacitor, wherein the step of forming the first capacitor electrode further comprises: A method comprising etching a first capacitor electrode in a predetermined pattern. 3. A semiconductor element storage capacitor having increased storage capacity by increasing surface area: a semiconductor substrate; a first electrode formed on the semiconductor substrate and electrically coupled to the semiconductor substrate. The first electrode having a large number of recesses in the upper surface of the first electrode; a thin insulating layer formed on the first electrode; and the first electrode formed on the upper surface of the thin insulating layer. A second electrode forming a capacitance therewith;
Semiconductor element storage capacitor. 4. A semiconductor element storage capacitor having a storage capacity increased by increasing the surface area according to claim 3, wherein the first electrode is made of polysilicon. 5. A semiconductor device storage capacitor having increased storage capacity by increasing the surface area according to claim 3, wherein the second electrode is formed of polysilicon, molybdenum or tungsten together with the first electrode. Characterized by comprising a substance forming a capacitance,
Semiconductor element storage capacitor.