JPH0294466A - Double-capacitor and its manufacture - Google Patents

Abstract

PURPOSE: To double the charge accumulation capacity in the same area by forming parallel connected two capacitors on one element in an integrated circuit. CONSTITUTION: After the formation of a depletion layer 2 on the surface of a substrate 1, a trench is formed. Next, an oxide having ONO or NO structure is evaporated on the trench to form an insulating layer 10a. Next, impurities are implanted in the part below the trench to form a conductor 10b. Next, a metal is evaporated in the trench using lift off technology to form a common grounding conductor 20. Next, another insulating layer 30a is formed and after the formation of a connecting window in the layer 30a and the conductor 10b, the other conductor 30b is formed. Through these procedures, a capacitor made of the conductor 10b, the layer 10a and the conductor 20 as well as another capacitor made of the conductor 30b, the layer 10a and the conductor 20 are connected to one end of a transistor through the conductor 30b. Accordingly, the charge accumulation capacity can be doubled in the same area.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a double capacitor capable of distributing a large amount of charge in a limited capacitor area in the manufacture of ultra-highly integrated semiconductor devices, and a method for manufacturing the same. , two capacitors can be integrated into one device in an integrated circuit by using area compensation technology of stacked (staCk> type capacitor and trench type capacitor) and lift-off process technology in semiconductor manufacturing process. This invention relates to a double capacitor configured in parallel connection and a manufacturing method thereof.

As the degree of integration of semiconductor memory devices increases, device manufacturing technology tends to become smaller, and in particular, the size of the memory cell becomes an important factor controlling the chip size. A technology for forming a capacitor that can store a larger amount of charge in a capacitor region is the key to ultra-high density semiconductor manufacturing technology.

In a typical flat capacitor, the thickness of the insulating film is reduced to compensate for the reduction in the capacitor area, ie, the storage capacity, due to the reduction in cell size.

However, in order to satisfy the trend of increasing the M capacity of cell capacitors in megabit class memory devices, the thinning of dielectric films and the alternative application of materials with high dielectric constants have brought about their limits, and new structures have become necessary. capacitors have become necessary.

Recently, in order to overcome these limitations, research has been carried out on the introduction of a three-dimensionally structured cell cabaret.
This is actually the old trench type capacitor.

Compared to a trench-type capacitor that has a three-dimensional structure on the substrate side, a stacked capacitor that has a three-dimensional structure on the upper side of the substrate is formed with a three-layer polycrystalline silicon laminated structure for the gate of the transistor of the memory cell. Therefore, it is difficult to apply it to memory devices of grades 4 to 15 or higher due to the severe step difference between them and the limitations of dielectric film growth technology.

On the other hand, trench-type capacitors that use anisotropic silicon etching technology to increase the effective capacitor area are capable of achieving JMB class or higher integration by securing a sufficient capacitor area in a narrow planar area. It can be applied to memory zeros with degrees.

However, the trench type capacitor, which is essential for ultra-highly integrated memory devices of 4 Mb class or higher, also has the following problems. In other words, there are leakage current problems caused by narrowing the spacing between trenches in order to increase the concentration of metals, and process difficulties that require the use of complex processes, such as acceleration. There are problems such as damage and contamination of the device due to anisotropic etching that requires the use of charged particles, and problems such as soft errors caused by alpha particles.

As explained above, with the trend of decreasing minimum line width due to the increase in the degree of integration of semiconductor memory devices, technology for securing capacitor area has emerged as one of the factors controlling the degree of device integration. The 1-transistor-to-1-capacitor type stacked type and trench type capacitor fabrication techniques that have emerged as a result of this technology have the above-mentioned problems, and therefore a new type of capacitor area securing technique is required.

For this reason, the present invention utilizes lift-off technology to complement stacked and trench-type capacitor formation technologies, and is capable of producing not only tens of Mb class DRΔM but also ultra-highly integrated semiconductor memory IJ ffi devices. It is also applicable, and by forming two capacitors connected in parallel to one circuit element in a semiconductor, it provides a double capacitor that can have a storage capacity of 2 (more volume) than the conventional one in the same area. A second object of the present invention is to provide a method for easily forming a double capacitor without requiring sophisticated techniques.

In order to achieve the above-mentioned first object, the present invention comprises a common grounding conductor formed in a concave shape in a silicon valley region with a grounding terminal, and a first non-conductor and a first conductor in the lower part of the common grounding conductor. A first capantor is formed by forming a first capantor, and a second capanter is formed by forming a second nonconductor and a second conductor on top of the common ground conductor. It is characterized by having two capacitor structures connected in parallel to one element in a semiconductor integrated circuit through a conductor.

In order to achieve the above-mentioned second object, the present invention implants impurities onto a semiconductor substrate, etches the activated semiconductor substrate to a predetermined thickness to form a valley, and then A process of applying oxide to form a first nonconductor, and then injecting impurities into the silicon valley to form a first conductor, and grounding the double capacitor using a multi-liftoff process in the silicon valley. A process of forming a common ground conductor forming a terminal, and forming a second nonconductor by distributing oxide over the entire surface, and etching predetermined portions of the first and second nonconductors to form a common ground conductor within the semiconductor integrated circuit. The method is characterized by comprising the steps of: forming a connection window with one of the elements, and further forming a second conductor on top of the connection window and the second nonconductor.

The invention will now be described in more detail with reference to the embodiments of FIGS. 1 to 4 attached hereto.

1 to 3 show manufacturing process diagrams of a double capacitor according to the present invention.
Figures 28 to 2F are manufacturing process diagrams for manufacturing the first nonconductor 10a and the first conductor 10b constituting the capacitor. It is possible to utilize a triple weight, which is one of the U processes, or to use a lift-off process technique (particularly, compared to lift-off using conventional isotropic sputtering, which is a feature of the present invention)
, l Ii'Process technology that reversely utilizes 4 points) is used to manufacture convex i! Figures 3A to 3C show the second nonconductor 30a and second conductor 30b, which together with the common ground conductor 20 formed through the process shown in Figure 2, constitute the second capacitor/conductor. A manufacturing process diagram for manufacturing is shown.

FIG. 4 shows a circuit diagram of the double capacitor of the present invention manufactured by the manufacturing process shown in FIGS. 1 to 3 above.

FIG. 1A illustrates the stage of collapse of the depletion region 2, in which N-type impurities (or P-type impurities) are implanted onto the semiconductor substrate 1 to activate the surface of the semiconductor substrate 1.

FIG. 1B illustrates the formation stage of silicon valley 3.
After coating the photoresist film PRI on the sample shown in FIG. 1A, the semiconductor substrate 1 is etched to a predetermined thickness to form U-shaped silicon valleys 3. As shown in FIG. At this time, the height h of the silicon valley 3 may be variable depending on the storage capacity of the memory device.

FIG. 1C shows a step of forming the first nonconductor 10a. After removing the photoresist film PRI from the sample shown in FIG. 1B, an oxide is deposited to form the first nonconductor 10a. At this time, the thinner the oxide deposition thickness, the better;
The thickness is preferably about 180, and by using ONO or an oxide having a No structure as the material, the volume of 171 can be further increased with the same thickness.

FIG. 1O illustrates the step of forming the first conductor tab, in which a photoresist film PR2 is deposited on the sample shown in FIG. A first conductor 10b made of an impurity region is formed in a portion of the silicon valley 3 on the substrate side by implanting a P-type impurity. At this time, the impurity region constituting the first conductor 10b is infiltrated into the depletion region 2 and a region of the substrate l along the inner surface of the silicon valley 3 formed through the process steps shown in FIGS. 1A to 1C. This allows it to be connected to a transistor, which is an element within an integrated circuit.

Next, the process of forming the common ground conductor 20 that constitutes the first capacitor together with the first nonconductor 10a and the first conductor 10b formed through the above manufacturing process (Figures 1A to 1D) is shown in Figure 2. Explain through technology.

The technique of forming metal conductors by lift-off can avoid the etching damage that occurs during metal etching for metal patterns, and can not only easily form metal conductors, but also improve the process by eliminating the etching process. It is one of the semiconductor processes whose effectiveness is once again in the spotlight with the arrival of the submicron era.

The technology regarding lift-off is U.S. Patent No. 4218532.
It is described in the issue of ``Photolithographic etching technology for thin film deposition'', and the contents of the technology are explained as follows for reference.

The lift-off mask for vapor deposition of metal patterns has a triple-layered sandwich structure of a photoresist film (base layer), a metal film (intermediate layer), and a photoresist film (upper layer) on a substrate. Vapor deposition is done on the upper layer and the middle layer.

After sequentially etching the basal layer, the etching is performed through the etched passages. However, with this technology, there was a problem that metal was deposited on the side walls of the base layer (photoresist film), so various deposition methods such as anisotropic deposition technology were used to solve this problem. This is an actual situation where an attempt is being made. On the other hand, the lift-off process technology used in the present invention takes advantage of the above-mentioned sidewall deposition problem to create a common ground conductor with a concave metal pattern of several hundred amperes, which is unthinkable with current technology. 20 can be formed.

FIG. 2A illustrates the formation stage of the first photoresist film, which is the base layer 21.
After removing 2, a first photoresist film is applied evenly. The main purpose of forming the base layer 21 is to flatten the base t&1 which has a step, thereby eliminating the adverse effects of the step and preventing undercuts with the intermediate layer 22 in the subsequent process.
cut) to facilitate the formation and lift-off of the side wall portion of the common ground conductor 20.

FIG. 2B illustrates the steps of forming the metal film as the intermediate layer 22 and the second photoresist film as the upper layer 23. This is to perform a mask role, and the top layer 23, which is a shape layer, is to facilitate lift-off after forming the common ground conductor 20.

FIG. 2C illustrates the process of etching the upper layer 23, which is a photoresist film, and the intermediate layer 22, which is a metal film, to form a window.

FIG. 2D illustrates the etching step of the base layer 21, in which an undercut is created in order to adjust the height of the side wall portion of the common ground conductor 20 which will be formed in a subsequent process. This facilitates lift-off of the base layer 21-intermediate layer 22-top layer 23 sandwich structure lift-off mask after forming the common ground conductor 20.

FIG. 2E illustrates the steps of forming the common ground conductor 20, and shows the formation of a triple-layer mask without the need for an etching process for metal patterns that are difficult to etch, especially fine metal patterns with a width of several hundred lines. It is easily formed by depositing a metal material through an etched path.

At this time, as the method of vapor deposition of the metal batten, the side wall portion and the lower conductor of the common ground conductor 20 are formed by sputtering, for example, a method using isotropic sputtering. An evaporator can also be used to form the lower part. Further, as the material of the common ground conductor 20, tungsten, titanium, or a mixture of tungsten and titanium, which have excellent conductivity, is used, and the thickness thereof can be from 300 Å to about 1000 Å. The height of both side walls of the common ground conductor 200 depends on the application range of the memory device, the height of the silicon valley 3, the degree of undercut between the base layer 21 and the intermediate layer 22, and the variables of the isotropic sputtering deposition technique, for example. target height, cloud envelope gas,
The height can be adjusted by adjusting the degree of vacuum and the thickness of the lift-off mask.

FIG. 2F illustrates the process of removing the lift-off mask, showing the base layer 21. Middle layer 22. The upper layer 23 and the conductor layer 24 are removed all at once to complete the production of the desired common ground conductor 20. At this time, the mask can be easily removed by irradiating it with ultraviolet rays or baking it at a predetermined temperature, and the removal time can also be saved.

FIG. 3A illustrates the step of forming the second nonconductor 30a, in which an oxide is deposited on the sample shown in FIG. 2F, and
A second nonconductor 30a is formed. The material and deposition thickness of the second nonconductor 30a are the same as those of the first nonconductor 10a.

FIG. 3B illustrates the steps of forming a connection window 31 for connecting the second capacitor to one element in the integrated circuit, in which a photoresist film PR3 is applied, and then a portion where a connection Δ31 is formed is etched. A connecting window 31 is formed.

FIG. 3C shows the steps of forming the second conductor 30b. After removing the photoresist film PR3 from the sample shown in FIG. The double capacitor of the present invention is completed by etching the portion.

FIG. 4 shows an equivalent circuit of the double capacitor of the present invention manufactured through the process diagrams shown in FIGS. 1 to 3 above.

As shown in the drawing, the double capacitor of the present invention is connected in parallel to a transistor. That is, the first
A first capacitor consisting of a conductor tab, a second nonconductor 10a, and a common ground conductor 20 is connected to one end of the transistor through the first conductor 10b, and a second capacitor 30b, a second nonconductor tOa, and a common ground conductor 20 are connected to one end of the transistor through the first conductor 10b. A second capacitor consisting of is connected to one end of the transistor through the second conductor 30b to obtain a two capacitor structure connected in parallel to the transistor.

As explained above, according to the present invention, it is possible to increase the storage capacity by at least twice as much in the same area as that of a normal carrier, and thereby the size of the chip can also be reduced. .

That is, the double capacitor of the present invention can be applied to ultra-highly integrated semiconductor memory devices, for example, memory devices of tens of Mb class DRAM or larger, and will make a significant contribution to improving the degree of integration of future memory devices. expected to do so.

[Brief explanation of the drawing]

FIGS. 1 to 3 are diagrams illustrating the manufacturing process of a double capacitor according to the present invention, and FIG. 4 is a diagram illustrating an equal circuit for a double capacitor according to the present invention. 1: Semiconductor substrate 2: Depletion region 3; Silicon valley PRI, PH1, PH3: Photoresist film 10a:
First nonconductor 10b: first conductor 21; base layer (
(first photosensitive film) 22: Intermediate layer (metal film) 23: Upper layer (second
FX optical film) 24; conductor layer 20; common ground conductor 3
0a; second nonconductor 30b = second conductor 31;
Connecting window patent applicant Samsung Electronics Co., Ltd. Representative Masu Kobori Figure number ↓ Figure 0b Figure 0b

Claims (1)

[Claims] 1. A common ground conductor 20 formed in a concave shape in the silicon valley 3 is constituted by a ground terminal, and a first non-conductor 10a and a first conductor 10b are provided below the common ground conductor 20. A first capacitor formed by forming a second capacitor and a second capacitor formed by forming a second non-conductor 30a and a second conductor 30b on the common ground conductor 20, respectively, are connected to the first conductor 10b and the second conductor. A double capacitor characterized by having two capacitor structures connected in parallel to one element in a semiconductor integrated circuit through a capacitor 30b. 2. The first nonconductor 10a and the second nonconductor 30a are N
2. The double capacitor according to claim 1, wherein the double capacitor is made of O or an oxide having an ONO structure. 3. Claim 1, wherein the thickness of the first nonconductor 10a and the second nonconductor 30a is 60 Å to 180 Å.
Double capacitor as described. 4. The double capacitor according to claim 1, wherein the first conductor 10b is composed of the same type of impurity region as the depletion region 2. 5. The double capacitor according to claim 1, wherein the common ground conductor 20 is made of tungsten or titanium, or a mixture of tungsten and titanium, which have excellent electrical conductivity. 6. The thickness of the common ground conductor 20 is 60 Å to 180 Å.
The double capacitor according to claim 1, characterized in that: 7. The thickness and material of the second conductor 30b are approximately 200 mm.
The double capacitor according to claim 1, characterized in that it is made of polycrystalline silicon with a thickness of about 0 Å. 8. After implanting impurities onto the semiconductor substrate 1 and etching the activated semiconductor substrate 1 to a predetermined thickness to form silicon valleys 3, an oxide is applied thereon to form the first nonconductor 10a. and further injecting impurities into the silicon valley 3 side to form the first conductor 10b; and forming a common ground conductor that forms the ground terminal of the double capacitor by using a lift-off process technique using multilayers in the silicon valley 3. a step of forming 20;
A second nonconductor 3 is formed by coating the entire surface of the semiconductor substrate 1 with an oxide.
0a, and the first and second nonconductors 10a, 3
A predetermined portion of 0a is etched to form a connection window 31 to be connected to one element in the semiconductor integrated circuit, and furthermore, a connection window 31 and a second connection window 31 are formed.
A method for manufacturing a double capacitor, comprising a step of forming a second conductor 30b on top of the nonconductor 30a. 9. In order to connect the first capacitor to one element in the semiconductor integrated circuit, the impurity of the first conductor 10b is permeated into the depletion region 2 and the substrate 1 along the inner surface of the silicon valley 3. 9. The method for manufacturing a double capacitor according to claim 8. 10. The above common ground conductor 20 uses a three-layer lift-off mask with a sandwich structure of the first photoresist film (base layer; 21) - the metal film (middle layer; 22) - the second photoresist film (upper layer; 23). 9. The method of manufacturing a double capacitor according to claim 8, wherein the double capacitor is manufactured by: 11. The method of manufacturing a double capacitor according to claim 8, wherein a sputtering method is used as a deposition method for forming the common ground conductor 20. 12. The method of manufacturing a double capacitor according to claim 11, wherein an isotropic sputtering method is used as a deposition method for forming the common ground conductor 20. 13. The method of manufacturing a double capacitor according to claim 8, wherein in the step of removing the triple layer lift-off mask, ultraviolet ray irradiation or heat treatment is performed to facilitate lift-off and save process time.