JPH06349846A - Semiconductor device - Google Patents

Abstract

PURPOSE:To acquire a semiconductor device which can make generated heat at a junction part escape effectively. CONSTITUTION:A bump electrode 1 is provided in connection with an emitter electrode 3 immediately above a transistor element intrinsic operation part of a vertical structure and over a layer insulation film 11 and an upper layer wiring 4. The bump electrode 1 has a recessed cross sectional structure and has an H-shaped structure from an upper surface. A semiconductor device is formed by packaging a device in flip chip. Thereby, it is possible to realize effective heat dissipation, to greatly reduce heat resistance, to reduce an inductance of an lead out electrode and to enable its use as a power amplifier in a microwave band.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical structure transistor, and more particularly to a vertical structure transistor for power amplification in a microwave band and a semiconductor device using the same.

[0002]

2. Description of the Related Art Recently, a demand for a power amplification transistor in a microwave band has been increased, and in the microwave band, it has a high gain and a low output conductance as compared with a GaAs FET currently in practical use. A heterojunction bipolar transistor (hereinafter abbreviated as HBT) is drawing attention as a means for realizing a high efficiency amplifier (for example, NLWang et al., "Ultrahig").
h Power Efficiency Operation of Common-Emitter and
Common-Base HBT's at 10 GHz "IEEE Transaction on
Microwave Theory and Techniques, vol.38, No.10, pp1
381-1389).

As is generally known, the above HBT
Operates at a high current density, so that the heat generation density is inevitably high. Therefore, in order to operate properly, the heat generated at the junction (pn junction) formed on the substrate surface must be efficiently released to the outside of the semiconductor substrate. The above-mentioned document adopts a means for allowing the heat generated at the joint to escape to the back side of the substrate. That is, while thinly cutting the semiconductor substrate,
A via hole (a hole penetrating from the back side of the substrate to the front side of the substrate) is provided just below the electrode drawn from the joint to the periphery, and a metal material having good thermal conductivity is embedded in the via hole (hereinafter, referred to as a conventional method). (I).

On the other hand, when the electrode structure of the bipolar transistor is widely investigated not only for the microwave band, but as shown in Japanese Patent Laid-Open No. 3-3335, the junction formed on the surface of the semiconductor substrate (semiconductor substrate (collector ), A substantially rectangular base region is provided, and an emitter region having an interdigital (comb-shaped) structure is provided in the base region), and bump electrodes protruding from the substrate surface are provided on the base region. Specifically, the thin film electrodes are provided in almost all regions of the base region and the emitter region, and the bump electrodes are provided on a portion (leading electrode portion) having a predetermined area other than the interdigital structure portion in each thin film electrode. There is. In this transistor, through the bump electrode,
It is possible to efficiently dissipate the heat generated at the joint to the outside of the substrate (hereinafter referred to as the conventional method (ii)).

On the other hand, Japanese Patent Application No. 4-172 filed by the present inventors.
645 shows a structure in which a bump electrode is provided immediately above a transistor element intrinsic operation part having a junction part divided into a plurality of parts (hereinafter referred to as a conventional method (iii)). -249400 shows a structure in which an electrode is drawn out in a direction orthogonal to a finger-shaped emitter and a bump is provided thereon (hereinafter referred to as a conventional method (iv)).

[0006]

However, the conventional method (i) has the following problems.

Since the via hole is opened in addition to thinly cutting the substrate, the wafer is cracked and chipped to lower the yield.

The via hole is separated by at least 5 μm or more from the joint (heat generating portion) due to the restriction of processing accuracy. Therefore, it is difficult to effectively reduce the thermal resistance.

In the microwave band, the emitter lead-out line from the junction has a non-negligible inductance and acts as a feedback inductance to cause a loss.

Further, the above conventional method (ii) has the following problems.

Since it is assumed that there is a lead-out electrode portion having bumps, which is different from the interdigital emitter / base region which can be said to be the intrinsic operation region, the parasitic capacitance of the device (Cbe (base-emitter capacitance)) , Cb
There is a limit to the reduction of c (base-collector capacitance), Cec (emitter-collector capacitance), and the same meaning below, and it is difficult to achieve high characteristics.

In practice, it is impossible to form bumps on each electrode in the case of a high frequency device because the electrodes are small.

Since the emitter electrode is taken out from the bump electrode existing apart from the intrinsic operation region, the emitter inductance cannot be reduced sufficiently.

Since many problems occur as described above, the HBT could not be put to practical use in the past for power amplification in the microwave band.

Further, in the conventional method (iii), most of the above problems are solved, but the heat dissipation is not sufficient because only one bump exists for a plurality of fingers.

Further, in the conventional method (iv), most of the above problems can be solved, but since the distance between the finger portion and the bump is large, the heat radiation is still insufficient.

Therefore, an object of the present invention is to more efficiently dissipate the heat generated at the junction formed on the substrate surface, reduce the inductance of the lead wire, reduce the parasitic capacitance, etc., and to amplify the power in the microwave band. It is an object of the present invention to provide a vertical structure transistor which can be put to practical use for use and a semiconductor device using the same.

[0018]

SUMMARY OF THE INVENTION According to the present invention, bump electrodes are arranged substantially orthogonal to an intrinsic operating portion of a finger-shaped vertical structure transistor formed on a substrate and extending to a non-intrinsic operating portion of the vertical structure transistor. It is characterized by being installed.

Further, the present invention is characterized in that the width dimension of the bump electrode in the finger longitudinal direction of the intrinsic operating portion of the finger-shaped vertical structure transistor is larger than the width dimension of the bump electrode of the non-intrinsic operating portion. It is a thing.

Further, the present invention is characterized in that the height of the bump electrode immediately above the intrinsic operating portion of the finger-shaped vertical structure transistor is lower than the height of the bump electrode of the non-intrinsic operating portion.

Further, according to the present invention, the dimension of the finger width in the direction orthogonal to the finger longitudinal direction of the intrinsic operating portion of the finger-shaped vertical structure transistor is 1 μm to 1 respectively.
It is characterized by being 0 μm.

Further, the present invention is characterized in that the dimension in the finger longitudinal direction of the intrinsic operating portion of the finger-shaped vertical structure transistor and the dimension in the finger longitudinal direction of the bump electrode are substantially the same. is there.

Further, the present invention is characterized in that the bump electrodes of the finger-shaped vertical structure transistors are connected to each other on the same substrate.

Furthermore, the present invention is characterized in that a semiconductor device provided with bump electrodes of finger-shaped vertical structure transistors is flip-chip mounted on an AlN substrate having a metal pattern.

Furthermore, the present invention is characterized in that the gap between the substrate of one semiconductor device and the other AlN substrate is filled with an epoxy resin.

Furthermore, the present invention is characterized in that the amount of bump electrode collapse during flip chip mounting of a semiconductor device is larger than the difference between the height immediately above the intrinsic operating portion and the height of the non-intrinsic operating portion. Is.

Furthermore, according to the present invention, the bump electrode A
The ground width to the 1N substrate is twice or more than the connection height between the substrate and the AlN substrate.

Furthermore, the tilt angle of the bump electrode with respect to the AlN substrate after flip-chip mounting is 45 ° or more.

[0029]

The bump electrode provided immediately above the intrinsic operating portion of the finger-shaped vertical structure transistor is located extremely close to the heat generating portion. For example, in the case of an emitter-top type HBT, the distance between the bump electrode and the heat generating portion (base / collector junction) is the sum of the emitter thickness and the base thickness (about 0.5 μm).
Becomes That is, when a conventional via hole is provided,
Alternatively, as compared with the case where heat is dissipated via bumps existing on the extraction electrode portion, the extraction distance is about 1/10.

Further, since the bump electrode exists so as to straddle the non-intrinsic operation portion with respect to the intrinsic operation portion of the single finger-shaped vertical structure transistor which is a heat generation source, it is larger than the heat generation source. The bumps will be present, and there will be no other heat generating sources in the vicinity, which will interfere with the heat flow. For this reason, heat can be diffused in the bumps directly above the fingers. Therefore, the thermal resistance can be reduced as compared with the conventional method.

Also, by connecting the bump electrodes to a heat sink, the heat dissipation efficiency is remarkably increased and the heat resistance is significantly reduced. At the same time at the shortest distance from the emitter,
In addition, since it is grounded with a thick ground wire, the inductance is reduced to a minimum.

If the bump electrode extends over the non-intrinsic operating portion located in the direction orthogonal to the longitudinal direction of the finger in the intrinsic operating portion of the finger-shaped vertical structure transistor, on the contrary, the bump operates in the intrinsic operating state. The parasitic capacitances Cbe and Cce are smaller than those in the case where the portions are located in the finger longitudinal direction. Therefore,
This vertical structure transistor can be put to practical use for power amplification in the microwave band.

Further, in a portion where the bump electrode is out of the element intrinsic operation portion of the finger-shaped vertical structure transistor, the width dimension of the bump electrode is set right above the intrinsic operation portion of the finger-shaped vertical structure transistor. A larger bump electrode width dimension increases the bump cross-sectional area without increasing the parasitic capacitance, which contributes to a reduction in thermal resistance.

Also, the bump electrode is added to the bump electrode in the flip chip bonding process by providing an insulator just below the portion of the finger-shaped vertical structure transistor which is exposed from the intrinsic operating portion. It is possible to prevent the pressure from concentrating on the finger portions, and thus to avoid a short mode failure due to crushing of the electrodes extending in the wing shape on the left and right of the intrinsic operation portion in the bonding process.

Further, the widthwise dimension of the intrinsic operating portion of the finger-shaped vertical structure transistor is 1 μm to 10 μm.
It is preferable to set it in the range of m for the following reasons.

In this structure, heat is radiated through the base / collector junction, which is a heat source, the emitter, the bump electrode, and the bump. The bump electrode contacts the emitter electrode corresponding to the intrinsic operating portion of the vertical structure transistor through the opening of the insulator existing so as to surround the emitter electrode. In the current photolithography technology, if the width in the width direction is 1 μm or less, if the alignment margin is subtracted, a contact area sufficient for heat dissipation and electrical connection cannot be obtained. Therefore, it is desirable that the dimension of the transistor element intrinsic operating portion in the width direction is 1 μm or more.

On the other hand, the upper limit of the widthwise dimension of the intrinsic operating portion of the finger-shaped vertical structure transistor is limited by the emitter crowding effect. When the dimension of the intrinsic operating portion in the width direction is 10 μm or more, the function as a high frequency device is significantly reduced due to the above effect.

In FIG. 6, the current density at the center of the emitter finger is 2 × 10 ⁴ Acm which is a value at which the HBT operates sufficiently.
The relation between the current density at the edge portion of the emitter finger portion and the emitter width x _E of the emitter finger portion in the case of selecting ^-2 is shown. When the emitter width x _E of the emitter finger portion is 10 μm, the current density in the central portion reaches about 3 times that in the edge portion. Above this, the central portion of the emitter finger portion no longer operates as a transistor and acts as a parasitic capacitance. Interfere with movement. Therefore, the emitter width x _E is 10
μm or less is desirable.

Further, the joint portion is formed of an interface of the emitter region provided in the base region, and the size of the emitter region and the width size of the bump electrode (the size of the cross section of the portion contacting the substrate side) are substantially equal to each other. If it does, it has the following advantages over the case of disagreement.

First, when the width dimension of the bump electrode is smaller than the dimension of the emitter region, the heat dissipation efficiency of the portion of the emitter region protruding to the periphery of the bump electrode is reduced. On the other hand, when the two dimensions are the same, heat is efficiently dissipated in the entire emitter region. On the other hand, when the width dimension of the bump electrode is larger than the dimension of the emitter region, the bump electrode joined to the emitter protrudes into the base region and the collector region, increasing parasitic capacitances Cbe and Cce and deteriorating the device characteristics. . On the other hand, when the two dimensions are the same, such parasitic capacitance can be suppressed at a small level. Therefore, the device characteristics are improved.

In addition, the bump height immediately above the intrinsic operating portion of the finger-shaped vertical structure transistor, or the portion directly insulated from the intrinsic operating portion of the finger-shaped vertical structure transistor and the other electrode by the insulator. , If the bumps are lower than the other parts, the load applied to the intrinsic operation part of the vertical structure transistor or the non-intrinsic operation part of the insulator and the transistor immediately below the insulator is reduced during flip chip bonding, resulting in device destruction. It hardly occurs and contributes to the improvement of yield.

Further, when the bump electrodes are connected to each other on the chip, the flip chip bonding area of the bump electrodes is increased, the thermal resistance is further lowered, and the heat transfer between the elements is improved. Thus, thermal runaway is less likely to occur even when a part of the plurality of intrinsic motion parts locally generates heat.

Further, the chip constituting the vertical structure transistor has a metal pattern for electrode connection A
It is desirable to form a semiconductor device by flip-chip mounting on the 1N substrate in order to prevent heat dissipation and reduce ground inductance.

Further, by filling the resin directly under the chip, it is possible to improve mechanical strength, reliability, and thermal resistance when flip chip bonding is performed.

Further, the bump collapse amount when flip-chip mounting the chip having the above bump electrodes is determined as the intrinsic operating portion of the finger-shaped vertical structure transistor or the finger-shaped transistor element intrinsic operating portion and the insulator. With the bump height directly above the part insulated from other electrodes and the height difference from the other part of the bump, it can be selected as the intrinsic operating part of the vertical structure transistor when flip-chip mounting. While minimizing such pressure,
The upper part of the element, which is most important for heat dissipation, can be bonded to the AlN substrate.

Most of the heat generated from the intrinsic operation portion of the finger-shaped vertical structure transistor is approximately 4 in the bump.
Disperses while diffusing in the 5 ° direction. Therefore, by setting the ground width of the bump electrode to the AlN substrate to be larger than twice the substrate connection height, it is possible to suppress an increase in thermal resistance inside the bump.

With the above operation, the thermal resistance can be reduced as compared with the conventional method. According to the study by the present inventors,
The present invention has a thermal resistance reducing effect as shown in FIG. 5 as compared with the conventional method. That is, the conventional methods (i), (iii), (i
Compared with v), the thermal resistance can be significantly reduced.

[0048]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a vertical structure transistor according to the present invention and a semiconductor device using the same will be described below with reference to the drawings.

A cross-sectional view of a vertical structure transistor provided with bump electrodes, which is an embodiment of the present invention, is shown in FIG. 1 (a), and a top view thereof is shown in FIG. 1 (b). Here, 1 is a bump electrode, 3 is an emitter electrode, 4 is an upper layer wiring, 5 is an emitter finger portion, 6 is a base electrode, 7 is a collector layer, 8 is a base layer, 9 is a subcollector layer, 10 is GaAs, etc. Semi-insulating substrate, 11 is an interlayer insulating film made of polyimide, 12
Is a collector electrode, 13 is a base extraction electrode, and 14 is a collector extraction electrode. In this embodiment, an npn emitter-up type HBT for microwave power amplification is used as a vertical structure transistor on the semi-insulating substrate 10. That is, the emitter finger portion 5 (which is a mesa shape formed by the mesa etching of the semiconductor layer) and the base layer 8 and the collector layer 7 and the subcollector layer 9 which are formed stepwise are provided on the subcollector layer 9. The two collector electrodes 12 thus formed are connected to each other by a collector extraction electrode 14, and the two base electrodes 6 provided on the base layer 8 are connected to each other by a base extraction electrode 13.
One emitter electrode 3 is connected to the bump electrode 1. Further, the bump electrode 1 is insulated from the base electrode 6 and the collector electrode 12, which are other electrodes, by the interlayer insulating film 11 made of polyimide just below the portion that goes out from the intrinsic operating portion of the finger-shaped vertical structure transistor. There is. An interlayer insulating film 11 is provided below the base extraction electrode 13 and the collector extraction electrode 14 in the region other than the bump electrode 1 to insulate the semiconductor layer. In the drawings, the same members will be denoted by the same reference symbols. Figure 1
As is clearer, immediately above the intrinsic operating portion (the operating area up to the base-emitter junction region and the collector layer) of the finger-shaped vertical structure transistor and the finger longitudinal direction of the intrinsic operating portion (in FIG. The bump electrode 1 is provided so as to straddle a non-intrinsic operating portion (a region other than the intrinsic operating portion) located in a direction orthogonal to the (vertical direction).

Next, the shape and main dimensions of this embodiment shown in FIG. 1 will be described.

First, in FIG. 1A, the bump electrode 1 on the vertical structure transistor has a concave sectional shape because of the upper layer wiring 4. The height of the bump electrode 1 at the portion directly above the intrinsic operating portion of the vertical structure transistor and across the interlayer insulating film 11 is 25 μm, which is lower than the bump electrode height of 29 μm at the non-intrinsic operating portion of the transistor. .

Further, in FIG. 1B, the bump electrode 1
Is a bump width dimension in the non-intrinsic operating portion of the finger-shaped vertical structure transistor which is exposed from the intrinsic operating portion (see FIG. 1).
The vertical dimension of the paper in (b) is the width of the bump just above the intrinsic operating portion of the finger-shaped vertical structure transistor (the vertical dimension of the paper in FIG. 1B).
It is large compared to. That is, the bump electrode 1 has a substantially H shape when viewed from above. The substantially H-shaped configuration can increase the area of the bump electrode without increasing the parasitic capacitance, so that the thermal resistance can be effectively reduced.

Further, the widthwise dimension of the intrinsic operating portion of the finger-shaped vertical structure transistor (the dimension in the left-right direction of the paper in FIG. 1A) is set to 5 μm. The bump electrode is formed by gold plating. The lengthwise dimension (dimension in the vertical direction of the paper in FIG. 1B) of the intrinsic operating portion of the finger-shaped vertical transistor is 20 μm.
The width of the bump electrode 1 just above the finger is 16 μm. After the flip-chip mounting, the bumps are crushed and spread, and the width dimension of the bump electrode is substantially the same as the longitudinal dimension of the finger-shaped transistor element intrinsic operating portion.

Next, FIG. 2A is a sectional view of a vertical structure transistor having bump electrodes according to another embodiment of the present invention.
2 and a top view thereof are shown in FIG. Here, FIG.
The same symbols as the respective symbols of 1 indicate the same members. The difference from the structure shown in FIG. 1 is that the upper layer wiring 4 covers the portion directly above the intrinsic operating portion of the vertical structure transistor and the interlayer insulating film 11, and the upper layer wiring 4 is connected to the emitter electrode 3.
Therefore, the difference in cross-sectional structure from FIG. 1 is that the bump electrode 1 on the vertical structure transistor has a convex shape.
The shape of the bump electrode in flip-chip mounting described later may be either shape shown in FIG. 1 or FIG. 2, but if stress relaxation to the vertical structure transistor is important, the bump shape of FIG. preferable. Even if a bump electrode is provided without providing the upper layer wiring 4, the bump electrode has a convex shape.

Next, FIG. 3 is a cross-sectional view of a semiconductor device after flip-chip mounting of a chip including the vertical structure transistor having the bump electrode shown in FIG. 1 on an AlN substrate having a metal pattern. Show. Where 15 is Al
A metal electrode on the N substrate, 16 is an AlN substrate, 17 is a transistor portion showing a vertical structure transistor, 18 is an electrode extraction bump (for example, a base in the case of a single transistor), 19 is a potential different from that of the electrode extraction bump 18. The electrode lead-out bumps (for example, a collector in the case of a single transistor) are shown, and other reference numerals are the same as those in FIG. Here, the area directly under the semi-insulating substrate 10 is filled with epoxy resin. Chip provided with bump electrode 1 (transistor portion having bump electrode on semi-insulating substrate 10)
The bump collapse amount when flip chip mounting is 9 μm
Then, the bump height immediately above the finger-shaped vertical structure transistor element intrinsic operation part or the intrinsic operation part of the finger-shaped vertical structure transistor and the portion insulated from other electrodes by the interlayer insulating film, The height difference from the portion is set to be larger than 4 μm. A of the bump electrode 1
The ground width to the IN board 16 is 42 μm, and the board connection height is 2
Greater than twice 0 μm.

Next, a method of manufacturing the npn emitter-up type HBT used as the vertical structure transistor shown in FIG. 1 will be described.

First, an AlGaAs / GaAs npn emitter-up type HBT is formed on a semi-insulating substrate by using a well-known method (for example, Technical Report of the Institute of Electronics and Communication Engineers ED90-135). npn emitter up type H
BT is a vertical structure transistor, and as shown in FIG. 1, is formed by a subcollector layer 9, a collector layer 7, a base layer 8 and an emitter layer from the bottom.

After that, polyimide is used as the interlayer insulating film 11, the base electrode 6 and the collector electrode 12 are covered, and the region right above the emitter is opened. (Contact parts to the base and collector are drawn out by using metal wiring, and lead-out electrodes are provided at distant places.) Then, a bump electrode made of Ti / Pt / Au is formed in a substantially H-shape directly above the transistor element. To form a pattern. This step also serves as the step of forming the lower layer wiring, and at the same time, the lower layer wiring is formed and becomes the extraction electrode.

Thereafter, SiN _{x (} not shown) is deposited as a passivation and MIM film, and openings are formed in the portions where the bump electrodes are provided and the contact portions with the upper wiring by photolithography and buffer hydrofluoric acid etching.

Thereafter, a protective resist is applied, and a region where an upper layer wiring is to be provided is opened by photolithography. At this time, the upper layer wiring is not provided at an appropriate distance (3 to 10 μm) including immediately above the intrinsic operating portion of the transistor, and the pattern is arranged so that the upper layer wiring is provided in the immediate vicinity thereof.

Then, Ti / which is a part of the upper wiring is
Au is vapor-deposited on the entire surface to serve as a plating electrode. Thereafter, an upper layer wiring plating resist is applied, and only the portion where the upper layer wiring is provided is opened using a photolithography technique.

Thereafter, an upper wiring (9 μm) made of Au is formed by a plating method. Through this step, the portion directly above the intrinsic operating portion of the vertical structure transistor (upper layer wiring 9 μm
m) − (transistor mesa height˜3 μm) − (polyimide height˜2 μm) = ˜4 μm.

Thereafter, the upper layer wiring plating resist was removed, Au other than the lower layer wiring was removed by etching, and then Ti other than the lower layer wiring was removed by lift-off with the protective resist.

After that, a protective resist is applied, and a substantially H-shaped opening is provided in the region where the bump electrode is to be provided by photolithography. After that, Ti / Au is vapor-deposited on the entire surface to form a plating electrode.

Thereafter, a resist for bump plating is applied, and a photolithography technique is used to open only a portion where a bump electrode is provided.

Thereafter, Au bumps are formed by plating. The bumps are substantially H-shaped, and the vertical width dimension of the substantially H-shaped central portion (dimension in the vertical direction of the paper in FIG. 1B) is 16 μm, and the horizontal width dimension of the H-shaped portion (FIG. 1).
In (b), the vertical dimension of the paper surface is 40 μm as the finished dimension after plating, and the Au bump height is 20 μm.

The shape of the bump from the upper surface is substantially H-shaped in order to enhance the heat dissipation effect, but it is not limited to the substantially H-shaped shape, and it is just above the intrinsic operating portion of the finger-shaped vertical structure transistor and the finger longitudinal direction. It suffices that it is provided so as to straddle the vertical axis and not to protrude from the intrinsic operating portion of the finger-shaped vertical structure transistor.

After that, the bump plating resist was removed, Au other than immediately below the bump was removed by etching, and then Ti other than immediately below the bump was removed by lift-off with a protective resist. After that, lapping and dicing were performed by a usual method to complete a semiconductor chip.

The semiconductor chip manufactured by the above method was flip-chip mounted on an AlN substrate having a metal pattern using a flip-chip bonder.
The pulse heating method was used during bonding to reduce the heat applied to the device as much as possible. The pressure is set so that the bump collapse amount during bonding is 9 μm (in the structure shown in FIG. 1,
2.2 kg, 3.0 k in the structure shown in FIG. 4 described later
g) and heat temperature of 350 ° C. and time of 5 sec. As a result, the bump collapse amount when flip-chip mounting a chip including bump electrodes is different depending on whether the intrinsic operating portion of the finger-shaped vertical structure transistor or the intrinsic operating portion of the finger-shaped vertical structure transistor and the interlayer insulator. Difference between the height of the bump directly above the part insulated from the electrode and the height of the other part of the bump is larger than 4 μm 9
It was possible to set it to μm. Although the bump crushing amount is set so that the concave portion of the bump electrode is crushed in the present embodiment, it is preferable to crush the bump electrode in consideration of heat dissipation efficiency, but the bump crushing amount may be set so as not to be completely crushed.

As described above, the bump electrode is substantially H-shaped, and the vertical width dimension of the H-shaped central portion is 16 μm.
Although the lateral width of the mold is 40 μm, the bump shape is changed by flip chip bonding, the vertical width of the H-shaped center is 18 μm, the lateral width of the H-shaped is 42 μm, and the connection height is It became 20 μm. After that, a small amount of liquid epoxy resin is dropped on the end portion of the chip, and the epoxy resin is separated from the chip and AlN by the capillary phenomenon.
It does not enter the space between the substrates and trap air bubbles. Then, the resin is cured in a nitrogen atmosphere at 150 ° C. for 2 hours to complete the semiconductor device.

Next, a sectional view of a vertical structure transistor provided with a plurality of bump electrodes is shown in FIG. 4 (a), and a top view thereof is shown in FIG. 4 (b). Here, reference numeral 20 denotes a bump that connects the bumps to each other, and other reference numerals are the same as those in FIG. It is manufactured by forming a bump plating pattern so that the plurality of H-shaped bumps directly above the finger-shaped vertical structure transistors are connected to each other by the bumps 20. That is, it can be manufactured by the same steps as those in the above-described embodiments.

In the above embodiment, the collector, the base and the emitter are formed in this order on the semiconductor substrate, but conversely, the emitter, the base and the collector may be formed in this order on the semiconductor substrate. Further, the conductivity type of the semiconductor layer may be reversed from the conductivity type of the embodiment. Regarding the structure of the bipolar transistor, a so-called single heterobipolar transistor (SHBT) in which only the emitter has a large bandgap or a so-called double heterobipolar transistor (DHBT) in which a wide bandgap material is used for the collector may also be used. In addition, O ⁺ , B ⁺ , H
A method of implanting ⁺ ions or the like directly below the external base to reduce C _bc , or a combination with an element isolation method by ion implantation is also possible.

In the above embodiment, H is used as the active element.
Although the BT is used, the element to be used is not limited to this. For example, in a vertical structure element, a normal bipolar transistor, a thyristor, a HET (Hot Electron Transistor), a resonance tunnel transistor, or the like may be used. Effect Transistor), lateral bipolar transistor, HEMT (High Electron Mobility Transi)
Needless to say, it is also possible to combine them, or to combine them, or to combine a light emitting element and a light receiving element.

In the above embodiment, the microwave power amplifying transistor is taken as an example, but it goes without saying that it can be applied to an MMIC, an ultra-high speed integrated circuit and the like. In the present embodiment, the bump electrode also functions as an emitter electrode, but for example, the MMIC (Mon
Depending on the application such as olithic microwave IC) and ultra high speed integrated circuit, it may be inconvenient if the bump electrode is an emitter (source). In such a case, use the bump electrode as the base (gate) or collector (drain).
It may be used only for heat dissipation by a method such as connecting to, or not using as an electrode, but via an insulating film.

The semiconductor chip used is not limited to this embodiment (GaAs), but InP, Si
It may be composed of another compound semiconductor such as C or GaP, or may be an elemental semiconductor such as C or Si. Also, the device itself is made of, for example, InGaAs (P) / InAlAs
It is needless to say that other lattice matching system such as a system, InGaAs (P) / InP system, etc., or a lattice mismatching system such as InGaAs / AlGaAs may be used.

Although the AlN substrate having the metal pattern is used as the flip chip substrate in the above embodiment, it goes without saying that another material may be used as long as it has a good thermal conductivity. . Further, the flip chip substrate used in this embodiment is not necessarily a plane single plate, and may have so-called through holes and via holes, and may have a structure other than a plane such as a laminated substrate.

In the above embodiment, the element substrate (chip)
Although the heat is not specifically radiated from the back surface side of the above, it may be combined with a means for radiating the heat through solder for heat transfer, a case cap or the like by cutting the back surface of the chip thin.

[0078]

As described above, according to the present invention, it is possible to construct the vertical structure transistor capable of radiating heat from the surface of the semiconductor chip very efficiently and the semiconductor device using the same. Therefore, according to the present invention, a semiconductor device having low thermal resistance can be formed with high yield and at low cost.

The present invention makes it possible to significantly reduce the thermal resistance of a semiconductor device. In particular, it has a significant industrial ripple effect in the sense of paving the way for the practical application of HBTs for microwave power amplification. .

[Brief description of drawings]

FIG. 1A is a diagram showing a cross-sectional structure of a vertical structure transistor provided with a bump electrode according to an embodiment of the present invention. (B) It is a figure which shows the upper surface structure of the vertical structure transistor which provided the bump electrode which concerns on one Example of this invention.

FIG. 2 (a) is a view showing a cross-sectional structure of a vertical structure transistor provided with bump electrodes according to another embodiment of the present invention. (B) It is a figure which shows the upper surface structure of the vertical structure transistor which provided the bump electrode which concerns on the other Example of this invention.

FIG. 3 is a diagram showing a sectional structure of a semiconductor device after flip-chip mounting according to an embodiment of the present invention.

FIG. 4A is a diagram showing a cross-sectional structure of a vertical structure transistor provided with a bump electrode according to still another embodiment of the present invention. (B) It is a figure which shows the upper surface structure of the vertical structure transistor which provided the bump electrode which concerns on the other Example of this invention.

FIG. 5 is a diagram showing the results of thermal resistance comparing the present invention with the prior art.

FIG. 6 is a diagram showing a relationship between a current density at an emitter edge and an emitter width.

[Explanation of symbols]

 1 bump electrode 3 emitter electrode 4 upper layer wiring 5 emitter finger 6 base electrode 7 collector layer 8 base layer 9 subcollector layer 10 semi-insulating substrate 11 interlayer insulating film 12 collector electrode 13 base extraction electrode 14 collector extraction electrode 15 AlN on substrate Metal electrode 16 AlN substrate 17 Transistor part 18 Electrode extraction bump 19 Potential extraction bump of different potential 20 Bump connecting bumps

Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display area H01L 29/205

Claims (11)

[Claims] 1. A semiconductor characterized in that bump electrodes are arranged substantially orthogonal to an intrinsic operating portion of a finger-shaped vertical structure transistor formed on a substrate and extending to a non-intrinsic operating portion of the vertical structure transistor. apparatus. 2. The width dimension of the bump electrode in the finger longitudinal direction of the intrinsic operating portion of the finger-shaped vertical structure transistor is larger than the width dimension of the bump electrode of the non-intrinsic operating portion. The semiconductor device described. 3. The height of the bump electrode immediately above the intrinsic operating portion of the finger-shaped vertical structure transistor is lower than the height of the bump electrode of the non-intrinsic operating portion. Semiconductor device. 4. The dimension of the finger width in the direction orthogonal to the finger longitudinal direction of the intrinsically operating portion of the finger-shaped vertical structure transistor is 1 μm to 10 μm, respectively. Item 3
The semiconductor device according to. 5. The dimension of the intrinsic operating portion of the finger-shaped vertical structure transistor in the finger longitudinal direction and the dimension of the bump electrode in the finger longitudinal direction are substantially the same. The semiconductor device according to claim 2 or claim 3. 6. Claim 1 or claim 2 or claim 3.
The semiconductor device according to the item (1), wherein bump electrodes are connected to each other on the same substrate. 7. Claim 1 or claim 2 or claim 3.
Alternatively, the semiconductor device according to claim 6 is flip-chip mounted on an AlN substrate having a metal pattern. 8. A semiconductor device substrate on one side and AlN on the other side.
The semiconductor device according to claim 7, wherein an epoxy resin is filled in a gap with the substrate. 9. A semiconductor device according to claim 3, wherein the bump electrode is crushed when the semiconductor device according to claim 3 is flip-chip mounted, and is larger than the difference between the height immediately above the intrinsic operating portion and the height of the non-intrinsic operating portion. apparatus. 10. The semiconductor device according to claim 7, wherein a ground width of the bump electrode to the AlN substrate is twice or more than a connection height between the substrate and the AlN substrate. 11. The semiconductor device according to claim 7, wherein the inclination angle of the bump electrode with respect to the AlN substrate after flip-chip mounting is 45 ° or more.