JP2006114732A - Semiconductor device, manufacturing method thereof, and semiconductor module - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can satisfy the securing of its mechanical strength, its miniaturization, and its thermal stability, with respect to the semiconductor device comprising active elements, passive elements, wiring portions, and electrodes. <P>SOLUTION: With respect to the semiconductor device, there is provided in the position of an opening present just under its active element a conductor layer for filling therewith the opening, and other conductor layers are also formed in the positions having no opening. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a small and highly reliable semiconductor device, a manufacturing method thereof, and a semiconductor module using the same.

  In recent years, with rapid growth in demand for mobile communication devices, research and development of power amplifiers used in communication devices has been actively conducted. In order to meet the demand for miniaturization of communication devices, a monolithic microwave integrated circuit (MMIC) in which a semiconductor chip is miniaturized, a passive element is incorporated, and a device is miniaturized is incorporated in a power amplifier module. As a transistor used therein, a heterojunction bipolar transistor (HBT) having a high power density and capable of being downsized is mainly used. In the present specification, hereinafter, the monolithic microwave integrated circuit is abbreviated as MMIC, and the heterojunction bipolar transistor is abbreviated as HBT.

  Among them, particularly in a power amplifier module aimed at miniaturization, an MMIC is mounted face-up on a ceramic substrate using metal bumps. Representative examples of this technique can be found in, for example, Japanese Patent Application Laid-Open No. 6-204449 (Patent Document 1) and Japanese Patent Application Laid-Open No. 2001-210667 (Patent Document 2).

JP-A-6-204449.

Japanese Patent Laid-Open No. 2001-210677.

  The structure of the semiconductor module using the HBT known so far will be considered from a practical aspect, and the problems will be clarified. First, a semiconductor device in which an electrode, a wiring, or a passive element is provided in addition to an active element on a semiconductor substrate, and an electrode provided in the semiconductor device is used as a connection point, and a thick conductor layer commonly called a bump is used to form a module. This is a face-down configuration for electrical connection to the substrate. In this case, structural difficulties arise in that the thickness of the connecting conductor layer from each element or each electric member to the module substrate is different. That is, the thickness of each element or each electric member is different. Therefore, the mechanical strength of the MMIC itself cannot be ensured, which causes a problem in reliability. Furthermore, since the semiconductor substrate side and the MMIC substrate side are connected via bumps, electrical connection points must be formed on both side surfaces. For this reason, a resistance component is generated in proportion to the number of connection points. In addition, there are many electrical connection points, and there is a difficulty in terms of durability associated therewith.

  From a practical point of view, there are the following difficulties in use. For example, when the semiconductor substrate is mounted on the MMIC substrate in the form of a face-up bump, other passive elements may naturally be formed on the back surface of the semiconductor substrate, that is, the surface on the bump forming side, before the bump is formed. I can't. Therefore, wiring using the back surface of the semiconductor substrate is impossible. In addition, when only the bumps for electrically connecting various elements are formed on the back surface of the semiconductor substrate instead of the openings, there is no heat dissipation from the bumps. Therefore, there is a difficulty in thermally dissipating the active element on the MMIC to the back surface side of the semiconductor substrate, which causes an unstable operation of the active element.

  In view of such a background, a first object of the present invention is a semiconductor device having active elements, passive elements, wirings, and electrodes that can satisfy all of mechanical strength, miniaturization, and thermal stability. To provide an apparatus. A second object of the present invention is to provide a method for manufacturing a semiconductor device that can satisfy all of the requirements for ensuring mechanical strength, miniaturization, and thermal stability in a semiconductor device having active elements, passive elements, wirings, and electrodes. There is to do. Furthermore, a third object of the present invention is to use a semiconductor device having active elements, passive elements, wirings, and electrodes, which can satisfy all of mechanical strength, small size, and thermal stability. It is to provide a semiconductor module.

  The gist of the present invention is as follows. That is, a semiconductor substrate having at least a semiconductor element on the first surface, an opening on the second surface of the semiconductor substrate opposite to the surface having the semiconductor element, an opening at a position facing the semiconductor element, and the opening A semiconductor device having a first conductor layer filling the portion and a second conductor layer on a second surface of the semiconductor substrate and at a position where the opening and the conductor are not present. The first conductor layer is electrically connected to a semiconductor element provided on the first surface.

  In the present invention, an opening is provided immediately below the active element portion from the side of downsizing the semiconductor device, and the opening is filled with the first conductor layer from the side of obtaining high heat dissipation characteristics. In addition, while taking advantage of the characteristics regarding these two side surfaces, it is possible to obtain a semiconductor device that satisfies the mechanical strength by providing the second conductor layer at a position where the opening does not exist in the semiconductor device. Become. A desired number of the second conductor layers is provided according to a planar size according to the use of the semiconductor substrate. In addition, the second conductor layer is provided at a position on the back surface of the semiconductor substrate, facing the passive elements, wirings, and electrodes of the semiconductor substrate. Furthermore, it is also useful to be placed at an appropriate position on the back surface of the semiconductor substrate from the viewpoint of ensuring mechanical strength, regardless of the presence or absence of electrical components such as passive elements, wiring, and electrodes provided on the semiconductor substrate. is there. In this case, there is no opening filled with the second conductor layer, and the second conductor layer is provided directly on the back surface of the semiconductor substrate.

  The first conductor layer that fills the opening is typically composed of two or more metals. As an example of the most preferable specific material, one metal is gold or copper having a large electric conductivity and thermal conductivity, and the other is a material that becomes a so-called barrier metal with respect to gold and copper. . That is, it is a metal layer for preventing diffusion of impurities from one conductor layer (in the above example, gold or copper) into the semiconductor layer. For example, Pt, Ti, WSi, Cr, Ta, Ti, Pt, Ni, etc. are used. This technique itself is sufficient using conventional techniques.

  The preferred size of the first conductor layer filling the opening is as follows. Here, the size refers to the size in the in-plane direction of a surface parallel to the first surface (and the second surface) of the semiconductor substrate. In the cross-sectional view, this corresponds to the width in a plane parallel to the first surface (and the second surface) of the semiconductor substrate. Hereinafter, in the present specification, “the size of the first conductor layer” means this meaning. The size of the first conductor layer is set to be larger than the width of the active element in the opening immediately below the active element provided in the semiconductor substrate. Here, the width of the active element is the width in the in-plane direction of a plane parallel to the first surface (and the second surface) of the semiconductor substrate.

The size of the first conductor layer is preferably larger from the viewpoint of reducing thermal resistance or mechanical strength. Actually, it is set in consideration of the size and layout in the MMIC design.
On the other hand, the lower limit of the cross-sectional area related to the second conductor layer at the position of the back surface of the semiconductor substrate relative to the passive elements, wirings, and electrodes of the semiconductor substrate is determined by the minimum resist dimension.

  With respect to the filling state in the opening, it is possible to project from the back surface of the semiconductor substrate from the form of filling the opening. It is possible to easily mount a further electric member on the back surface of the semiconductor substrate by using the protruding portion. The upper limit of the height from the back surface of the semiconductor substrate depends on the maximum resist film thickness.

  The manufacturing method of the semiconductor device of the present invention is as follows.

Preparing a semiconductor substrate on which at least a semiconductor element portion is mounted on the semi-insulating semiconductor substrate;
Selectively exposing the semiconductor substrate other than the semiconductor element portion;
Coating the semiconductor substrate with an insulating film;
Selectively removing a desired portion of the insulating film;
A step of coating the first metal layer on the semiconductor substrate thus prepared;
Selectively removing the first metal layer so that the metal layer is present so as to cover at least a region where the insulating film is selectively removed;
Forming an opening in a region corresponding to a region where the metal layer is present from a surface opposite to the surface where the first metal layer is present of the semiconductor substrate;
Forming a conductor layer electrically connected to the metal layer through the opening; and filling the opening with a conductor layer.

  The semiconductor module of the present invention is realized by mounting the following semiconductor device.

Having at least a semiconductor element on a semi-insulating semiconductor substrate;
Derivation of each conductor layer connected to a desired region of the semiconductor element to the outside of the semiconductor element is derived from the surface of the semiconductor substrate opposite to the surface on which the semiconductor element is mounted,
The semiconductor substrate has a lead-out end electrically connected to a metal pad on the module substrate via a via-filling conductor layer from the surface opposite to the surface on which the semiconductor element is mounted.

  In the present invention, it is preferable that each conductor layer connected to a desired region of the semiconductor element is led out of the semiconductor element through an opening provided in the semiconductor substrate.

  Such an implementation is very useful when the semiconductor element is a heterojunction bipolar transistor, as seen in the description herein.

  According to the present invention, it is possible to provide a semiconductor device capable of satisfying all of mechanical strength, miniaturization, and thermal stability. According to another aspect of the present invention, it is possible to provide a method for manufacturing a semiconductor device capable of satisfying all of mechanical strength, miniaturization, and thermal stability. Furthermore, according to the invention of the present application, it is possible to provide a semiconductor module capable of satisfying mechanical strength, miniaturization, and thermal stability.

  Prior to the description of the embodiments of the present invention, a supplementary explanation will be given of the gist of the present invention.

  FIG. 1 is a cross-sectional view of the main part showing an example in which the MMIC of the present invention is mounted on a module substrate. In this example, an MMIC semiconductor substrate 5 is mounted on the module substrate 1 via so-called bumps 3. In this example, the following configuration is extremely important. That is, the emitter via hole 114 is formed on the back surface of the semiconductor substrate 5, particularly at a position facing the active region of the HBT. The emitter via hole 114 is filled with the bump (first conductor layer) 3, and the height of the first conductor layer 3 exceeds the thickness of the semiconductor substrate 5. Further, bumps 3-1 are arranged in addition to the positions opposite to the active area of the HBT. On the module substrate 1, electrodes 16 and 16-4 are formed, and a first conductor layer 3 (referred to as a first conductor layer in the present specification) and a second conductor layer 3-1 (referred to in the present specification), respectively. Is referred to as the second conductor layer). Reference numeral 4-4 denotes an electrode pad provided on the semiconductor substrate 5 side for the second conductor layer. Here, the space between the semiconductor substrate 5 and the module substrate 1 is filled with the dielectric filler 2 to improve reliability (for example, mechanical strength).

  The conventional structure of the HBT itself is sufficient, but the configuration will be briefly described. In this example, three HBTs (HBT1, HBT2, and HBT3) are connected in parallel. An emitter layer 7, a base layer 8, and a collector layer 9 are formed on the sub-emitter layer 6 formed on the semiconductor substrate 5. The sub-emitter layer 6 is connected to the back surface electrode 4, while the collector electrode 10 is connected to three wirings. In this cross-sectional view, the connection of the collector electrode to the wiring is not shown for the purpose of taking a cross section. The collector-side wiring is connected to the back electrode through a pad. On the other hand, three base electrodes 11 are also connected and connected to the wiring. In this cross-sectional view, the connection of the base electrode to the wiring is not shown because of the way of taking a cross section. The active region of the HBT is covered with an interlayer insulator layer 12 and an interlayer insulator layer 13. Various wirings and the like not shown in this cross-sectional view are arranged using the interlayer insulator layer 12 and the interlayer insulator layer 13. The second conductor layer 3-1 may be used for drawing out a base or a collector, or may be provided as a bump simply for the purpose of physical support of the semiconductor substrate 5. The role is determined by the design of the semiconductor module. In this sense, the configuration of FIG. 1 shows the basic idea of the present invention. The present invention produces the following advantages in such a structure.

  In the semiconductor device having an active element, a passive element, a wiring, and an electrode, the side surface for securing the mechanical strength is an active element, a passive element, which is present on the first surface (simply abbreviated as a surface) of the semiconductor substrate. The second conductor layer is disposed at an arbitrary position on the second surface (simply abbreviated as the back surface) of the semiconductor substrate facing the wiring and the electrode. More preferably, in a semiconductor device having an active element, a passive element, a wiring, and an electrode, the second conductor layers are arranged at equal intervals on the back surface of the semiconductor substrate where the active element, the passive element, the wiring, and the electrode are not present. That is. In other words, not only the conductor layer (that is, the first conductor layer) is formed directly under the active element, but also the conductor layer (that is, the second conductor) is formed on the back surface of the semiconductor substrate where the passive element, the wiring, and the electrode position are opposed. It is preferable to arrange a layer). The arrangement of the first and second conductor layers makes it possible to maintain a certain distance with respect to the module substrate of the semiconductor substrate.

  In the semiconductor device having an active element, a passive element, a wiring, and an electrode, the downsizing side face is that a passive element is also formed at a position other than the opening existing on the back surface, and an opening is formed immediately below the electrode. In addition, this is achieved by two techniques of forming an opening directly under the active element. More specifically, for example, by forming a passive element of capacitance or inductance that has been provided on the surface of the semiconductor substrate on the back surface, more electrical members can be mounted within a desired area of the semiconductor substrate. That is, various electric members are three-dimensionally arranged on the front and back surfaces of the semiconductor substrate.

  In the semiconductor device having an active element, a passive element, a wiring, and an electrode, the thermal stability aspect is filled with a conductor layer (that is, a first conductor layer) immediately below the active element that is a heating element. Forming an opening. That is, since there is a heat radiation path called a conductor layer in the opening immediately below the active element, the thermal resistance is low, and the active element having a low thermal resistance is prevented from thermal runaway.

  Next, a semiconductor device showing an embodiment of the present invention, a manufacturing method thereof, and details of mounting using the semiconductor device will be described in detail with reference to the drawings. Note that in all the drawings for explaining the embodiments, the same reference numerals are given to the same functions, and the repeated explanation thereof is omitted.

<Example 1>
This example is an example of a power amplifier module. 2 is a schematic plan view of the present example, FIG. 3 is an enlarged plan view of the vicinity of the MMIC (100) used in the power amplifier module, and FIGS. 4 and 5 are longitudinal sectional views of the MMIC. Corresponds to a longitudinal sectional view taken along lines 33 ′ and 44 ′ in FIG. FIG. 6 is a schematic cross-sectional view of the power amplifier module of this example. FIG. 6 conceptually shows an example related to the stacking relationship of various members of the module. The MMIC in this example uses a collector top HBT.

  Referring to the example of the planar arrangement in the module of FIG. 2, the MMIC (100) is mounted on the module substrate 210, and the other chip components 130, 130 ', etc. are arranged around the module substrate 210. These chip members are, for example, passive elements. In addition, the rectangular parts arranged around the MMIC (100) other than those indicated by reference numerals 130 and 130 'in FIG. 2 are not particularly specified, but these are various chip components required for the module. Is shown. The input part of the MMIC (100) is indicated by reference numeral 15-2, the output part is 15-1, and the grounding part is 4. FIG. 1 shows a basic planar arrangement of main members on the module substrate.

  FIG. 3 is an enlarged plan view of the vicinity of the MMIC (100) of this power amplifier module. Corresponding to FIG. 2, an input wiring 15-2, an output wiring 15-1 and a ground (GND) 4 are shown. In FIG. 3, each part of the transistor existing below the wiring is also shown. Reference numeral 10 denotes a collector electrode, and reference numeral 11 denotes a base electrode. In this example, the three base electrodes 11 are collected and connected to the input wiring 15-2, and the three collector electrodes 10 are collected and connected to the output wiring 15-1. 4 and 5 are sectional views taken along lines 44 'and 55' in FIG. Details of these will be described later.

  FIG. 6 illustrates a laminated structure of modules. In this example of the module substrate, three substrates 161, 160, and 162 are used. In the plan view of FIG. 2, these three substrates are collectively referred to as a module substrate 210. As the module substrate, a low-temperature fired glass ceramic substrate having a relative dielectric constant of 8 is generally used. A resin can also be used as the module substrate.

  As shown in the plan view of FIG. 2, the MMIC (100) is arranged at the center or near the center of the module substrate, and various electric members 130, 130 ′, for example, passive elements, further transmission lines 131, etc. are arranged around the MMIC. Be placed. In this figure, the detailed structure of the MMIC itself is omitted. 4 and 5 are referred to for details. As described above, FIG. 6 conceptually shows an example of the stacking relationship of various members in the module. In the example using three substrates in this example, the MMIC is mounted on the substrate 160, and the various electric members 130 and the transmission line 131 are mounted on the substrate 161. Reference numeral 100-1 indicates a first surface (hereinafter simply referred to as a front surface) of the semiconductor substrate 5, and reference numeral 100-2 indicates a second surface (hereinafter simply referred to as a back surface). At the position where the active element 170 is formed, an opening is provided on the back surface of the semiconductor substrate 5, and a conductor layer (referred to as a first conductor layer in this specification) 144 is formed by filling the opening. Is done. As described above, details of the internal structure such as a so-called barrier metal layer are omitted in this structural diagram. The first conductor layer 144 is led out to the wiring 117 provided on the surface of the substrate 160. Typically such conductor layers are referred to as bumps. If it has the role of an electrode, it is called a bump electrode. The base electrode side of the HBT is indicated by reference numeral 15-2 (input wiring), and the collector electrode side is indicated by reference numeral 15-1 (output wiring). These input / output wirings 15-1 and 15-2 are provided on the surface of the substrate 160 by openings corresponding to the input / output wirings 15-1 and 15-2 and a conductor layer filled therein (referred to as a second conductor layer in the present specification). To the connected wirings 118 and 119. In this example, an opening is provided through the substrates 160 and 162, and the electrode layer 171 is filled in the opening. Heat dissipation is facilitated through the electrode layer 171. For this reason, such an opening is called a thermal via (Thermal VIA). Of course, depending on various requirements such as the characteristics of the apparatus, a configuration in which such a thermal via is not provided may be employed.

  In FIG. 6, reference numeral 112 denotes a bias line provided in the module substrate, and reference numeral 170 denotes an active element (Tr) mounted on the semiconductor substrate. Reference numerals 190 and 191 are ground planes, 120 is a thermal via, 112 is a bias line, and 113 is a metal cap.

  The example of the collector top HBT has been described so far, but it is also possible to use an emitter top HBT. FIG. 26 is a plan view showing an example of a module substrate when an emitter top HBT is used for mounting. The cross-sectional view of the emitter top HBT-MMIC is basically the same as that of the collector top HBT-MMIC, except that there are changes due to changes in the vertical positions of the collector and emitter. The general arrangement of the plan view shown in FIG. 26 is similar to that of FIG. 2, but the role of each terminal is different. The portion denoted by reference numeral 15-1 is connected to the base terminal. Wiring from the front surface to the back surface through through vias. The portion denoted by reference numeral 15-2 is connected to the collector terminal (from Via immediately below Tr). Power stage output pad. Reference numeral 16 is ground, which is connected to the emitter terminal. Wiring from the front surface to the back surface through through vias. Since the emitter grounding operation is assumed, the ground is GND on the module substrate.

  Next, an example of the MMIC portion will be described in detail. The MMIC of this example is mounted face up. That is, as seen in FIG. 6, the first surface (abbreviated as surface) 100-1 of the semiconductor substrate 5 is the front side, an emitter wiring region on the MMIC surface, a base wiring region on the MMIC surface, A collector wiring region is disposed on the MMIC surface. Reference numeral 100-2 denotes the back surface of the semiconductor substrate 5. Cross-sectional views of examples of the MMIC are shown in FIG. 4 and FIG. 5, and these examples show examples in which the HBT is a collector top type. The semiconductor substrate 5 of the MMIC (100) is mounted on the module substrate 1 (the module substrate 1 corresponds to the substrate 160 in FIG. 6) via the via-filling conductor layer 3. In FIG. 4, the extraction conductor layer on the collector electrode side appears in the cross section, and in FIG. 5, the extraction conductor layer on the base electrode side appears.

  Details of the HBT formed on the semiconductor substrate 5 are as follows. In this example, three HBTs (HBT1, HBT2, and HBT3) are connected in parallel. An emitter layer 7 is formed on the sub-emitter layer 6 formed on the semiconductor substrate 5, and a collector layer 9 is formed on the base layer 8. The sub-emitter layer 6 is connected to the back electrode 4 while the three collector electrodes 10 are connected and connected to the wiring 15-1 (FIG. 4). The collector-side wiring 15-1 is connected to the pad 14-1 and further connected to the back electrode 4-1.

  On the other hand, as shown in FIG. 5, the three base electrodes 11 are also connected to each other and connected to the wiring 15-2. The collector-side wiring 15-2 is connected to the pad 14-2 and to the back electrode 4-2. The active region of the HBT is covered with an interlayer insulating layer 12. An opening is provided in the interlayer insulating layer 12, and the pads 14-1 and 14-2 are formed covering the opening. An interlayer insulating layer 13 is formed to cover the pads 14-1 and 14-2, and at least openings corresponding to the pads 14-1 and 14-2 are formed. Wirings are formed on the interlayer insulating layer 13, and the wirings 15-1 and 15-2 are connected to the pads 14-1 and 14-2 through the openings.

  In this example, the emitter via hole 114 ′ is formed on the back surface of the MMIC at a position facing the HBT of the MMIC, while the base via hole 115 ′ and the collector via hole 116 ′ are on the back surface of the MMIC and at a position not facing the HBT. It is formed. Each via hole is filled with the first conductor layer 114 or the second conductor layers 115, 116, and the height of the first conductor layer or the second conductor layer is determined by the thickness of the semiconductor substrate 5. Formed beyond.

  In the example shown in FIGS. 4 and 5, the base via hole 115 and the collector via hole 116 are formed in contact with the WSiN electrode 14-1 or 14-2 on the surface of the GaAs substrate 1. Therefore, the depth of the via hole is the same as that of the emitter via hole 114 formed immediately below the active region of the HBT. As a result, a plurality of via holes can be formed at one time, which is extremely effective for cost reduction.

  In the example of FIGS. 4 and 5 described above, the conductor layer 3-2 is formed at a position other than the emitter via hole 114 and the collector via hole 116. The conductor layers 3-3 and 3-4 are the second conductor layers referred to in the specification of the present application, and the effect of ensuring the mechanical strength and improving the reliability in mounting is obtained.

  An example in which a barrier metal is provided is shown in FIG. In this example, after the via hole back surface electrode 4 is formed in the emitter via hole 114, the electrode 4-3 is further formed, and the conductor layer 3 is formed. The electrode 4-3 becomes a barrier metal of the conductor layer 3. As specific examples of the electrodes, the back electrode 4 is a laminated electrode of Au / Ge / Ni / Ti / Au, the electrode 4-3 is Ni or Cr, and the conductor layer 3 is Au or Cu. The other parts are the same as in FIG.

  Next, it will be illustrated that the first and second conductor layers of the present invention can sufficiently cope with the irregularities of the module substrate. In the example of FIG. 8, in the emitter via hole 114 and the collector via hole 116, after the via hole back surface electrodes 4 and 4-1 are formed, the conductor layers 3 and 3-1 are formed. Furthermore, as can be seen in this example, the conductor layer of the emitter via hole and the collector via hole has a narrowed tip. Further, the bump 3-3 provided via the electrode layer 4-3 has a constricted portion 3-7. Since the height of the narrowed portions 3-5, 3-6, and 3-7 at the tip is easily adjusted, variations in height from the back surface of each conductor layer in a plurality of filled openings can be easily corrected. The The width of the constriction at the tip is preferably about 25 microns φ, for example. The height is preferable for adjustment by the mounting process of the semiconductor substrate 5 to the substrate 160. Further, the thickness of the constricted portion is usually selected to be about 10 microns. Set in consideration of module board warpage. FIG. 9 is a module cross-sectional view showing an example in which the height variation is easily corrected from the back surface of each conductor layer. When the tip portions of the conductor layers 3-5 and 3-6 are mounted on the module substrate 1 of the semiconductor substrate 5, the heights thereof are adjusted. That is, the height of the conductor layer 3-6 or 3-7 is adjusted based on the conductor layer 3-5 that does not bend. The other parts are the same as in FIG. Thus, even when the module substrate has irregularities, it is possible to easily mount the semiconductor substrate 5 by adjusting the height of each conductor layer while keeping the semiconductor substrate 5 substantially flat. FIG. 10 is a schematic enlargement of this state. Similar to FIG. 6, three module substrates 162, 160, and 161 are used, and the lamination and arrangement are the same. In this case, it is assumed that at least the module substrates 162 and 160 have irregularities with a thickness d2. The thickness from the lower surface of the MMIC semiconductor substrate 5 to the recess of the substrate 160 is d1. Typically, d1 is about 100 microns rather than 20 microns, whereas d2 is about 10 microns at maximum. Also in this case, when the structure of the conductor layer of the present example is used, the height of the conductor layer is adjusted by the above-described conductor layer, and the influence of stress or the like due to the substrate unevenness can be easily eliminated. I can do it.

  FIG. 11 is a cross-sectional view showing an example in which electrical members and semiconductor element portions are three-dimensionally provided on both surfaces of the semiconductor substrate 1. A semiconductor element portion such as a semiconductor active element 180 is provided on the front surface of the semiconductor substrate 1 and a passive element 192 is provided on the back surface. The distance from the back surface of the semiconductor substrate 5 to the surface of the module substrate 160 is d1, and the thickness of the electric member 192 provided on the back surface of the semiconductor substrate 1 is d3. FIG. 12 is a cross-sectional view showing a state where the module substrates 160 and 162 are uneven when such mounting is performed. When the distance between the back surface of the semiconductor substrate 5 and the surface of the concave portion of the module substrate 160 is d1, the height of the unevenness of the module substrate is d2, and the thickness of the electric member 192 is d3, the relationship d1 ≧ d2 + d3 is required. With respect to such a relationship, the height can be adjusted and the semiconductor substrate 5 can be satisfactorily mounted on the module substrate 160 by the structure of this example.

  In mounting, face-up bump mounting and wire bonding mounting can be used in combination. FIG. 27 is a sectional view showing this example. In other words, the MMIC is mounted face up and further electrically connected to the module substrate using bonding wires. The basic structure of this structure is the same as that shown in FIG. 6, but a part thereof is that wire bonding is used in addition to bump mounting. That is, reference numeral 200 represents a bonding pad electrode on the MMIC, reference numeral 201 represents a bonding pad electrode on the module substrate, and reference numeral 204 represents a wire. Further, in this example, empty bumps 147 are provided in the portion denoted by reference numeral 203 immediately below the wire bonding pads existing on the MMIC. This is for mechanical reinforcement during wire bonding. The other parts are the same as in FIG. In addition to the configuration of this example, it is needless to say that the purpose of this example of bump mounting and wire bonding can be implemented according to the specific structure of the MMIC.

<Example 2>
A typical method for manufacturing a semiconductor device will be described. 13 to 20 are cross-sectional views of the apparatus for explaining the semiconductor device manufacturing method of the present invention according to the manufacturing process. This example is an example of a high power multi-finger HBT configured by connecting basic HBTs in parallel.

On a semi-insulating GaAs substrate 5, a highly doped n-type GaAs sub-emitter layer (Si concentration 5 × 10 ¹⁸ cm ⁻³ , film thickness 0.8 μm) 6, an n-type InGaP emitter layer (InP molar ratio 0.5, Si Concentration 5 × 10 ¹⁷ cm ⁻³ , film thickness 0.2 μm) 7, p-type GaAs base layer (C concentration 3 × 10 ¹⁹ cm ⁻³ , film thickness 70 nm) 8, n-type InGaAs collector layer (Si doping, film thickness) 0.8 μm) 9 is grown by metalorganic vapor phase epitaxy. The n-type InGaAs collector layer is configured as a layer whose InAs molar ratio varies from 0 to 0.5 and whose Si concentration varies from 3 × 10 ¹⁶ cm ⁻³ to 2 × 10 ¹⁹ cm ^−3. .

Next, a WSi layer (WSi: Si molar ratio 0.3, film thickness 0.3 μm) is deposited on the entire surface of the wafer by using a high frequency sputtering method. Thereafter, the WSi layer was processed into a desired shape by photolithography and dry etching using CF ₄ to form the collector electrode 10 (FIG. 13).
Using the collector electrode 10 as a mask region, the n-type InGaAs collector layer 9 is combined with dry etching using SF ₆ and SiCl ₄ and wet etching using a mixed solution of phosphoric acid, hydrogen peroxide, and water. Removed to desired shape.

As a subsequent process, it is sufficient to use a well-known method as a method for manufacturing the collector top HBT. FIG. 14 is a cross-sectional view of the active region of the HBT. The process will be briefly described below. Boron ions are implanted on the entire surface under conditions of an acceleration energy of 50 keV and a dose of 2 × 10 ¹² cm ⁻² at room temperature, and a high-resistance InGaP region 17 is formed in the transistor parasitic region (a region other than the transistor intrinsic region directly below the collector electrode 10). The base current flowing through the parasitic emitter-base junction was suppressed. Since the high resistance region 17 is not an essential part of the present invention, the description and illustration of the high resistance region 17 are omitted in the specification of the present application even in the HBTs exemplified so far.

  Thereafter, a base electrode (Pt (thickness 20 nm) / Ti (thickness 50 nm) / Pt (thickness 50 nm) / Au (thickness 200 nm) laminate) 11 was formed by electron beam evaporation and a lift-off method.

  Subsequently, the p-type GaAs base layer 8, the InGaP emitter layer 7, and the GaAs sub-emitter region 6 are formed using conventional photolithography and wet etching using a hydrochloric acid aqueous solution and a mixed solution of phosphoric acid, hydrogen peroxide, and water. After removal, the semi-insulating GaAs substrate 5 was exposed (FIG. 14).

Then, an SiO ₂ layer (film thickness 1 μm) 12 is formed as an interlayer insulating film by a plasma enhanced chemical vapor deposition method. For this SiO ₂ layer 12, by photolithography and dry etching customary to remove the _SiO 2 12 of region for forming the base via hole and collector via hole. Thereafter, a WSiN layer (thickness: 0.3 μm) is deposited on the entire surface of the wafer by using a high-frequency sputtering method for the surface electrode of the via hole. This WSiN layer was formed as a surface electrode for a base via hole (not shown in the cross section of the figure) and a surface electrode 14 for a collector via hole by photolithography and dry etching using CF ₄ (FIG. 15). The via hole surface electrode 14 is made of the same material as the resistance element material, and the resistance element can be simultaneously formed in the MMIC.

Thereafter, an interlayer insulating film SiO ₂ (film thickness 1 μm) 13 is formed again by plasma enhanced chemical vapor deposition. Then, contact holes are formed between the base electrode, the collector electrode, and the wiring by photolithography and dry etching. The SiO ₂ 13 in the via hole and collector via hole forming region was removed. A wiring Mo (film thickness 50 nm) / Au (film thickness 800 nm) 15 to the base and collector was formed by electron beam evaporation and milling. The wiring 15 may be a Ti (film thickness of 50 nm) / Au (film thickness of 800 nm) laminated body, and may be formed by electron beam evaporation and a lift-off method. The wiring 15 is connected to the collector electrode 10 or the surface electrode 14 for the collector via hole through the via hole and the collector via hole.

  Thereafter, the semi-insulating GaAs substrate 5 is bonded to the glass substrate 20 with the adhesive 21 face down, and then the GaAs substrate 5 is thinned to a thickness of 50 to 70 μm by polishing. Emitter via holes 114, base via holes (not shown), and collector via holes 116 are formed by photolithography and wet etching using a mixed solution of sulfuric acid, hydrogen peroxide, and water (FIG. 16).

  Next, the emitter electrode 4 and the electrode 4-1 made of AuGe (film thickness 60 nm) / Ni (film thickness 10 nm) / Au (film thickness 10 μm) were subjected to electron beam evaporation and then alloyed at 370 ° C. for 10 minutes in a nitrogen atmosphere ( FIG. 17).

  Thereafter, a desired plating pattern was formed by photolithography using two types of resists 18-1 and 18-2 (using two types of resists having different photosensitivities). (FIG. 18). In the following drawings, these two types of resists are shown by reference numeral 18 as a unit for convenience.

  Next, the emitter via hole 114, the base via hole (not shown), and the collector via hole are filled at the same time by electrolytic copper plating, and finally the outermost surface is covered with electrolytic tin (Sn) 19 by plating (FIG. 19). ). Thereafter, the insulating film pattern was removed with an organic substance (FIG. 20).

  Thereafter, the MMIC (100) was peeled off from the glass substrate and mounted on the module substrate 1. The bump electrode 3 and the electrode 16 on the module substrate (this specific metal material example is gold) or the bump electrode 3-1 and the electrode 16-1 (gold) on the module substrate are added to the module substrate 1 at 210 degrees Celsius. They were connected by thermocompression bonding (FIG. 21).

According to the manufacturing method of this example, it is possible to manufacture a semiconductor device that can satisfy all of the reliability related to ensuring mechanical strength, downsizing, and thermal stability. Another object is to manufacture the semiconductor device at a low cost. That is, the via hole can be produced in a common processing step, and the conductor layer (bump electrode) can be formed simultaneously with the via hole filling plating step, so that low cost can be realized.
<Example 3>
This example is an example of a power amplifier module using various HBT-MMICs. In this example, a power amplifier module is illustrated using an HBT-MMIC using an InP-based compound semiconductor material instead of the HBT-MMIC using the GaAs-based compound semiconductor material used in Example 1. Hereinafter, the HBT-MMIC using an InP-based compound semiconductor material is abbreviated as “InPHBT-MMIC”.

The structure of InPHBT-MMIC is basically the same as that of the first embodiment. Specific examples of the material of this example are as follows. 4 and 5, the back electrode material 4 is Ti (film thickness 50 nm) / Au (10 μm), the semiconductor substrate 5 is a semi-insulating InP substrate, and the sub-emitter layer 6 is highly doped n-type InGaAs (InAs molar ratio 0.5). , Si concentration 2 × 10 ¹⁹ cm ⁻³ , film thickness 0.8 μm), emitter layer 7 is n-type InAlAs (InAs molar ratio 0.5, Si concentration 3 × 10 ¹⁷ cm ⁻³ , film thickness 0.2 μm), The base layer 8 is p-type InGaAs (InAs molar ratio 0.5, C concentration 3 × 10 ¹⁹ cm ⁻³ , film thickness 70 nm), and the collector layer 9 is n-type InGaAs (film thickness 0.8 μm). The n-type InGaAsIn of the collector layer 9 has an As molar ratio of 0.5 and a Si concentration of 3 × 10 ¹⁶ cm ⁻³ to 2 × 10 ¹⁹ cm ⁻³ . The manufacturing method of each of these layers was the same as that in Example 1, and the growth of layers 6 to 9 was performed by the metal organic vapor phase epitaxy method and was performed in the same manner including ion implantation. The HBT itself is different in material system, and the basic configuration is the same as the conventional one.

  FIG. 22 shows an equivalent circuit diagram of a typical power amplifier example. In a power amplifier, as shown in FIG. 22, the HBTs Q1 and Q2 are normally used with a common emitter. Therefore, if the HBT is a collector top type rather than an emitter top type, the MMIC and the power amplifier module can be downsized. desirable. This is because, with respect to the HBT fingers formed in a plurality of MMICs, the collector top HBT can form a first via hole that is common as a back emitter. On the other hand, in the emitter top HBT, since the collector electrode cannot be shared, it is necessary to form a fine via hole for each finger and to provide a collective wiring on the back surface of the MMIC, which increases the size of the MMIC. Because. In FIG. 22, HBTQ3 and Q4 are for bias, not emitter grounding. Therefore, an emitter top type is sufficient for these HBTs.

  According to the manufacturing method of this example, it is possible to manufacture a semiconductor device that can satisfy all of the reliability related to ensuring mechanical strength, downsizing, and thermal stability.

<Comparison study of other structures>
In order to facilitate the understanding of the utility of the present invention, the following points will be specifically considered in the case of mounting the conventional structure.

  FIG. 23 shows a longitudinal sectional structural view of the most assumed module example. This is a structure simulating a signal processing apparatus using an optical element array disclosed in, for example, Japanese Patent Laid-Open No. 6-204449 (Patent Document 1). Reference numeral 100 indicates an MMIC semiconductor substrate. An optical element 181 is mounted face up on the semiconductor substrate 100. Reference numeral 115 is a wiring provided as appropriate on the semiconductor substrate. This signal processing apparatus uses three substrates 161, 160, and 162, and the substrate 161 is provided with an opening. An MMIC is disposed in the opening. A via 170 immediately below the optical element array 181 of the MMIC is formed. The via is filled with a conductive layer, and an electrode 171 is further provided. The electrode 171 is connected to the electrode 113 on the signal processing device substrate side through the bump electrode 143. Usually, a chip member 130, a transmission path 131, and the like are appropriately disposed on the substrate 161.

  In the example of FIG. 23, the conductor layer 170 is formed only directly below the optical element 181 provided on the surface of the semiconductor substrate 100, and the electrode 171 is disposed on the back surface of the semiconductor substrate 100. Therefore, when an electrode, a wiring, a passive element, or the like other than the active element of the optical element is to be disposed on the back surface of the semiconductor substrate 100, for example, the bump electrodes 143 cannot be disposed at equal intervals, so that the mechanical strength is ensured. It becomes difficult. For this reason, there is a difficulty in the reliability of the signal processing device.

  Furthermore, in this connection method, many electrical connection points are generated, and there are problems in the generation of resistance components and long-term durability. That is, there are two connections (170 and 171 and 171 and 143) between the lead-out electrode 171 to the outside of one optical element 181 and the electrode 113 on the substrate in the signal processing apparatus. The resistance component accompanying the connection point in this electric circuit is generated in proportion to the number of connections. In addition, since many joints are included, the durability is also difficult.

  FIG. 24 shows a longitudinal sectional view of another module configuration example. FIG. 24 shows a structure simulating a semiconductor device disclosed in, for example, Japanese Patent Laid-Open No. 2001-210677 (Patent Document 2). Also in this example, the MMIC substrate 100 is mounted face-up on the module substrate 160. As the module substrate, three substrates 161, 160, and 162 are used. The wiring pads 111 are disposed on the substrate 160, and the active elements 121 are disposed on the semiconductor substrate 100. For the module substrates 160, 161, 162, a low-temperature fired glass ceramic substrate having a relative dielectric constant of 8 has been generally used. A surface electrode 110 is disposed on the semiconductor substrate 100 of the MMIC in order to connect the wiring from the active element to the module substrate side. An opening is formed from the back surface of the semiconductor substrate 100 toward the front surface electrode 110, and a wiring pad 111 provided on the module substrate 160 is connected to the surface electrode 110 through the bump electrode.

  A typical manufacturing method of the structure shown in the example of FIG. 24 so far is a manufacturing method as shown in FIG. 25, for example. First, a semiconductor substrate 100 on which a desired active region is formed is prepared ((a) of FIG. 25). An active element 121 and a surface electrode 110 are shown on the semiconductor substrate 100, and detailed structures and connections thereof are omitted. Next, a through hole is formed by dry etching from a position facing the front surface electrode 110 on the back surface of the semiconductor substrate 100. Further, the conductor layer 141 is embedded in the through hole ((b) of FIG. 25). Thereafter, the semiconductor substrate 100 is etched from the back surface to be thinned. In this way, a conductor layer 141 protruding from the semiconductor substrate 100 is obtained (FIG. 25C). The conductor layer 141 is connected to the wiring pad 11 of the module substrate 160. This state is a cross-sectional view shown in FIG.

  The structure of FIG. 24 may seem to be similar to the structure of the present invention at first glance. However, when such a manufacturing method cannot be avoided, the electrical members cannot be three-dimensionally arranged using the back surface of the semiconductor substrate 100 as in the present invention. That is, as can be seen from the manufacturing process, before the conductor layer 141 is formed, a new electric member, for example, a passive element or a wiring cannot naturally be formed on the back surface of the semiconductor substrate 100. Therefore, it is not suitable for downsizing of the apparatus.

  Furthermore, in the structure of FIG. 24, since the conductor layer 141 is formed directly below the surface electrode 110 while avoiding active elements and passive elements, heat generated in the active element 121 and the like cannot be efficiently released to the outside. Therefore, the active element 121 tends to be thermally unstable.

Since this application includes many forms, the main embodiments of the present invention are listed below.
(1) Having a heterojunction bipolar transistor on a semiconductor substrate, on the back surface of the semiconductor substrate, at a position facing the heterojunction bipolar transistor, on the back surface of the semiconductor substrate and on the heterojunction A semiconductor device having second and third via holes in addition to positions opposite to the junction bipolar transistor.
(2) The semiconductor device according to (1), wherein the first, second, and third via holes are filled with a conductor layer.
(3) The heterojunction bipolar transistor has a collector top type, wherein the first via hole is an emitter via hole, and the second and third via holes are a base via hole and a collector via hole, respectively (1) ), (2).
(4) In the semiconductor device, the first via hole is formed with an electrode extending over the back surface of the semiconductor substrate, and the second and third via holes are formed with electrodes extending over the semiconductor substrate surface and the back surface. The semiconductor device according to any one of (1), (2), and (3), wherein the first, second, and third via holes are electrically isolated from each other.
(5) The semiconductor device as described in (4) above, wherein the semiconductor-side surface electrodes of the semiconductor in the second and third via holes are in contact with the semiconductor substrate.
(6) The semiconductor device as described in (5) above, wherein the substrate-side surface electrode of the semiconductor is made of WSiN or NiCr.
(7) The semiconductor device as described in (4) above, wherein the substrate-side surface electrode of the semiconductor is made of Mo / Au or Ti / Au.
(8) The semiconductor substrate is GaAs, and an electrode extending over the back surface of the semiconductor substrate provided in each of the first, second, and third via holes includes AuGe. The semiconductor device according to any one of 6).
(9) The semiconductor substrate is InP, and the electrode over the back surface of the semiconductor substrate provided in each of the first, second, and third via holes contains Ti, The semiconductor device according to any one of (6).
(10) A semiconductor device characterized in that a conductor layer formed on a surface side on which the base, emitter, and collector regions of the semiconductor substrate in the second and third openings are mounted is in contact with the semiconductor substrate.
(11) The step of selectively exposing the semiconductor substrate, the step of covering the entire surface with the insulating film, the step of selectively removing the insulating film, the step of covering the entire surface of the metal, and the portion of the insulating film selectively removed The method for manufacturing a semiconductor device according to any one of (1) to (8), further including a step of selectively removing the metal so as to cover the region.
(12) A step of preparing a semiconductor substrate on which at least a semiconductor element portion is mounted, a step of selectively exposing the semiconductor substrate other than the semiconductor element portion, a step of covering the semiconductor substrate with an insulating film, and a desired insulating film A step of selectively removing the portions, a step of covering the prepared semiconductor substrate with a metal layer, and at least covering the region where the insulating film has been selectively removed so that the metal layer is present. Selectively removing,
At least a step of forming an opening in a region corresponding to a region where the metal layer exists, and a step of filling the opening with a conductor layer from a surface of the semiconductor substrate opposite to the surface on which the metal layer exists. A method of manufacturing a semiconductor device.
(13) The step of forming an opening in a region opposite to the surface on which the metal layer is present on the semiconductor substrate and in a region corresponding to the region on which the metal layer is present includes mounting the semiconductor element on the semiconductor substrate. The method according to item (12), further including forming an opening in a region corresponding to a region where the semiconductor element exists from a surface opposite to the surface opposite to the surface, and then filling the opening with a conductor layer. A method for manufacturing a semiconductor device.
(14) The semiconductor element portion includes a collector top type heterojunction bipolar transistor,
There are at least two regions where the metal layer is present from the surface opposite to the surface where the metal layer is present on the semiconductor substrate, and each of them is connected to the base and collector regions of the heterojunction bipolar transistor. Area,
An opening is filled with a conductor layer in a region opposite to the surface where the metal layer is present of the semiconductor substrate and corresponding to the region where the metal layer is present, and the opening corresponds to each region of the base and the collector. And an opening to a region corresponding to a region where the semiconductor element exists from a surface opposite to the surface on which the semiconductor element is mounted of the semiconductor substrate is filled with a conductor layer, and the opening is The method of manufacturing a semiconductor device according to item (13), wherein the method is for each emitter region.
(15) In the semiconductor device, the opening in the semiconductor substrate is a step of forming two kinds of resist films with different sensitivity and having an opening of a desired shape, and a step of filling the opening with a conductive material. Production method.
(16) The semiconductor substrate has at least a semiconductor element, and each conductor layer connected to a desired region of the semiconductor element is led out of the semiconductor element. What is the surface of the semiconductor substrate on which the semiconductor element is mounted? The lead-out end is derived from the opposite surface side, and the lead-out end from the surface opposite to the surface on which the semiconductor element is mounted of the semiconductor substrate is electrically connected to the metal pad on the module substrate. A semiconductor module characterized by that.
(17) The item described in (16) above, wherein a lead-out end is made through an opening provided in the semiconductor substrate from a surface opposite to a surface on which the semiconductor element is mounted of the semiconductor substrate. Semiconductor module.
(18) The semiconductor module according to item (17), wherein when the semiconductor substrate is mounted on the module substrate, the tip is curved so that the heights of the conductor layers on the back surface are equal.
(19) The semiconductor module according to item (18), wherein the semiconductor element is a heterojunction bipolar transistor.
(20) The surface electrode of the semiconductor substrate in the first, second, and third via holes is electrically connected to the metal pad formed on the ceramic or resin substrate via the via-filling conductor layer. A high-power amplifier module characterized by that.

FIG. 1 is a longitudinal sectional view of an example of a collector top HBT used in a semiconductor device of the present invention. FIG. 2 is a plan view of an example of a semiconductor module using the semiconductor device of the present invention. FIG. 3 is a plan view of the vicinity of the MMIC of the semiconductor module illustrated in FIG. 4 is a cross-sectional view taken along line 44 'in the plan view of FIG. 5 is a cross-sectional view taken along line 55 'in the plan view of FIG. FIG. 6 is a cross-sectional view of an example of a semiconductor module using the semiconductor device of the present invention. FIG. 7 is a longitudinal sectional view of another example of the collector top HBT used in the semiconductor device of the present invention. FIG. 8 is a longitudinal sectional view of another example of a collector top HBT having a thin bump at the tip of the present invention. FIG. 9 is an enlarged sectional view showing a state in which the HBT of FIG. 8 is mounted on the module substrate. FIG. 10 is a cross-sectional view of a semiconductor module for explaining the case where the module substrate has irregularities. FIG. 11 is a cross-sectional view of a semiconductor module showing an example in which an electrical member is mounted on the back surface of a semiconductor substrate. FIG. 12 is a cross-sectional view of the semiconductor module of the present invention showing an example in which an electrical member is mounted on the back surface of the semiconductor substrate. FIG. 13 is a cross-sectional view showing a semiconductor substrate having a collector top HBT according to the present invention in the order of manufacturing steps. FIG. 14 is a cross-sectional view showing a semiconductor substrate having a collector top HBT according to the present invention in the order of manufacturing steps. FIG. 15 is a cross-sectional view showing a semiconductor substrate having a collector top HBT according to the present invention in the order of manufacturing steps. FIG. 16 is a cross-sectional view illustrating a semiconductor substrate having a collector top HBT according to the present invention in the order of manufacturing steps. FIG. 17 is a cross-sectional view showing a semiconductor substrate having a collector top HBT according to the present invention in the order of manufacturing steps. FIG. 18 is a cross-sectional view showing a semiconductor substrate having a collector top HBT according to the present invention in the order of manufacturing steps. FIG. 19 is a cross-sectional view showing a semiconductor substrate having a collector top HBT according to the present invention in the order of manufacturing steps. FIG. 20 is a cross-sectional view showing a semiconductor substrate having a collector top HBT according to the present invention in the order of manufacturing steps. FIG. 21 is a cross-sectional view showing a semiconductor substrate having a collector top HBT according to the present invention in the order of manufacturing steps. FIG. 22 is a diagram illustrating an example of a circuit configuration of the power amplifier. FIG. 23 is a cross-sectional view of a semiconductor module assuming a conventional semiconductor device. FIG. 24 is a cross-sectional view of another semiconductor module assuming the conventional semiconductor device. FIG. 25 is a cross-sectional view illustrating a method for mounting the semiconductor device illustrated in FIG. FIG. 26 is a schematic plan view of a module substrate when the emitter top HBT is mounted. FIG. 27 is a schematic cross-sectional view showing an example of a combined structure of face-up mounting and wire bonding mounting.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,160 ... Module board | substrate, 2 ... Dielectric filler 3, 3-1, 3-2, 3-3, 3-4 ... Conductor layer, 4 ... Via-hole inner side electrode, 5 ... Semiconductor substrate, 6 ... Sub-emitter layer 7 ... emitter layer, 8 ... base layer, 9 ... collector layer, 10 ... collector electrode, 11 ... base electrode, 12, 13 ... interlayer insulating film, 15, 15-1, 15-2 ... MMIC surface wiring, 16 ... 1 (or 160), 17 ... high resistance region, 100 ... MMIC, 130 ... chip component, 131 ... transmission line, 141, 143, 144, 145, 146 ... conductor layer / bump electrode, 118 ... base input, 119 ... Collector output, 190, 191, 117 ... Ground plane, 120, 171 ... Thermal via, 112 ... Bias line, 147 ... Empty bump, 150, 113 ... Metal cap, 114 ... Emitter via 115, base via hole, 116 ... collector via hole, 121 ... active element, 110, 115 ... front electrode, 160, 161, 162 ... module substrate, 180 ... active element, 120, 171 ... back electrode, 170 ... active element 181 ... Optical element. 108, 110, 111, 113 ... module substrate electrodes, 192 ... passive elements, 200 ... bonding pad electrodes on the MMIC, 201 ... bonding pad electrodes on the module substrate, 204 ... wires.

Claims (22)

A semiconductor substrate;
A semiconductor element on the first surface of the semiconductor substrate;
A second surface of the semiconductor substrate opposite to the surface having the semiconductor element, an opening at a position facing the semiconductor element, a first conductor layer filling the opening, and the semiconductor substrate And a second conductor layer at a position where the opening and the first conductor layer do not exist,
A semiconductor device, wherein at least the first conductor layer is electrically connected to a semiconductor element on the first surface. The semiconductor device according to claim 1, wherein the first and second conductor layers are made of two or more kinds of metal layers. The first conductor layer of the semiconductor substrate has a cross-sectional area in a plane parallel to the first surface of the semiconductor substrate, wherein the second surface side is larger than the first surface side. Item 14. The semiconductor device according to Item 1. The height of the first conductor layer of the semiconductor substrate protruding from the second surface of the semiconductor substrate and the height of the first conductor layer protruding from the second surface of the semiconductor substrate is The semiconductor device according to claim 1, wherein the height is higher than an electronic member mounted on the second surface. The height of the first conductor layer of the semiconductor substrate protruding from the second surface of the semiconductor substrate and the height of the first conductor layer protruding from the second surface of the semiconductor substrate is the semiconductor device. The semiconductor device according to claim 1, wherein the height of the unevenness of the module substrate on which is mounted is higher. The first conductor layer of the semiconductor substrate protrudes from the second surface of the semiconductor substrate, and the height of the first conductor layer protruding from the second surface of the semiconductor substrate is the semiconductor substrate. 2. The semiconductor device according to claim 1, wherein the height of the electronic member mounted on the second surface is higher than the sum of the height of the unevenness of the module substrate on which the semiconductor device is mounted. The semiconductor device according to claim 1, wherein the semiconductor element is a heterojunction bipolar transistor. The semiconductor substrate has a plurality of heterojunction bipolar transistors as the semiconductor element, and a desired number of the plurality of heterojunction bipolar transistors in each region of the base, emitter, and collector of the heterojunction bipolar transistor. 8. The semiconductor device according to claim 7, wherein the heterojunction bipolar transistor is led out to the outside in each region. 8. The semiconductor device according to claim 7, wherein at least the collector region having the heterojunction bipolar transistor is located above the base region having the heterojunction bipolar transistor in the stacking direction of the semiconductor layer with respect to the semiconductor substrate. 8. The semiconductor device according to claim 7, wherein at least the emitter region having the heterojunction bipolar transistor is located above the base region having the heterojunction bipolar transistor with respect to the semiconductor substrate in the stacking direction of the semiconductor layer. The semiconductor substrate has at least first, second and third openings, and a heterojunction bipolar transistor as the semiconductor element, and the heterojunction bipolar transistor is opposed to the first opening, The lead-out of each conductor layer connected to the base, emitter, and collector regions of the heterojunction bipolar transistor to the outside of the heterojunction bipolar transistor may be any of the first, second, and third openings. The semiconductor device according to claim 1, wherein the semiconductor device is formed through the gap. The semiconductor element is a collector top type heterojunction bipolar transistor, wherein the first opening corresponds to an emitter via hole, and the second and third openings correspond to a base via hole and a collector via hole, respectively. Item 14. The semiconductor device according to Item 1. The semiconductor substrate has at least first, second and third openings, and a heterojunction bipolar transistor as the semiconductor element, and the heterojunction bipolar transistor is opposed to the first opening, and The first opening has a first conductor layer extending to the second surface side of the semiconductor substrate, and each of the second and third openings has a first surface of the semiconductor substrate. A second conductor layer formed across the second surface side from the side,
The semiconductor device according to claim 7, wherein the first, second, and third openings are electrically separated from each other. The first opening has a first conductor layer extending to the second surface side of the semiconductor substrate, and each of the second and third openings has a first surface of the semiconductor substrate. A second conductor layer formed across the second surface side from the side,
The semiconductor device according to claim 11, wherein the first, second, and third openings are electrically separated from each other. 12. A conductive layer is formed in the opening to fill the first, second, and third openings, and a lead-out electrode to the outside of the semiconductor element is provided on the back surface of the semiconductor substrate. The semiconductor device described. Preparing a semiconductor substrate on which at least a semiconductor element is mounted;
Selectively exposing the semiconductor substrate other than the semiconductor element;
Coating the semiconductor substrate with an insulating film;
Selectively removing a desired portion of the insulating film;
A step of coating the first metal layer on the semiconductor substrate thus prepared;
Selectively removing the first metal layer so that the first metal layer is present so as to cover at least a region where the insulating film is selectively removed;
Forming an opening in a region corresponding to a region where the first metal layer is present from a surface of the semiconductor substrate opposite to a surface where the first metal layer is present;
A method of manufacturing a semiconductor device, comprising at least a step of filling the opening with a conductor layer. The semiconductor element has a collector top type heterojunction bipolar transistor,
There are at least two openings opened in a region corresponding to a region where the metal layer exists from a surface opposite to the surface where the metal layer exists of the semiconductor substrate, each of which is the heterojunction bipolar. An opening corresponding to a region connected to each region of the base and collector of the transistor;
Each opening is filled with a conductor layer, and each opening is connected to each region of the base and the collector, and is opposite to the surface on which the semiconductor element is mounted on the semiconductor substrate. From the surface, an opening portion opened in a region corresponding to a region where the semiconductor element exists is filled with a conductor layer, and the opening portion is connected to each region of the emitter. Item 17. A method for manufacturing a semiconductor device according to Item 16. A semiconductor substrate having a semiconductor element and a module substrate, and each conductor layer connected to a desired region of the semiconductor element is led out of the semiconductor element through an opening provided in the semiconductor substrate. The semiconductor substrate is derived from the surface opposite to the surface on which the semiconductor element is mounted, and the lead-out end from the surface opposite to the surface on which the semiconductor element is mounted on the semiconductor substrate is A semiconductor module characterized by being electrically connected to a conductor layer on the module substrate. The lead-out end to the outside of the semiconductor element of each conductor layer connected to the desired region of the semiconductor element is curved, from the surface side opposite to the surface on which the semiconductor element portion of the semiconductor substrate is mounted, The semiconductor module according to claim 18, wherein heights of the conductor layers are equal to each other. Each conductor layer connected to a desired region of the semiconductor element is led out of the semiconductor element by using a bonding substrate from an opening provided in the semiconductor substrate and an electrode existing on the semiconductor substrate. A semiconductor module which is electrically connected to an upper conductor layer. 21. The semiconductor module according to claim 20, wherein a bump electrode is provided immediately below the wire bonding electrode existing on the semiconductor substrate. 21. The semiconductor module according to claim 20, wherein the semiconductor element is a heterojunction bipolar transistor.

Images