JP3229185B2 - Semiconductor chip, manufacturing method thereof, semiconductor element, and semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a transistor device, a semiconductor chip including the semiconductor device, a method of manufacturing the same, and a semiconductor device such as a microwave or millimeter-wave monolithic IC using the same.

[0002]

2. Description of the Related Art In recent years, a transistor chip or a microwave monolithic integrated circuit (Mo
nolithic Microwave IC. There is a growing demand for chips (hereinafter abbreviated as “MMIC”). Above all, in the microwave band, a GaAs field effect transistor (Field Effect Transistor), which is currently in practical use.
Heterojunction bipolar transistor elements (hereinafter abbreviated as “HBTs”) having higher gain and lower output conductance as compared with “T” (hereinafter abbreviated as “T”) have attracted attention as means for realizing a high-efficiency amplifier.

[0003] As is generally known, HBTs operate at a high current density, so that the heat generation density inevitably increases. Therefore, in order to operate the HBT properly,
It is necessary to efficiently release heat generated from a pn junction formed on the main surface of the semiconductor chip to the outside of the semiconductor chip.

[0004] In addition to efficiently dissipating the heat generated at the junction formed on the main surface of the semiconductor chip, it is also possible to reduce the inductance and parasitic capacitance of the lead-out wiring, and to amplify the power in the microwave band. As for the transistor element that can be put to practical use, a transistor chip or MMIC chip having a plurality of them, a method for manufacturing a semiconductor device using them, a structure of a bump electrode, etc. It is disclosed in the following documents and the like. H. Sato et al., "Bump Heat Sink technology" 15th
Annual GaAs ICSymposium Technical Digest p337-34
0. K. Yamamura et al., "Flip-Chip Bonding Technology
for GaAs-MMIC PowerDevices "ISHM '93 p433-438. JP-A-6-104274 (Japanese Patent Application No. 4-2493)
98).

FIG. 25 shows a structure for forming "a plurality of dummy bump electrodes not intended for electrical connection" disclosed as "semiconductor device" in JP-A-6-104274. Nos. 0057 and 005 of this published patent publication
In paragraph 8, the element bump electrode 810 connected to the uppermost emitter of the mesa layer 611 of the vertical transistor 600 formed on the semiconductor substrate 500, and the dummy bump electrode 8
A configuration in which a metal structure 612 is formed below the dummy bump electrodes 831 and 832 in order to eliminate a difference in height between the dummy bump electrodes 31 and 832 is disclosed.

[0006]

However, the above-mentioned prior art has the following problems. That is,
A chip wiring having a plurality of different potentials, for example, a base wiring and a collector wiring in the case of a transistor chip;
In the case of a chip, the purpose is to balance the load applied to the chip in performing flip chip bonding with the input / output bump electrodes connected to the control voltage terminal and the power supply voltage terminal etc. The dummy electrode to be arranged may be peeled off at a joint portion with the wiring board, that is, at a joint portion between the bump electrode and the wiring electrode portion in the wiring board. In particular, if the input / output terminal bump electrode is peeled off, an open failure may occur, which is a serious problem.

The following can be considered as the cause of this failure. The height of these bump electrodes from the semiconductor chip substrate is lower than the height of the device bump electrodes existing above the transistor device due to the thickness of the semiconductor layer and other factors. This is because the bonding strength of the input / output terminal bump electrode is reduced. The input / output terminal bump electrodes are located relatively at the periphery of the chip, and the element bump electrodes are located relatively at the center of the chip. In general, the greater the distance from the stress neutral point, the more likely it is to receive a large stress due to thermal expansion or thermal contraction.

Therefore, it is inevitable that a greater stress is applied to the input / output terminal bump electrodes located relatively at the periphery of the chip. However, JP-A-6-104
Although the prior art of Japanese Patent No. 274 discloses that the height of a plurality of dummy bump electrodes not intended for electrical connection is adjusted to be equal to the height of an element bump electrode, the height of an input / output terminal bump electrode is adjusted. No measures have been taken. The phenomenon that the input / output terminal bump electrodes in the peripheral area are easily peeled off is that the number of input / output terminal bump electrodes in a chip having a large number of transistor elements is inevitably greater than that of a group of element bump electrodes that are inevitably densely arranged. This is noticeable because the arrangement tends to be small and sparse.

In some cases, some structural layer is provided below the chip wiring connected to the input / output terminal bump electrode so as to cross the direction in which the chip wiring extends to the outside on the main surface of the semiconductor chip. However, there is a possibility that the chip wiring may be disconnected at a portion traversed by the structural layer, resulting in an open defect. Such a phenomenon becomes more remarkable as the thickness of the structure layer is larger and the side surface of the structure layer is steeper.

In an element bump electrode provided in the vicinity of a transistor element, a part of the element bump electrode may be formed also in a portion directly above an intrinsic operation portion as a transistor element. In one element bump electrode, the height of a portion centered immediately above the intrinsic operation portion is increased by the influence of the stacked height of the semiconductor layers. When such a chip is flip-chip mounted, thermal stress and external stress applied to the element bump electrode, in particular, the load at the time of flip-chip bonding are indirectly transmitted to the intrinsic operation part of the transistor element, and the transistor element is damaged. There is a risk. Such phenomena are when the number of element bump electrodes is small and small, when the thickness of the bump electrode etc. above the intrinsic operation part of the transistor element is thin, or when the amount of collapse of the bump electrode etc. of the intrinsic operation part during flip chip mounting is large. It becomes remarkable.

An object of the present invention is to provide a structure in which an input / output terminal bump electrode or the like which is relatively present in the peripheral portion of a chip is unlikely to be peeled off at the time of bonding to a wiring board, and is hardly subjected to stress in an intrinsic operation portion. It is an object of the present invention to provide a semiconductor chip having the above, a manufacturing method thereof, a semiconductor element, and a semiconductor device.

[0012]

According to the present invention, there is provided a semiconductor device comprising a semi-insulating substrate and a semiconductor layer formed on the main surface of the semi-insulating substrate. A plurality of semiconductor elements each having a single element or a plurality of semiconductor elements each having a plurality of input / output terminal bump electrodes connected to a chip wiring having a different potential from the element bump electrodes. In the semiconductor chip, the input / output terminal bump electrode is provided between the lower side of the input / output terminal bump electrode and the semi-insulating substrate, is made of the same material as the metal or the semiconductor layer, and is based on the main surface of the semi-insulating substrate. The height of the semiconductor chip is lower than the height of the element bump electrode. According to the present invention, the input / output terminal bump electrode has the lower structure provided below, and the height from the surface of the semi-insulating substrate is equal to or higher than the height of the element bump electrode. In this case, the amount of crushing of the bump electrode or the like at the time increases, and the bonding strength can be increased, thereby eliminating the possibility of peeling or the like. Since the height of the device bump electrode is less than the height of the input / output terminal bump electrode, the crush amount of the bump electrode etc. during flip chip bonding may be relative or absolute in the portion directly above the intrinsically operating part of the semiconductor device. Therefore, stress is not applied to the intrinsic operation portion as a semiconductor element, and indirect damage can be reduced. In addition, the heat generated from the semiconductor chip during operation is radiated to the wiring board through the larger element bump electrode, and the element bump electrode which is not only thermally but also electrically connected has, for example, a top layer. When the emitter is connected to the ground electrode of the wiring board through the element bump electrode, the stability as ground increases. Each of these provides a more preferable form for application to a power amplifier or the like using microwaves.

Further, the present invention provides a method of manufacturing a semiconductor device, comprising: forming a lower structure on a main surface of a semi-insulating substrate from a lower structure below the input / output terminal bump electrode and above the lower structure of the input / output terminal bump electrode. It has a chip wiring connected to the outside, and the thickness of the lower structure is smaller than the thickness of the chip wiring. According to the present invention, since chip wiring is provided from the input / output terminal bump electrode to the main surface of the semi-insulating substrate,
When various elements constituting the MMIC, such as a transistor, a resistor, a spiral inductor, and a capacitor, are mounted on a semi-insulating substrate, they can be easily electrically connected. By providing the lower structure, even if the lower structure may cross the chip wiring in a portion connected from the lower structure to the main surface of the semi-insulating substrate, the thickness of the chip wiring is larger than the thickness of the lower structure. Since it is thick, it is possible to avoid a risk that an open defect occurs due to disconnection of the chip wiring.

Further, according to the present invention, the lower structure may be provided on the main surface of the semi-insulating substrate from the lower structure below the input / output terminal bump electrode and above the lower structure of the input / output terminal bump electrode. It is characterized by having a chip wiring connected to the outside, and including an electrically insulating resin layer immediately below a portion where the chip wiring is drawn out from the lower structure to the outside. According to the present invention, a chip wiring is provided above the lower structure below the input / output terminal bump electrode, and an electrically insulating resin layer is provided at a lead portion extending from the lower structure to the semi-insulating substrate main surface. As a result, the chip wiring can be smoothly drawn out, and the risk of occurrence of open failure due to disconnection of the chip can be further reduced. In addition, since the chip wiring is smoothly drawn out, the coverage of SiNx or the like as a passivation formed thereabove can be improved, and the moisture resistance of the semiconductor chip can be improved.

Further, according to the present invention, the lower structure may be formed on the main surface of the semi-insulating substrate from the lower structure below the input / output terminal bump electrode and above the lower structure of the input / output terminal bump electrode. It has a chip wiring connected to the outside, and the lower structure is formed in a mesa shape. According to the present invention, the substructure is formed in a multi-stage mesa shape. Since the thickness of the lower structure is divided and the thickness of one step becomes thinner,
Since the step is smaller than the thickness of the chip wiring as compared with the case where it is not formed in a mesa shape, disconnection of the chip wiring is less likely to occur, and the occurrence of an open defect due to this can be prevented.

Further, the present invention provides a step of sequentially laminating a plurality of semiconductor layers, which are constituent elements of a semiconductor element, on a main surface of a semi-insulating substrate, wherein an intrinsic operation portion of the semiconductor element and an input / output terminal bump are formed. A step of etching most of the semiconductor layer excluding the formed input / output section until the semiconductor layer reaches the semi-insulating substrate; and forming an element bump electrode and an input electrode on the intrinsic operation section including the periphery and the semiconductor layer of the input / output section. Forming a bump electrode including each of the output terminal bump electrodes.
According to the present invention, prior to the step of forming a bump electrode, a step of sequentially stacking semiconductor layers and a step of removing most of the stacked semiconductor layers until the semiconductor layers reach the semi-insulating substrate are removed. In the process, not only the intrinsic operation portion of the semiconductor element but also the input / output portion where the input / output terminal bumps are formed are left. Therefore, when the lower structure of the input / output terminal bump electrode is formed of the same material as the semiconductor layer, the etching removal is required. Substructures can be simultaneously formed in the process. When forming the bump electrodes in this manner, it is easy to make the height of the input / output bump electrodes from the main surface of the semi-insulating substrate equal to or higher than the height of the element bump electrodes. According to the invention, a lower structure (particularly, a mesa-shaped lower structure) or a semiconductor device having a device bump electrode shaped to further prevent damage to an intrinsically operating portion of the semiconductor device can be formed by photolithography. It can be formed only by changing the opening pattern of the chip structure, and furthermore, the chip wiring thicker than the lower structure, the electrically insulating resin layer immediately below the chip wiring in contact with the lower structure, etc. In some steps, they can be formed simultaneously only by changing the opening pattern in photolithography, and there is no need to add a new step. That is, it is possible to provide a means for producing a semiconductor chip that solves the problem in a very small process.

Further, the present invention has a vertical structure in which semiconductor layers are sequentially laminated on a main surface of a semi-insulating substrate, and between ohmic electrodes is insulated by mesa etching, and at least one ohmic electrode is formed. In a semiconductor element having an element bump electrode to be connected, the element bump electrode does not exist immediately above at least the intrinsic operation part of the semiconductor element, and at least a non-intrinsic operation part existing around the intrinsic operation part. Lead wiring formed in a shape that exists directly above a part of the non-intrinsic operation part, and connecting the element bump electrode that exists directly above at least a part of the non-intrinsic operation part and the uppermost layer of the vertical structure of the intrinsic operation part A semiconductor element characterized by including: According to the present invention, since the element bump electrode does not exist directly above the intrinsic operation portion of the semiconductor element having the vertical structure, when the semiconductor element is flip-chip bonded, the semiconductor element is pressed so as to have a sufficient crush amount. As a result, it is possible to increase the bonding strength, prevent peeling, and eliminate the possibility of indirectly damaging the intrinsically operating portion.

[0018]

Further, the present invention is a semiconductor device for mounting a semiconductor chip having an element bump electrode and an input / output bump electrode whose height from the main surface of the semi-insulating substrate is higher than the element bump electrode, A ground electrode is provided at a position where an element bump electrode of a semiconductor chip is to be bonded, and a wiring board having a wiring electrode is provided at a position where an input / output terminal bump electrode is to be bonded. On a main surface of the wiring substrate, A semiconductor device wherein a semiconductor chip is connected via the element bump electrode and the input / output terminal bump electrode. According to the present invention, sufficient input / output bump electrode bonding strength can be obtained at the time of flip chip bonding, and the possibility of damaging the intrinsic operation portion of the semiconductor chip through stress via the element bump electrodes can be eliminated. The device bump electrodes not only improve the heat dissipation from the semiconductor chip, but also improve the operating characteristics of the device by being grounded. Since input and output can be performed, a semiconductor device in a mounted form suitable for microwaves or the like can be realized at low cost.

Further, the present invention is characterized in that a gap between the connected semiconductor chip and the wiring board is sealed with an electrically insulating resin material. According to the present invention, the gap between the main surface of the semiconductor chip and the main surface of the wiring board, which is formed by the presence of the bump electrode at the connection portion, is sealed with an electrically insulating resin to provide moisture resistance and shock resistance. Reliability such as reliability can be improved.

[0021]

FIG. 1 shows a basic configuration of a first embodiment of the present invention. In the semiconductor chip 400, a vertical transistor element 600 as a semiconductor element is formed on a surface of a semiconductor chip base 500 as a semi-insulating substrate. The transistor element 600 has an element bump electrode 8
10 are arranged, and input / output terminal bump electrodes 820 are arranged on the periphery of the surface of the semiconductor chip substrate 500. A lower structure 612 is provided between the input / output terminal bump electrode 820 and the semiconductor chip base 500. Substructure 6
12, the semiconductor chip substrate 50
Input / output terminal bump electrode 820 from the surface which is the main surface
The height h _s, relative to the height h _t from the surface of the semiconductor chip substrate 500 of the element bump electrodes 810 are adjusted such that h _s ≧ h _t.

FIG. 2 shows the transistor element 60 shown in FIG.
0 shows the simplified outline of the active part. Transistor element 600 has, for example, an npn emitter-up vertical structure. Semiconductor layers corresponding to the collector, the base, and the emitter are sequentially stacked, and mesa layers 611C, 611B, and 611E are formed by mesa etching. As the vertical structure, for example, as shown in FIG. 2A, the stacked semiconductor layers have a uniform length in one direction, or as shown in FIG. There are types that are stacked concentrically.

FIG. 3 shows a sectional structure of a main part including an active part of the transistor element 600 of FIG. The vertical structure of the transistor element 600 includes FIGS.
3 (2a) and (2b)
The one-sided electrode type shown in FIG. FIGS. 3A and 3B are longitudinal sectional views, and FIGS. 3A and 3B are plan views. The semiconductor chip base 500 is formed of, for example, a semi-insulating GaAs (gallium arsenide) substrate. Semiconductor layers are sequentially stacked on the main surface of the substrate and subjected to mesa etching to form mesa layers 611C, 611B, 6
11E (hereinafter generically indicated by reference numeral 611). The mesa layers 611C, 611B, and 611E have ohmic electrodes 620C, 620B, and 620E serving as collector, base, and emitter electrodes, respectively. Ohmic electrodes 620C, 62 corresponding to collector and base
OB is electrically connected to the collector wiring 710C and the base wiring 710B via the extraction electrode portions 711C and 711B. 3 (1a) and (2a) are cross-sectional lines X of FIGS. 3 (1b) and (2b).
Each corresponds to a cross-sectional view seen from -Y.

FIG. 4 shows a configuration of a semiconductor chip 400 including a plurality of transistor elements 600 of both electrode types shown in FIGS. 3A and 3B. FIG.
(A) is a longitudinal sectional view, and corresponds to a state viewed from a cutting plane line XY in the plan view of FIG. 4 (b). Semiconductor chip 400
The transistor element 600 having a vertical structure including the element bump electrode 810 is formed in parallel at the center of the substrate. The ohmic electrode of the collector of each transistor element 600 is
Collector wiring 710C through extraction electrode section 711C
Is electrically connected to The collector wiring 710C is connected to an input / output terminal electrode portion 712C for a collector signal.
The ohmic electrode at the base of each transistor element 600 is connected to the base wiring 710 through the extraction electrode portion 711B.
B, and further connected from the base wiring 710B to the input / output terminal electrode portion 712B. Each input / output terminal electrode section 7
Above 12C and 712B, an input / output terminal bump electrode 820 for each signal is formed. As described above, the lower structure 612 is provided below the input / output bump electrode 820. In the vicinity of the device bump electrode 810, a dummy bump electrode 8 for heat radiation from the transistor device 600 is provided.
31 is also provided. Dummy bump electrodes 832 are also provided at the four corners of the semiconductor chip substrate 500 for the purpose of preventing inclination during flip chip bonding.

FIG. 5 shows the structure of the element bump electrode 810 to which the emitter is electrically connected in the transistor element 600 of FIG. FIG. 5A is a sectional view,
This corresponds to a state viewed from the cutting plane line XY in the plan view shown in FIG. FIG. 5 (c) is a plan view of the same, but the intrinsic operation part adjacent area 6 in a particularly close area of the intrinsic operation part 630.
FIG. 40 is a diagram illustrating a non-intrinsic operation unit 650 around the device 40; The active portion of the transistor element 600 is an elongated rectangular solid as shown in FIG. 2 and has a certain thickness, and is formed in a shape such that the longitudinal direction extends in a direction perpendicular to the paper of FIG. 5A. You. The portion immediately above the intrinsic operation section 630 as the transistor element 600 and the section of the intrinsic operation section 630
The element bump electrode 810 is formed so as to straddle the non-intrinsic operation part 650 located in the direction orthogonal to the longitudinal direction of the shape of the shape. The lead-out wiring 720 extends between the intrinsic operation part 630 and the non-intrinsic operation parts 650 on both sides.
Is formed. Specifically, on the lead wiring 720, more specifically, above the non-intrinsic operation part 650, the upper wiring 7
50, above the intrinsic operation unit proximity area 640 including above the intrinsic operation unit 630, without passing through the upper layer wiring 750,
A substantially H-shaped element bump electrode 810 having a planar shape is formed by gold plating.

Further, the element bump electrode 810 and the lead wiring 720 are electrically connected. Except for the ohmic electrode 620E electrically connected to the extraction electrode section 721 of the extraction wiring 720, the intrinsic operation section 63
In the intrinsic operation portion proximity region 640 including 0, the extraction wiring 7
20, an electrically insulating resin layer 920 such as polyimide
Is formed, and is electrically insulated from the other ohmic electrodes 620C and 620B.

Next, the "H" type here will be explained. The longitudinal direction of the elongated shape of the transistor element 600 and a part of the element bump electrode 810 extending in the same direction and located above the non-intrinsic operation section 650 are two parallel plane-shaped “H” characters. Form a stem. A part of the element bump electrode 810 extending in a direction orthogonal to the longitudinal direction of the transistor element 600 and located above the intrinsic operation part proximity region 640 including the non-intrinsic operation part 650 to the intrinsic operation part 630 to the non-intrinsic operation part 630 Corresponds to the horizontal bar of “H”.

[0028] Among the height of the units shown in FIG. 5, the height h _{t r} of the element bump electrodes 810 in the upper portion of the intrinsic operation unit close vicinity 640 including right above the intrinsic operation portion 630 of the transistor element 600, The semiconductor chip substrate 500 which is a semi-insulating substrate is formed to have a thickness of about 22 to 25 μm. Other parts, i.e. the height h _{t n} of the element bump electrodes 810 above the non-intrinsic operation unit 650, about 29μm
Formed. Therefore h _{t r} is lower than h _{t n.} That is, as shown in FIG. 5A, the bumps of the intrinsic operation section 630 are lower than those of the surrounding non-intrinsic operation section 650. The height h _s of the input / output terminal bump electrodes 820 described later is formed to be about 32 μm, and the height from the surface of the semiconductor chip substrate 500 is the highest. Therefore, when the semiconductor chip 400 is flip-chip mounted, the bonding strength of the input / output terminal bump electrodes 820 becomes relatively high. Also, the element bump electrode 810
In the intrinsic operation part 63 of the transistor element 600.
Straight upper portion corresponding to 0, the height h _{t r} is lower than the height h _{t n} of the other portion, for example load during bonding becomes difficult to apply to the intrinsic operation unit 630 also indirectly, transistor Damage to the element 600 can be avoided.

FIGS. 6 and 7 show an example of a process for manufacturing the semiconductor chip 400 as shown in FIG. As shown in FIG. 6A, a semiconductor layer 610 which is a component of the transistor element 600 having a vertical structure is sequentially stacked on the main surface of the semiconductor chip base 500. Next, FIG.
As shown in (b), the lower structure 61 of the mesa layers 611C, 611B, 611E and at least the input / output terminal bump electrode 820, which are the main components of the transistor element 600,
Most of the semiconductor chip substrate 500 except for the portion that becomes 2
Etching until it reaches. The method of etching removal is described in, for example, IEICE Technical Report ED90-1.
35 and other well-known methods can be employed. At this time, n of AlGaAs / GaAs
The mesa layers 611C, 611B, 611E of the pn emitter-up type transistor element 600 and the lower structure 612 below the bump electrode, especially the input / output terminal bump electrode 820.
Are simultaneously formed. Further, the shape of the lower structure 612 is formed so that the periphery thereof has a multi-stage mesa shape, as described later. In order to form the lower structure 612 below the input / output terminal bump electrode, it is only necessary to modify the etching pattern for selectively removing the stacked semiconductor layers, and it is not necessary to add a new process. In this state, ohmic electrodes 620E, 620B, and 620C for the emitter, base, and collector are also formed.

FIG. 6C shows a state in which polyimide is used as the interlayer insulating film and the electrically insulating resin layer 920 is formed so as to cover the base and collector ohmic electrodes 620B and 620C. A state in which the ohmic electrode 620E of the emitter is opened, and at the same time, an electrically insulating resin layer 920 is formed using polyimide also on a part immediately below the part where the chip wiring of the input / output terminal bump electrode is exposed to the outside of the lower structure 612. Is shown. Therefore, in order to form the electrically insulating resin layer 920 for preventing disconnection of the wiring at the periphery of the lower structure 612, it is only necessary to change the opening pattern, and it is not necessary to add a new process. In addition, the description of the shape of the electrically insulating resin layer 920 in the vicinity of the input / output terminal bump electrode is added. When the lower structure 612 is formed in a mesa shape, the lower structure 612 is covered, and the vicinity of the input / output terminal bump electrode is opened. Shape.

FIG. 6 (d) shows that titanium (Ti) /
An H-type emitter lead-out wiring 720 is formed using platinum (Pt) / gold (Au), and a chip wiring 700 of the input / output terminal bump electrode 820 is formed at the same time. Note that the chip wiring 700 includes a base wiring 710B connected from the ohmic electrode 620B of each base to the input / output terminal electrode part 712B of the base signal through the lead electrode part 711B of each base, ie, each base wiring lead electrode part and the base. Wiring between the signal input and output terminals is included. Also, a collector wiring connected from the ohmic electrode of each collector to the collector signal input / output terminal electrode through each collector lead electrode, that is, a wiring between each collector lead electrode and the collector signal input / output terminal electrode. Is also included.

FIG. 6E shows a state in which SiNx is then used to deposit a passivation film 910. The passivation film 910 is formed as an insulating layer for forming an impedance matching circuit together with a spiral inductor and the like formed on the semiconductor chip, and also functions as an MIM (Metal-Insulator-Metal Capacitor) film. By photolithography and buffered hydrofluoric acid etching, a portion where a bump electrode is provided, a contact portion with the upper layer wiring 750, and the like are opened. The illustration of the passivation film 910 is omitted in the description of the subsequent steps.

In FIG. 7F, the protection resist 9 is thereafter formed.
After application of No. 30 and opening of a predetermined portion, a metal 740 for upper layer wiring plating is formed on the entire surface. Subsequently, a state is shown in which an upper layer wiring plating resist 932 is applied and a predetermined portion is opened. The opening of the protective resist 930 by photolithography corresponds to a region where the upper wiring 750 is to be provided. An upper layer wiring is not provided in a portion above the intrinsic operation portion proximity region 640 including immediately above the intrinsic operation portion 630 of the transistor element 600, and an upper layer wiring is provided in a portion 650 a above the non-intrinsic operation portion 650 in the immediate vicinity. In this embodiment, the resist 932 for plating the upper layer wiring is opened so as to be substantially H-shaped in plan view. At the same time, in the portion where the upper layer wiring of the input / output terminal bump electrode is formed, at least the chip 932 for plating the upper layer wiring near the portion 612 a where the chip wiring to the input / output terminal bump electrode goes out of the lower structure 612.
To open.

As the metal 740 for plating the upper wiring, Ti / Au is used. Upper layer wiring plating resist 9
An opening 32 by photolithography is a portion where an upper layer wiring is provided. Therefore, even if an upper layer wiring thicker than the lower structure 612 is formed in order to prevent disconnection of the wiring, it is only necessary to change the opening pattern, and it is not necessary to add a new process. Also, the transistor element 600
In order to reduce the height of the portion directly above the intrinsic operation portion 630, that is, the height from the surface of the semiconductor chip substrate 500 which is a semi-insulating substrate, for the purpose of preventing damage to the semiconductor device, only the opening pattern is changed. Should be performed.

FIG. 7 (g) shows the upper wiring 7 by plating.
After the formation of the wiring 50, the resist 932 for plating the upper layer wiring shown in FIG.
7 shows a state in which gold (Au) other than the chip wiring 700 is removed by etching, and titanium (Ti) other than the chip wiring 700 is removed by lift-off using a protective resist 930 shown in FIG. In this embodiment, the thickness of the upper layer wiring 750 is 9 μm, and the thickness of the upper layer wiring 750 is 9 μm. Of the transistor element 6
00 mesa height of 0 to 3 μm + polyimide thickness of 0
2 μm = 0 to about 5 μm. Transistor element 60
Since the thickness above the non-intrinsic operation portion 0 is about 9 μm in the thickness of the upper layer wiring 750, a difference of about 4 to 9 μm from above the region near the intrinsic operation portion 640 occurs. In addition, the height of the input / output terminal electrode portion is about 12 μm = thickness of the lower structure 612 which is a semiconductor layer + 9 μm of upper wiring = 12 μm. In addition, since the input / output terminal bump electrode is not formed above the mesa-shaped portion of the lower structure 612 as described later, it is excluded from the height comparison.

FIG. 7 (h) shows that after the application of the protective resist 933 and the opening treatment, the bump plating metal 76 is formed on the entire surface.
0 is formed, and subsequently, a resist 934 for bump plating is applied and opened. The opening of the protective resist 933 by photolithography corresponds to a region where a bump electrode including an element bump electrode and an input / output terminal bump electrode is to be provided. In the present embodiment, an H-shaped opening is formed so as to extend directly above the intrinsic operation part and above the non-intrinsic operation part of the transistor element for the element bump electrode. At the same time, a circular opening is formed for the input / output terminal bump electrode. An opening for a dummy bump electrode other than the element bump electrode and the input / output terminal bump electrode is also formed. Ti / Au is used as the metal 760 for bump plating. The opening of the bump plating resist 934 by photolithography also corresponds to the portion where the bump electrode is provided.

FIG. 7 (i) shows that after the bump electrodes are formed by plating, the bump plating resist 9 shown in FIG.
34 shows a state in which Au is removed by etching other than immediately below the bump electrode, and Ti other than immediately below the bump electrode is removed by lift-off using the protective resist 933. In the present embodiment, the planar shape is changed to the element bump electrode 8.
Reference numeral 10 denotes an H type, and the input / output terminal bump electrode 820 and the dummy bump electrode are circular. The thickness of the bump electrode only, that is, the thickness of the gold plating is basically uniform irrespective of the height of the part to be formed from the reference plane is high or low, but the step part is plated gently. , A little thick thin results. In this embodiment, the thickness of only the bump electrode is basically 20 μm, reflecting the “difference of about 4 to 9 μm” described in the description of FIG. A difference of about 4 to 9 μm in height from the semiconductor chip substrate 500 occurs in the vicinity of the intrinsic operation part proximity region 640 without the wiring 750 and above the non-intrinsic operation part 650 with the upper wiring 750. However, due to the stepped portion, the finish after plating is slightly gentler than before plating. By this process, the thickness of the element bump electrode 810 above the intrinsic operation part proximity area 640 including immediately above the intrinsic operation part 630 of the transistor element 600 is: the mesa thickness of the transistor element 600 + the polyimide thickness 0-2 μm + the bump electrode Thickness 20 μm = 2
It becomes about 0 to 25 μm. The thickness of the element bump electrode 810 above the non-intrinsic operation part 650 of the transistor element 600 is 9 μm of the thickness of the upper wiring 750 + 20 μm of the bump electrode thickness.
μm = about 29 μm. Also, the input / output terminal bump electrode 8
The thickness of 20 is about 32 μm = thickness of lower structure 612 as a semiconductor layer + thickness of upper wiring 750 9 μm + bump electrode thickness 20 μm. After that, lapping, dicing, and the like are performed by a normal method to complete the semiconductor chip.

As described above, the semiconductor chip 400 as shown in FIG. 4, that is, the semiconductor chip 400 having the feature that not only the lower structure 612 is provided but also the shape of the transistor element 600 is devised, is shown in FIGS. It is manufactured in each step shown in FIG. As apparent from the individual description of each step, the semiconductor chip 400 of the present embodiment can be manufactured without adding a new step to the conventional step. If the height of the input / output bump electrode 820 is particularly increased in forming the bump electrode without providing the lower structure 612, it is necessary to perform the plating of the bump twice including the patterning step. Additional steps occur.

FIGS. 8 and 9 show the structure of a transistor element 600 according to the second and third embodiments of the present invention. In the second embodiment shown in FIG. 8, the upper wiring 750 is not formed as in the first embodiment shown in FIG.
The device bump electrode 810 is formed directly on the substrate 20. FIG.
In the third embodiment, an upper layer wiring 750 is formed on a lead wiring 720 over an intrinsic operation section 630 and non-intrinsic operation sections 650 on both sides, and an element bump electrode 8 is formed thereon.
Form 10. Lead wiring 720, upper wiring 750
The planar shape of the element bump electrode 810 is H-shaped as an example of a preferable shape, but may be another shape. In the shape of these element bump electrodes 810, the case shown in FIG. 5 (that is, by using a pattern in which the upper layer wiring 750 is not formed in the intrinsic operation part proximity area 640 including the intrinsic operation part 630, 810 may have a higher stress at the time of flip chip bonding. However, if the lower structure 612 is provided as shown in FIGS. 6 and 7 and the height of the input / output bump electrodes is made higher as a semiconductor chip, the stress applied to the element bump electrodes 810 is reduced. .

FIG. 10 shows the structure of a transistor element 600 according to the fourth embodiment of the present invention. FIG. 10A is a longitudinal sectional view, and corresponds to a state viewed from a cutting plane line XY in the plan view of FIG. In the first to third embodiments, the element bump electrode 810 is formed over the intrinsic operation section 630 of the transistor element 600 and the non-intrinsic operation sections 650 on both sides. From the extraction electrode portion 721 on the upper surface of the ohmic electrode 620E of a certain emitter, the extraction wiring 720 is extracted in an arch shape to both sides in the direction orthogonal to the longitudinal direction of the top layer, and a part of the extraction wiring 720, that is, the non-intrinsic operating portions on both sides 65
An element bump electrode 810 is formed in a portion corresponding to an area above zero. In the present embodiment, the lead wiring 720 extends over the intrinsic operation unit 630 and the non-intrinsic operation units 650 on both sides.
Is formed. An upper layer wiring 750 is formed on the lead wiring 720 over the intrinsic operation section 630 and the non-intrinsic operation sections 650 on both sides. On the upper layer wiring 750, the device bump electrodes 810 are provided on both sides of the non-intrinsic operation section 650.
Is formed substantially in an H-shape by gold plating.
Further, the element bump electrode 810 and the lead wiring 720 are electrically connected. Except for the ohmic electrode 620E of the emitter joined to the extraction electrode section 721 of the extraction wiring 720, the portion immediately below the extraction wiring 720 corresponding to the intrinsic operation section proximity area 640 including the intrinsic operation section 630 is an electrically insulating resin layer of polyimide. 920 are formed, and are insulated from the other ohmic electrodes 620C and 620B.

[0041] The addition of description the height of the portions shown in FIG. 10, the height h _t from the surface of the semiconductor chip substrate 500 of the non-intrinsic operation unit 650 in the presence of the element bump electrode 810
_n is formed to be about 29 μm. The height h _{t r} of the upper portion corresponding intrinsic operation unit close vicinity 640 including right above the existent intrinsic operation unit 630 of the device bump electrodes 810 11
It is formed to about 14 μm. The height of an input / output terminal bump electrode 820 described later is formed to be about 32 μm, which is the highest. For this reason, in the state where the flip-chip bonding is performed, the crushing amount of the input / output terminal bump electrode 820 due to the bonding becomes larger than the crushing amount of the element bump electrode 810, so that the input / output terminal bump electrode 81 is formed.
The bonding strength of 0 becomes relatively high. In addition, the portion immediately above the intrinsic operation section 630 of the transistor element 600 has the lowest height without the element bump electrode 810. For example, the connection height is about 2 by bonding.
In the case of the bonding condition of 1 μm, the crushing amount of the input / output terminal bump electrode by bonding is about 11 μm.
m, the element bump electrode 81 existing in the non-intrinsic operation section 650
The crush amount of 0 is about 8 μm. On the other hand, the bonding load is basically not transmitted to the intrinsic operation part 630 of the transistor element 600, and the transistor element 600 is not damaged.

FIGS. 11 and 12 show the structure of a transistor element 600 according to the fifth and sixth embodiments of the present invention, respectively. FIGS. 11 and 12A are longitudinal sectional views of the respective transistor elements 600. FIG. FIG.
(B) is a plan view of the transistor element 600. FIG.
FIG. 2A corresponds to a cross-sectional view taken along line XY of FIG. 12B. A plan view of the transistor element 600 shown in FIG. 11 also appears as in FIG. Fifth of FIG.
In the embodiment, the element bump electrode 810 is formed in a portion excluding the region above the intrinsic operation portion proximity region 640 without forming the upper layer wiring. In the sixth embodiment shown in FIG. 12, after the upper layer wiring 750 is formed once on the portion above the non-intrinsic operation portion 650 except above the region near the intrinsic operation portion 640, the element bump electrode 810 is formed. In the fifth and sixth embodiments, the lead-out electrode 720 is used for the lead-out wiring 720.
1 except for the ohmic electrode 620E of the emitter joined to the intrinsic operation part 630 including the intrinsic operation part 630.
The air bridge 730 is formed by providing a gap immediately below the lead wire 720 existing in the above. Therefore, the electrically insulating resin layer 920 made of polyimide or the like as in the fourth embodiment is not provided. Also, the lead wiring 720, the upper wiring 750,
In addition, the shape of the element bump electrode 810 is not limited to the illustrated shape, and may be another shape.

FIG. 13 shows, as a seventh embodiment of the present invention, a semiconductor chip 400 having a transistor element group including a double-sided electrode type npn emitter-up transistor element 600. In the present embodiment, the semiconductor chip 40
A plurality of transistor elements 600 each having a vertical structure and having an element bump electrode 810 are formed in parallel at the center of the zero.
Unlike the first to sixth embodiments described so far, the transistor element 600 in parallel from the intrinsic operation portion of the elongated transistor element 600 to one side in the longitudinal direction, more specifically, from the ohmic electrode 620E of the emitter as the top layer. To the side symmetric with respect to the base wiring 710B parallel to the arrangement direction of the group
Pull out. An element bump electrode 810 is formed above the lead wiring 720. The collector wiring 710C is connected to the collector signal input / output terminal electrode portion 712C from the ohmic electrode 620C of each collector through each collector extraction electrode portion 711C. Similarly, from each ohmic electrode 620B of each base to each base lead-out electrode portion 711
Through B, a base wiring 710B is connected to an input / output terminal electrode portion 712B of a base signal. Each input / output terminal electrode section 7
Above 12C and 712B, the input / output terminal bump electrode 8
20 is provided, and a lower structure 612 is interposed below it. In the vicinity of the element bump electrode 810, a dummy bump electrode 831 that is not electrically connected is provided for heat radiation from the transistor element 600 or the like.

FIG. 14 shows the structure of the transistor element group shown in FIG. The ohmic electrode 620C of the collector of each transistor element 600 is electrically connected to the ohmic electrode 620C of the adjacent collector. The collector wiring 710C connected to the ohmic electrode 620C of the collector forms an air bridge 730 except for the collector extraction electrode portion 711C.

FIG. 15 shows the structure of a transistor element 600 according to the seventh embodiment. FIG. 15A is a longitudinal sectional view, and FIG.
5 (b) shows a plan view, and FIG.
A cross-sectional view as viewed from Y corresponds to FIG. From the intrinsic operation part 630 of the elongated transistor element 600,
The lead-out wiring 720 is drawn out to one side in the longitudinal direction, specifically, from the ohmic electrode 620E of the emitter as the top layer in a direction perpendicular to the direction in which the base wiring 710B extends. An upper layer wiring 750 is formed on a part of the lead wiring 720, and an element bump electrode 810 by plating is formed on a part of the upper layer wiring 750. The element bump electrode 810 and the lead wiring 720 are electrically connected. Extraction electrode portion 721 of extraction wiring 720
Except for the ohmic electrode 620E of the emitter joined to the substrate, immediately below the lead wire 720 on the side where the element bump electrode 810 exists, the electrically insulating resin layer 9 made of polyimide is used.
At 20, it is electrically insulated from other ohmic electrodes and chip wiring. In the present embodiment, the transistor element 6
In a portion directly above the intrinsic operation portion 630 of 00, the collector wiring 710C forming the air bridge 730 passes, and the element bump electrode 810 does not exist. Therefore, if the flip-chip bonding is performed under the condition that the collector wiring 710C does not contact the wiring board wiring, the bonding load is basically not applied to the intrinsic operation part 630 of the transistor element 600, and the transistor element 600 is not damaged.

FIGS. 16 and 17 show the structure of a transistor element 600 according to the eighth and ninth embodiments of the present invention, respectively. 16 and 17 (a) are longitudinal sectional views,
FIG. 17B is a plan view. FIG. 17A corresponds to a state viewed from the section line XY of FIG. 17B. In the eighth embodiment shown in FIG. 16, the element bump electrode 810 is formed on the lead-out wiring 720 on the non-intrinsic operation part 650 without forming the upper-layer wiring 750. The ninth shown in FIG.
In the embodiment, the thick lead wiring 720 is formed entirely, and the element bump electrode 810 is formed thereon. In the case of these embodiments, since the air bridge 730 is formed by the lead-out wiring 720 at a portion above the collector wiring 710C, it is necessary to consider the height relationship and the time of formation and bonding. For example, the collector wiring 71
0C may be formed as an arched lead-out wiring 720 on the symmetrical side of the base wiring 710B without air bridging. Although the element bump electrode 810 and the lead wire 720 are electrically connected, the lead wire 720 in this portion may be formed as an air bridge 730 directly under the lead wire 720 without using an insulator such as polyimide. it can. Further, the shapes of the lead wiring 720 and the element bump electrode 810 are not limited to the shapes shown in the figure, and can be freely selected.

FIGS. 18 and 19 show a structure related to the input / output terminal bump electrode 820 according to the tenth and eleventh embodiments of the present invention. FIGS. 18 and 19A are longitudinal sectional views, and FIGS. 18 and 19B are plan views, respectively. FIG. 18A is a sectional view taken along the line XY of FIG.
This corresponds to a cross-sectional view as viewed from above. Input / output terminal bump electrode 82
Below 0, there is a lower structure 612 made of the same material as the semiconductor layer. Below the input / output terminal bump electrode 820 and above the lower structure 612, there is provided a chip wiring 700 connected from the lower structure 612 to the outside. In the tenth embodiment, a thick chip wiring 700 is formed. Eleventh
An electrically insulating resin layer 920 made of polyimide is provided immediately below a portion where the chip wiring 700 of the embodiment is exposed to the outside of the lower structure 612 on the main surface of the semiconductor chip. This polyimide is formed so as to cover the side surface of the steep lower structure 612 and have a gentle shape. For this reason, an open shift failure due to disconnection of the chip wiring at a portion where the lower structure 612 crosses is less likely to occur. Also, due to the smoothness of the polyimide, the coverage of SiNx as the passivation film 31 formed thereon is improved,
As a result, the moisture resistance of the semiconductor chip 400 can be improved.

FIG. 20 shows a configuration of an input / output terminal bump electrode 820 according to the twelfth embodiment of the present invention. FIG.
20A shows a vertical cross-sectional view, FIG. 20B shows a plan view, and FIG. 20A corresponds to a cross-sectional view taken along line X-Y of FIG. 20B. The lower structure 612 is made of the same material as the semiconductor layer, and the chip wiring 700 connected to the outside is drawn out from below the input / output terminal bump electrode 820.
The chip wiring 700 is provided on the lower structure 6 on the peripheral surface of the semiconductor chip.
In the portion immediately before being drawn out of the substructure 12, the lower structure 6
A mesa-shaped portion 612b in which the shape of the substrate 12 is a multi-stage mesa is formed. With this shape, the thickness of the lower structure 612 is divided and the thickness of one step is reduced, so that an open failure due to disconnection of the chip wiring 700 is less likely to occur.

FIG. 21 shows a configuration of an input / output terminal bump electrode 820 according to the thirteenth embodiment of the present invention. FIG.
21A is a longitudinal sectional view, FIG. 21B is a plan view, and FIG. 21A is a sectional view taken along the line X-Y of FIG. 21B. The input / output terminal bump electrode 820 according to the thirteenth embodiment has a combined shape with the input / output terminal bump electrode 820 according to the tenth to twelfth embodiments. Therefore, the synergistic effect is remarkably enhanced, and the chip wiring 700 is hardly disconnected. The lower structure 612
In addition, the input / output terminal bump electrode 8
The periphery of the lower structure 612 is formed in a mesa shape so as to surround 20. Also, an electrically insulating resin layer 92 made of polyimide.
If the shape of 0 is added, the shape covers the mesa-shaped portion 612c of the lower structure 612 and has an opening 700a near the input / output terminal bump electrode 820.

The heights of the input / output terminal bump electrodes 820 and the element bump electrodes 810 from the surface of the semiconductor chip substrate 500 differ depending on whether or not the upper wiring 750 is formed. The input / output terminal bump electrode 820 is
The height is adjusted to be equal to or higher than 10 heights. Further, as a material of the lower structure 612,
Instead of the semiconductor layer as in the above embodiment, a metal or the like forming the chip wiring 700 can be used. These can also be used in combination. The lower structure 612
Although it is conceivable to use an electrically insulating resin such as polyimide as a material for the material, in consideration of adhesion and process convenience, etc., it is not used, or when used, it is not used alone, but rather with a semiconductor layer or metal. It is desirable to use them together.

FIG. 22 shows the basic structure of the semiconductor device 100 according to the fourteenth embodiment of the present invention. FIG. 22A is a longitudinal sectional view, FIG. 22B is a plan view, and FIG.
(A) corresponds to a cross-sectional view taken along the line XY of FIG. 22 (b). In the semiconductor device 100 according to the present embodiment, the semiconductor chip 400 having the transistor element 600 having the vertical structure is connected to the wiring board 30 having the wiring board wiring 320.
0, elements and input / output terminal bump electrodes 810, 82
Flip-chip connection via 0 or the like. Wiring board 3
00 is an LCC in which a wiring board wiring 320 is formed of Au on a wiring board substrate 310 made of AlN (aluminum nitride).
It is a substrate. With respect to the wiring board wiring 320, the position where the element bump electrode 810 should be joined is the ground electrode 340,
The positions where the input / output terminal bump electrodes 820 should be joined are the respective wiring board electrode portions 330. A of the wiring substrate 310
1N, Au used for the wiring board wiring 320, the bump electrode, and the upper layer wiring is a material having good thermal conductivity, so that the heat from the transistor element 600 can be efficiently dissipated to the wiring board 300 side. Also in the semiconductor chip 400 having the transistor element group, favorable electric characteristics can be obtained. In the present embodiment, the area directly below the semiconductor chip 400, that is, the gap between the semiconductor chip 400 and the wiring board 300 is filled with the interface resin 200 such as an epoxy resin or a silicone resin. Performance, thermal history, and mechanical reliability can be improved. Further, by using a resin having excellent thermal conductivity as the interface resin 200, the heat dissipation can be further improved.

FIG. 23 shows a semiconductor device 1 according to the fourteenth embodiment.
00 shows a part of the process of manufacturing the “00”. In FIG. 23 (a),
7 shows an alignment step of aligning the semiconductor chip 400 and the wiring board 300. The semiconductor chip 400 is vacuum-adsorbed to the tip of the bonding tool 350 of the bonder, and the wiring board 300 is vacuum-adsorbed to the stage 360 of the bonder. Next, a bonding step shown in FIG. The bonding condition is such that the crushing amount of the bump electrode 800 such as an element bump electrode, an input / output bump electrode or a dummy bump electrode due to bonding is about 10%.
The pressure, the heating temperature and the heating time are adjusted so as to be μm. In this embodiment, the input / output terminal bump electrode 820 is used.
Is about 11 μm, that is, the pressure is 1.
0 kg / cm ² , a heating temperature of 350 ° C., and a heating time of 5 seconds. For the heating during bonding, a pulse heating method is used, and heat applied to the transistor element 600 and the like is reduced as much as possible.

FIG. 23B shows a crushed state of the element and the bump electrodes 800 such as the input / output terminal bump electrodes 810 and 820 by bonding. As shown in FIG. 24B, the crush amount p _s of the input / output terminal bump electrode 820 is about 1
When the height is 1 μm, the height h _b from the surface of the semiconductor chip substrate 500 after connection to the wiring board wiring 320 is about 21 μm.
The case of the bonding condition where m is taken is taken as an example. That is, crush amount p _s of the input and output terminal bump electrodes 820 yuan height of about 32μm is about 11 [mu] m. At this time, as shown in FIG. 24A, the crush amount p _tn of the element bump electrode in the portion corresponding to the non-intrinsic operation part 650 of the element bump electrode 810 whose original height is about 29 μm is about 8 μm.
The crush amount _ptr of the element bump electrode in a portion corresponding to the intrinsic operation portion 630 of the element bump electrode 810 having an original height of about 25 μm is about 4 μm. The larger the amount of collapse, the greater the bonding strength of the bump electrode. Therefore, in this embodiment, the bonding strength of the input / output terminal bump electrode 820 is higher than the bonding strength of the element bump electrode 810. On the other hand, in the configuration after the flip-chip connection, the thermal stress and the like become larger at the bumps at the peripheral portion of the chip. Even if the input / output terminal bump electrode 820 is arranged around the chip, its bonding strength is relatively high,
Open failure due to peeling between the bump electrode and the joint of the wiring board 300 is less likely to occur. Further, in the element bump electrode 810, since the crush amount p _tr in a portion immediately above the intrinsic operation section 630 is small, it is difficult for the bonding load to be transmitted to the intrinsic operation section 630 at the time of bonding or the like, so that the transistor element 600 may be damaged. Can be prevented.

FIG. 23C shows a step of injecting the interface resin 200. In this embodiment, an interface resin 200 such as an epoxy-based resin or a silicone-based resin containing no filler is dropped and injected into the end of the semiconductor chip 400 from the nozzle 210 of the dispenser. Interface resin 20
0 penetrates into the gap between the semiconductor chip 400 and the wiring substrate 300 without entrapping bubbles or the like due to capillary action. Note that a material having a small dielectric constant is used as the interface resin 200 so that the influence on the high-frequency operation is reduced.
In this embodiment, a resin containing no filler is used as the interfacial resin 200 so as to easily enter the gap between the semiconductor chip 400 and the wiring substrate 300. A material containing a sufficiently small fine filler may be used. FIG. 23D shows a step of curing the interface resin 200. In this embodiment, heating is performed at 150 ° C. for 2 hours in a nitrogen gas atmosphere. In the present embodiment, although the gap between the semiconductor chip 400 and the wiring board 300 is sealed with the interface resin 200, the gap is not necessarily required. Alternatively, coating may be performed so as to cover the semiconductor chip 400 as a whole.

In each of the embodiments described above, the collector, the base, and the emitter are formed on the semiconductor chip substrate 500 in this order as an npn emitter-up type vertical structure. , A base and a collector may be formed on the semiconductor chip substrate 500. Further, the conductivity type of the semiconductor layer can be changed to a conductivity type different from the conductivity type shown in each embodiment. The bipolar transistor can also be a so-called single hetero bipolar transistor (SHBT) in which only the emitter has a large band cap, or a so-called double hetero bipolar transistor (DHBT) using a wide band gap material for the collector. Further, a method of reducing the base-collector capacitance Cbc by implanting O ⁺ , B ⁺ , H ⁺ ions, etc. directly below the external base, or a combination with an element isolation method by ion implantation is also possible.

In the first to fourteenth embodiments, the HBT has been described as an active element. However, in the case of a vertical structure element, for example, a normal bipolar transistor, a thyristor, a HET (Hot Electron Transistor), a resonance tunnel transistor, or the like is used. The invention is equally applicable. In the case of a lateral structure element, an FET (FieldEffec
t Transistor), horizontal bipolar transistor, HEM
T (High Electron Mobility Transistor) etc.
The present invention is also applicable to a combination of these or a combination with a light emitting or light receiving element. In each embodiment, a transistor chip for microwave power amplification is described as an example, but the present invention is also applicable to an MMIC chip having various semiconductor elements described above, an integrated circuit for ultra high speed, and the like. In each embodiment, the element bump electrode 81
Although 0 also plays a role as an emitter signal electrode, it may be inconvenient if the bump electrode is an emitter or a source depending on the application of an MMIC chip or an ultra-high-speed integrated circuit that handles large power. In such a case, the bump electrode may be connected to a base or a gate, a collector or a drain, or not used as an electrode, but may be used only for heat diffusion by a method such as via an insulating film.

The material of the semiconductor chip 400 that can be used in each embodiment is not limited to GaAs, but may be a compound semiconductor such as InP, SiC, or GaP, or an element semiconductor such as C or Si. You may. In addition, the element itself is, for example, an AlGaAs / GaAs system,
InGaP / GaAs, InGaAs (P) / InA
An lAs system, InGaAs (P) / InP system and other lattice matching systems may be used, and InGaAs / AlGaAs may be used.
A lattice mismatching system such as / InP may be used.

Further, in each embodiment, the wiring board 300 is made of Au as the wiring board 300 by flip-chip connection.
An AlN substrate on which 20 is formed is used. Other materials having good thermal conductivity, such as SiC to which beryllium oxide (BeO) is added, can also be used. Further, the wiring substrate 300 does not necessarily need to be a single planar plate, and may have a so-called through hole or via hole, or may have a structure other than a flat surface such as a laminated substrate. In each embodiment, heat radiation from the back surface side of the semiconductor chip 400 is not particularly intended. Naturally, it is also possible to combine with a method of shaving the back surface of the semiconductor chip 400 thinly and dissipating heat via the heat transfer solder or the case cap.

[0059]

As described above, according to the present invention, the height of the input / output terminal bump electrodes of the semiconductor chip from the surface of the semi-insulating substrate is adjusted to be higher than the height of the element bump electrodes of the semiconductor element. In addition, the bonding strength of the input / output terminal bump electrode can be relatively enhanced at the time of flip-chip mounting, and peeling of the joint portion with the wiring board can be prevented.

Further, according to the present invention, since the chip wiring is provided from the input / output terminal bump electrode, when various elements constituting the MMIC such as a transistor, a resistor, a spiral inductor, and a capacitor are mounted on a semi-insulating substrate. In addition, electrical connection and coupling can be easily performed. By providing the lower structure, even if the lower structure may cross the chip wiring in a portion connected to the main surface of the semi-insulating substrate, since the thickness of the chip wiring is thicker than the thickness of the lower structure, It is possible to avoid a risk that the chip wiring is disconnected and an open defect occurs.

According to the present invention, a chip wiring is provided, and an electrically insulating resin layer is provided at a lead portion extending from the lower structure to the semi-insulating substrate main surface. As a result, the chip wiring can be smoothly drawn out, and the risk of occurrence of an open defect due to disconnection can be further reduced. In addition, since the chip wiring is smoothly drawn out, the coverage of SiNx or the like as a passivation formed thereabove can be improved, and the moisture resistance of the semiconductor chip can be improved.

Further, according to the present invention, the lower structure is formed in a multi-stage mesa shape. Since the thickness of the lower structure is divided and the thickness of one step is reduced, it is difficult for the lead-out portion of the chip wiring to contact, and the occurrence of an open defect due to disconnection of the step can be prevented.

Further, according to the present invention, before the step of forming a bump electrode, a step of sequentially stacking semiconductor layers and a step of removing most of the stacked semiconductor layers until the semiconductor layers reach the semi-insulating substrate. Including. When the lower structure of the input / output terminal bump electrode is formed of the same material as the semiconductor layer, the lower structure can be formed simultaneously with the etching removal process. When the lower structure is present, it is easy to form the bump electrode with a height of the input / output bump electrode from the main surface of the semi-insulating substrate equal to or higher than the height of the element bump electrode.

Further, according to the present invention, there is no element bump electrode just above the intrinsic operation part of a semiconductor device having a vertical structure. In the case of flip chip bonding of a semiconductor element, it is necessary to increase the bonding strength by pressing so as to have a sufficient amount of crushing, prevent peeling, and eliminate the possibility of indirectly damaging the intrinsic operation part. it can.

[0065]

Further, according to the present invention, sufficient bonding strength between input and output bump electrodes can be obtained at the time of flip chip bonding, and the possibility of damaging the intrinsic operation portion of the semiconductor chip through stress through the element bump electrodes can be eliminated. be able to. The heat dissipation from the semiconductor chip can be improved by the element bump electrodes, and the electrical connection for signal input / output can be performed by the input / output bump electrodes. This makes it possible to realize a semiconductor device having a mounting form suitable for microwaves or the like at low cost.

Further, according to the present invention, reliability such as moisture resistance can be improved by sealing the connection portion with an electrically insulating resin. Further, the semiconductor device can be formed in a mounting mode suitable for handling high-heat and high-frequency signals, and can greatly contribute to the practical use of an HBT for microwave power amplification.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view showing a basic configuration of a first embodiment of the present invention.

FIG. 2 is a simplified perspective view showing an appearance of an active portion of an npn emitter-up transistor element used in the first embodiment.

FIGS. 3A and 3B are a vertical sectional view and a plan view showing a configuration of a main part including an active part of an npn emitter-up type transistor element used in the first embodiment. FIGS.

FIGS. 4A and 4B are a vertical sectional view and a plan view showing a configuration of a semiconductor chip according to a first embodiment.

FIGS. 5A and 5B are an enlarged longitudinal sectional view and a plan view showing a transistor element according to the first embodiment; FIGS.

FIG. 6 is a series of longitudinal sectional views showing a method for manufacturing the transistor chip of the first embodiment.

FIG. 7 is a series of longitudinal sectional views showing a method for manufacturing the transistor chip of the first embodiment.

FIG. 8 is an enlarged longitudinal sectional view showing a transistor element according to a second embodiment of the present invention.

FIG. 9 is an enlarged longitudinal sectional view showing a transistor element according to a third embodiment of the present invention.

FIG. 10 is an enlarged longitudinal sectional view and a plan view showing a transistor element according to a fourth embodiment of the present invention.

FIG. 11 is an enlarged longitudinal sectional view showing a transistor element according to a fifth embodiment of the present invention.

FIG. 12 is an enlarged longitudinal sectional view and a plan view showing a transistor element according to a sixth embodiment of the present invention.

FIG. 13 is a plan view showing a semiconductor chip according to a seventh embodiment of the present invention.

FIG. 14 is a partial longitudinal sectional view showing a configuration of a transistor element group according to a seventh embodiment.

15A and 15B are a longitudinal sectional view and a plan view showing a transistor element of a seventh embodiment in an enlarged manner.

FIG. 16 is a vertical sectional view showing a transistor chip according to an eighth embodiment of the present invention in a partially enlarged manner.

17A and 17B are a longitudinal sectional view and a plan view showing a transistor chip according to a ninth embodiment of the present invention in a partially enlarged manner.

FIGS. 18A and 18B are an enlarged longitudinal sectional view and a plan view showing the vicinity of an input / output terminal bump electrode according to a tenth embodiment of the present invention.

FIG. 19 is an enlarged longitudinal sectional view and a plan view showing the vicinity of an input / output terminal bump electrode according to an eleventh embodiment of the present invention.

FIG. 20 is an enlarged longitudinal sectional view and a plan view showing the vicinity of an input / output terminal bump electrode according to a twelfth embodiment of the present invention.

FIG. 21 is an enlarged longitudinal sectional view and a plan view showing the vicinity of an input / output terminal bump electrode according to a thirteenth embodiment of the present invention.

FIG. 22 is a vertical sectional view and a plan view showing a semiconductor device according to a fourteenth embodiment of the present invention;

FIG. 23 is a series of longitudinal sectional views illustrating an example of a method for manufacturing a semiconductor device of a fourteenth embodiment.

FIG. 24 is a partial vertical cross-sectional view showing an example of bump heights before and after bonding and the amount of crushing of bump electrodes and the like due to bonding in the semiconductor device of the fourteenth embodiment.

FIG. 25 is a longitudinal sectional view showing a configuration of a dummy bump electrode according to a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 100 Semiconductor device 200 Interface resin 300 Wiring board 320 Wiring board wiring 330 Wiring board electrode part 340 Ground electrode 400 Semiconductor chip 500 Semiconductor chip base material 600 Transistor element 610 Semiconductor layer 611, 611C, 611B, 611E Mesa layer 612 Lower structure 620C, 620B, 620E Ohmic electrode 630 Intrinsic operating part 640 Intrinsic operating part proximity area 650 Non-intrinsic operating part 700 Chip wiring 720 Leading wiring 721 Leading electrode part 730 Air bridge 750 Upper layer wiring 800 Bump electrode 810 Element bump electrode 820 Input / output terminal bump electrode 831 , 832 Dummy bump electrode 910 Passivation film 920 Electrically insulating resin layer

Continuation of the front page (56) References JP-A-6-349846 (JP, A) JP-A-6-104275 (JP, A) JP-A-2-105420 (JP, A) , U) (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/60 H01L 21/331 H01L 29/73

Claims (8)

(57) [Claims] An element bump electrode, which is formed by sequentially laminating semiconductor layers on a main surface of a semi-insulating substrate, is insulated between each ohmic electrode by mesa etching, and is connected to at least one ohmic electrode. A semiconductor chip having a plurality of semiconductor elements provided in a single or parallel connection and having a plurality of input / output terminal bump electrodes connected to a chip wiring having a potential different from that of the element bump electrodes; It is provided between the lower part of the bump electrode and the semi-insulating substrate, and is made of the same material as the metal or the semiconductor layer. A semiconductor chip comprising a lower structure that is adjusted to have a height equal to or higher than a height. 2. A structure extending from the lower structure to the outside of the lower structure on the main surface of the semi-insulating substrate, below the input / output terminal bump electrode and above the lower structure of the input / output terminal bump electrode. The semiconductor chip according to claim 1, further comprising a chip wiring, wherein a thickness of the lower structure is smaller than a thickness of the chip wiring. 3. The lower structure is connected to the outside of the lower structure on the main surface of the semi-insulating substrate, below the input / output terminal bump electrode and above the lower structure of the input / output terminal bump electrode. 2. The semiconductor chip according to claim 1, further comprising a chip wiring, wherein an electric insulating resin layer is provided immediately below a portion where the chip wiring is drawn out from the lower structure. 4. The lower structure is connected to the outside of the lower structure on the main surface of the semi-insulating substrate below the input / output terminal bump electrode and above the lower structure of the input / output terminal bump electrode. The semiconductor chip according to claim 1, further comprising a chip wiring, wherein the lower structure is formed in a mesa shape. 5. A step of sequentially laminating a plurality of semiconductor layers as constituent elements of a semiconductor element on a main surface of a semi-insulating substrate, and forming an intrinsically operating portion of the semiconductor element and input / output terminal bumps. A step of etching most of the semiconductor layer excluding the input / output part by etching until reaching the semi-insulating substrate; and, on the intrinsic operation part including the periphery and the semiconductor layer of the input / output part,
Forming a bump electrode including each of an element bump electrode and an input / output terminal bump electrode. 6. A semiconductor device having a vertical structure in which semiconductor layers are sequentially stacked on a main surface of a semi-insulating substrate, and each ohmic electrode is insulated by mesa etching and connected to at least one ohmic electrode. In a semiconductor device having an element bump electrode, the element bump electrode does not exist directly above at least the intrinsic operation part of the semiconductor element, and at least a part of a non-intrinsic operation part existing around the intrinsic operation part. A lead wire formed to have a shape directly above and including an element bump electrode immediately above at least a part of the non-intrinsic operation part and an uppermost layer of a vertical structure of the intrinsic operation part; A semiconductor element characterized by the above-mentioned. 7. A semiconductor chip according to claim 1 or a plurality of semiconductor elements according to claim 6 connected in a single or in parallel and having a potential different from that of the element bump electrodes. A semiconductor device mounting a semiconductor chip including a plurality of input / output terminal bump electrodes connected to a chip wiring, comprising: a ground electrode at a position where the element bump electrode is to be joined; A wiring board provided with wiring electrodes at positions to be joined; and a semiconductor chip connected to the main surface of the wiring board via the element bump electrodes and the input / output terminal bump electrodes. Characteristic semiconductor device. 8. The semiconductor device according to claim 7, wherein a gap between the connected semiconductor chip and the wiring board is sealed with an electrically insulating resin material.