JPH06348466A - Digital signal processor - Google Patents

Abstract

PURPOSE:To provide a digital signal processor capable of drastically reducing the load of user's program development, reducing the load of a microcomputer, unnecessitating an external memory device, and drastically reducing total cost. CONSTITUTION:The digital signal processor is provided with a program ROM 30 for storing plural module programs for digital signal processing, the microcomputer 10 for outputting start address data corresponding to a necessary module program out of the plural module programs stored in the ROM 30, a module sequence RAM 23 for storing start address data, and a means for controlling the successive reading of module programs corresponding to the start address data stored in the RAM 23 from the ROM 30.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing device used in audio equipment, and more particularly to a sequence control circuit thereof.

[0002]

2. Description of the Related Art In recent years, many audio equipments perform signal processing by digital operation.
As such digital signal processing, for example, a sound field control processing for reproducing / simulating a concert hall sound field in a home audio device such as an AV amplifier or a mini component system, a professional audio device such as a studio adjusting console, or an in-vehicle audio device, Filtering processing such as equalizer, dynamic signal processing such as compressor / expander, professional logic surround decoder processing that can be said to be comprehensive signal processing of these, key control (pitch shift) processing and microphone echo processing often used for karaoke etc. It has been known. Further, these various digital signal processings are performed based on a signal processing program dedicated thereto.

Most of the signal processing performed by the various audio equipments is a program in which a plurality of the above-mentioned signal processing programs are combined. For example, a combination of sound field control processing + equalizer processing, compressor processing + sound field control processing, prologic surround decoder processing + sound field control processing + equalizer processing, key control processing + microphone echo processing + sound field control processing + equalizer processing There is.
Audio equipment such as an AV amplifier and a mini component system has a specification having a plurality of modes of signal processing in which a plurality of the above-mentioned combinations are performed.

FIG. 6 is a block diagram showing the configuration of a conventional digital signal processing device. In the figure, 81 is a control CPU, for example, a microcomputer (hereinafter referred to as a microcomputer), 82 is an external memory device including a mask ROM and a non-volatile memory (EPROM) storing various signal processing programs, Reference numeral 83 is the main body of the digital signal processing device.

A microcomputer interface circuit 84 for exchanging data with the microcomputer 81 and a multiplexer (hereinafter referred to as M
PX) 85, program counter (same PC) 86,
Incrementer (INC) 87, stack 88, program RAM 89, instruction register (IR) 9
0, instruction decoder (same ID) 91, condition determination circuit 92, signal processing circuit 93 and the like are provided.

In the apparatus having such a configuration, in order to execute the signal processing program, a necessary one is selected from a plurality of signal processing programs stored in the external memory device 82, and the digital signal is transmitted via the microcomputer 81. Processor body
The signal processing circuit is written in the program RAM 89 in the 83, after which the signal processing program is sequentially read from the program RAM 89, and the control signal is generated by the ID 91.
It is done by supplying to 93.

Writing of the signal processing program is performed in the following procedure. Microcomputer 81 is program RAM
The write address and program data are transmitted to the digital signal processor main body 83 as microcomputer transmission data 94. The microcomputer interface circuit 84 which receives the transmission data 94 sends the program RAM address 95 to the MPX 85.
And a write address selection signal 96, and program RA
Give the program data 97 to M89. MPX85 which received write address selection signal 96 is program RAM89
A program RAM address 95 is applied to the program RAM 97, and the program data 97 is written at the address designated by the program RAM address 95. After that, the microcomputer 81 repeats this procedure until all necessary programs are written in the program RAM 89.

The signal processing program is executed in the following procedure. The program counter output 98 of the PC 86 which has been cleared in advance is given to the program RAM 89 via the MPX 85, and the RAM output 99 of the address designated by this is given to the ID 91 as instruction data 100 via the IR 90. And ID91
Then, the control signal 101 is generated and given to the signal processing circuit 93.

On the other hand, the program counter output 98 output from the MPX85 is incremented by 1 at the INC87, and the PC is again output.
Given to 86. Then, after being read from the program RAM 89, the incremented program counter output 98 is M
It is given to the program RAM98 via the PX85, and the next address of the program RAM89 is designated by this, and the RAM output 99 passes through the IR90 and the ID91 in the same manner as above.
Given as instruction data 100 to the ID
At 91, the control signal 101 is generated and given to the signal processing circuit 93. The same procedure is followed from the RAM output 99 to the control signal 10
1s are sequentially generated and given to the signal processing circuit 93, and the signal processing circuit 93 performs digital signal processing.

On the other hand, if there is a branch instruction during program execution, the branch address 102 output from IR90 is MPX85.
Is given to the program RAM 89 via. At this time, the program counter output 98 immediately before the branch instruction is held in the stack 88 as a return address. afterwards,
As a result of the condition selection signal 103 being given to the condition judging circuit 92 from the ID 91 and the status data 104 being further given to the condition judging circuit 92, when the branch return conditions are satisfied, the branch return address selection signal 105 is given to the MPX85, and thereafter. , Return address held in stack 88 in advance
106 is given to the program RAM 89 via the MPX85, and returns to the original program before the branch.

In the above conventional apparatus, the signal processing program is switched by switching the new signal processing program to the microcomputer.
Program memory 89 from external memory device 82 via 81
It is done by rewriting to. For example, in order to perform the various signal processes described above, a program such as sound field control processing, equalizer processing, compressor processing, expander processing, pro-logic surround decoder processing, key control processing, microphone echo processing, etc. may be optionally stored in the program RAM 89. Must be written each time with a combination of.

Generally, a microcomputer has a built-in ROM, but does not have a capacity for writing all the signal processing programs. For this reason, the external memory device is prepared as described above, all the necessary signal processing programs are written therein, and when necessary, this is selectively read and written in the program RAM.

[0013]

As described above, in the conventional digital signal processing apparatus, it is necessary to develop a microcomputer control program for writing a necessary signal processing program in the program RAM each time, which is a burden on the user for program development. Not only does this increase the load on the microcomputer, but also the load on the microcomputer becomes very large, and an external memory device for storing the signal processing program is required, which disadvantageously reduces the total cost.

The present invention has been made in consideration of the above circumstances, and an object thereof is to significantly reduce the program development load of the user and the load of the microcomputer, and to external memory device. It is an object of the present invention to provide a digital signal processing device for an audio device which realizes a significant reduction in total cost by eliminating the requirement.

[0015]

A digital signal processing apparatus for audio equipment according to the present invention comprises a module program storage means for storing a plurality of module programs for digital signal processing, and a plurality of module program storage means stored in the module program storage means. Start address data output means for outputting start address data corresponding to a necessary module program among the module programs, data storage means capable of rewriting data for storing the start address data, and stored in the data storage means. The module program read control means for controlling the sequential reading of the module program corresponding to the start address data from the module program storage means.

[0016]

A plurality of module programs are stored in the module program storage means, start address data corresponding to a necessary module program among the plurality of module programs is output from the start address data output means, and these start address data are stored in the data. Are stored in a rewritable data storage means.
Then, the module program read control means sequentially reads the module programs corresponding to the start address data stored in the data storage means from the module program storage means, thereby executing the necessary module programs, thereby the user program The development burden can be significantly reduced.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram showing the configuration of a digital signal processing device according to the present invention. In the figure, 10 is a control CPU, for example, a microcomputer, and 20 is a digital signal processing apparatus main body.

In the digital signal processor main body 20, a microcomputer interface circuit 21, a multiplexer (MPX) 22, a module sequence RAM 23, a module sequence RAM counter (hereinafter referred to as MSRC) 24, a module address register (the same MAR) 25. ,
Multiplexer (MPX) 26, program counter (P
C) 27, incrementer (INC) 28, stack 29, program ROM 30, instruction register (I
R) 31, instruction decoder (ID) 32, condition determination circuit 33, signal processing circuit 34 and the like are provided.

The program ROM 30 contains all the signal processing programs which are considered necessary such as the pro-logic surround decoder processing, sound field control processing, equalizer processing, compressor processing, expander processing, key control processing and microphone echo processing. It is stored in advance as ROM data. An example of data storage in the program ROM 30 is shown in FIG. That is, a sequence return instruction is stored at the first address 0, a program module for sound field control processing is provided at addresses 1 to n, and an equalizer processing program is provided at addresses (m + 1) to p. Each module is stored, and program modules for the compressor process, expander process, key control process, microphone echo process, etc., which are not shown, are sequentially stored at subsequent addresses.

Further, as shown in FIG. 3, return instructions are described as control codes at the end addresses of the various program modules. Next, the operation of the apparatus configured as described above will be described. As described above, in actual digital signal processing, it is necessary to execute a program in which a plurality of various signal processing programs (program modules) are combined. Therefore, here, as one specification, consider a case where signal processing is performed by combining module programs in the order of pro-logic surround decoder processing, sound field control processing, equalizer processing, and compressor processing.

First, the microcomputer 10 sets the transmission data 35 as
The first module sequence RAM write address and the write module address data, which is the start address of the pro-logic surround decoder processing program module stored in advance in the program ROM 30, are transmitted to the digital signal processor main body 20. Microcomputer interface circuit 21 that received this transmission data 35
Gives the module sequence RAM write address 36 and write address selection signal 37 of address 0 to MPX22,
In the module sequence RAM 23, write module address data of address 0 which is the start address of the pro logic surround decoder processing program module
Give 38. The MPX 22 receiving the write address selection signal 37 outputs the module sequence R as the MPX output 39.
The module sequence RAM write address is given to AM23. Therefore, in this case, as shown in FIG. 4, the start address data of the pro-logic surround decoder processing program module is stored at address 0 of the module sequence RAM 23.

Next, the microcomputer 10 uses, as the transmission data 35, the following module sequence RAM write address and write module address data which is the start address of the sound field control processing program module stored in the program ROM 30 in advance. Send to the main body 20. The microcomputer interface circuit 21 which has received the transmission data 35 gives the module sequence RAM write address 36 and the write address selection signal 37 at the first address to the MPX 22 to send the module sequence RAM.
Write module address data 38 at address (n + 1) is given to 23. Therefore, in this case, as shown in FIG. 4, the start address data of the sound field control processing program module is stored in the address 1 of the module sequence RAM 23. Thereafter, by the same procedure, as shown in FIG. 4, the start address data of the equalizer processing program module is stored in the address 2 of the module sequence RAM 23.

Next, data reading from the module sequence RAM 23 is started. The contents of each of the MSRC 24 and the PC 27 are cleared to 0 in advance in synchronization with the start edge of the system synchronization signal (not shown). The program counter output 40 of the PC 27 in the cleared state is given to the program ROM 30 via the MPX 26, and thereby address 0 of the program ROM 30 is addressed. As shown in FIG. 2, a return instruction is described in advance at this address 0. The ROM output 41 as a return instruction read from the program ROM 30 by the above address designation is given to the ID 32 as instruction data 42 via the IR 31. And this instruction data 41 with ID 32
The module address selection signal 43 is output by decoding the (return instruction), and the MPX 26 selects the output of the MAR 25 by inputting this signal 43.

On the other hand, after writing the data to the module sequence RAM 23, the MSR which has been cleared in advance is
The output 44 of C24 is provided as an MPX output 39 to the module sequence RAM 23 via MPX22. At this time,
The module sequence RAM 23 is set to the data read mode by a control signal (not shown), which addresses the 0 address of the module sequence RAM 23, and the start address data of the pro-logic surround decoder processing program module stored in advance at this address. It is read out and is temporarily held in the MAR 25 as the module sequence RAM output 45.

Therefore, when the output of the MAR 25 is selected by the MPX 26, this is given to the program ROM 30,
This addresses address 1 in program ROM 30. As shown in FIG. 4, the pro-logic surround decoder processing program module is stored in advance at this address, and then the first step of this program module is read out as the ROM output 41, and the ID 32 is passed via the IR 31. Is given as instruction data 42 to the. Then, by decoding the instruction data 41 with the ID 32, the control signal 46 for realizing the pro-logic surround decoder processing is generated and given to the signal processing circuit 34.

On the other hand, the output from the MAR 25 output from the MPX 26 is incremented by 1 in the INC 28 and given to the PC 27. Then, after reading from the program ROM 30, the incremented program counter output 40 is given to the program ROM 30 via the MPX 26, whereby the next address of the program ROM 30 is designated, and thereafter, the control signal 46 is given by the ID 32 as in the above. It is generated and given to the signal processing circuit 34. Thereafter, the control signal 46 is sequentially generated from the ROM output 41 and given to the signal processing circuit 34 in the same procedure, and the signal processing circuit 34 sequentially performs the pro-logic surround decoder processing.

On the other hand, if there is a branch instruction during execution of the program, the branch address 47 output from the IR 31 is given to the program ROM 30 via the MPX 26. At this time,
The contents of the program counter immediately before the branch instruction are stacked
It is held in 29 as a return address. Then ID
As a result of the condition selection signal 48 being given to the condition judging circuit 33 from 32 and the status data 49 being given to the condition judging circuit 33, if the branch return conditions are satisfied, the branch return address selection signal 50 is given to the MPX 26 in advance. The return address 51 held in the stack 29 is the program ROM
It is given to 30 and returns to the program execution before the original branch.

On the other hand, the contents of the MSRC 24 are incremented by 1 during execution of this prologic surround decoder processing program, and the MAR 25 holds the start address of the sound field control processing program module stored in the address 1 of the module sequence RAM 23. .

Then, the execution of the pro-logic surround decoder processing program module proceeds, and the data from the end address is read. Since this data is a return instruction as shown in FIG. 3, the module address selection signal 43 is output again from the ID 32, and the MPX 26 selects the output of the MAR 25 when this signal 43 is input. At this time, the address output from the MAR 25 is address 2, and the sound field control processing program module is stored in the area starting from this address in advance. The first step of this program module is RO.
It is read out as M output 41, and thereafter, the sound field control processing program module is executed in the same manner as in the case of executing the above-mentioned pro logic surround decoder processing program module. After execution of this sound field control processing program module, the next equalizer processing program module is executed in the same manner as described above. In this way, a plurality of signal processings are continuously performed by the combination stored in the module sequence RAM 23.

As described above, in this embodiment, the combination of a plurality of programs can be easily executed by writing the start addresses of the combined processing program modules into the module sequence RAM 23 in the order of processing from 0. You can That is, only by rewriting the data in the module sequence RAM 23, a program in which a plurality of various signal processing programs (module programs) are combined can be easily executed in a plurality of modes without adding a program or an external circuit. Moreover, an external memory device for storing the signal processing program is unnecessary, which is advantageous in terms of total cost.

Further, by incorporating a plurality of standard module programs in the program ROM 30, it is possible to obtain an excellent effect that the user's program development load can be significantly reduced. Also, without changing the circuit board (hardware) in which the device of the above embodiment is incorporated,
The user's specifications can be easily changed only by changing the address data write program to the module sequence RAM 23.

Next, a specific configuration example of the signal processing circuit 34 will be described. As shown in FIG. 5, the signal processing circuit 34 includes
A serial-in register (hereinafter referred to as SI) 61 to which input voice data for being digitized in advance and subjected to the various digital signal processes is supplied, a serial out for outputting voice data after subjected to the various digital signal processes A register (hereinafter referred to as SO) 62, a data RAM 63 for temporarily storing data, a coefficient RAM 64 for storing coefficient data, an adder 65 for executing addition of data, and various calculations. Multiplier (same MPY) 66, X, Y registers (same X, Y) for temporarily storing both data calculated by the MPY66
67, 68, an accumulator (same ACC) 69 for temporarily storing the output of the MPY 66, an internal bus 70, etc. are provided.

In the signal processing circuit 34 having such a configuration, the audio data input via the SI 61 is subjected to the above-mentioned various signal processing by being subjected to addition and various operations in the adder 65 and the MPY 66, and 1 The audio data subjected to the one signal processing is temporarily stored in the data RAM 63, and then subjected to another signal processing as necessary, and finally SO62.
Is output via. The control signal 46 generated by the ID 32 controls the operation of each part in FIG.

[0034]

As described above, according to the present invention,
It is possible to provide a digital signal processing device for an audio device, which can significantly reduce the user's program development load and the load on the microcomputer, and also realizes a significant reduction in total cost by eliminating the need for an external memory device. it can.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a digital signal processing device according to the present invention.

FIG. 2 is a diagram showing a data storage state of a program ROM in FIG.

FIG. 3 is a diagram showing a configuration example of each program module stored in a program ROM.

FIG. 4 is a diagram showing a data storage state of a program sequence RAM in FIG.

5 is a block diagram showing a specific configuration example of a signal processing circuit in FIG.

FIG. 6 is a block diagram showing a configuration of a conventional digital signal processing device.

[Explanation of symbols]

10 ... Microcomputer, 20 ... Digital signal processor main body, 21 ...
Microcomputer interface circuit, 22 ... MPX (multiplexer), 23 ... Module sequence RAM, 24 ... MS
RC (Module Sequence RAM Counter), 25 ... M
AR (module address register), 26 ... MPX (multiplexer), 27 ... PC (program counter), 28
... INC (incrementer), 29 ... Stack, 30 ... Program ROM, 31 ... IR (instruction register), 32 ... ID (instruction decoder), 33 ...
Condition determination circuit, 34 ... Signal processing circuit.

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[Procedure amendment]

[Submission date] July 14, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Title of invention

[Correction method] Change

[Correction content]

Title: Digital signal processing device

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be amended] Claims

[Correction method] Change

[Correction content]

[Claims]

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0001

[Correction method] Change

[Correction content]

[0001]

BACKGROUND OF THE INVENTION This invention relates to de Ijitaru signal processing device, in particular to the sequence control circuit.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0014

[Correction method] Change

[Correction content]

The present invention has been made in consideration of the above circumstances, and an object thereof is to significantly reduce the program development load of the user and the load of the microcomputer, and to external memory device. It was unnecessary to provide a Lud Ijitaru signal processing apparatus to realize a significant reduction in total cost.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Name of item to be corrected] 0015

[Correction method] Change

[Correction content]

[0015]

Means for Solving the Problems] de Ijitaru signal processing apparatus of the invention comprises a module program storage means for storing a plurality of module program for digital signal processing, a plurality of modules program stored in the module program storage means A start address data output means for outputting start address data corresponding to a required module program, a data storage means capable of rewriting data for storing the start address data, and a start stored in the data storage means. And a module program read control means for controlling the sequential reading of the module program corresponding to the address data from the module program storage means.

[Procedure correction 6]

[Document name to be amended] Statement

[Correction target item name] 0034

[Correction method] Change

[Correction content]

[0034]

As described above, according to the present invention,
The user's program development load can be greatly reduced, the load on the microcomputer can be reduced, and the external memory device is not required, resulting in a significant reduction in total cost.
It is possible to provide a Lud Ijitaru signal processor.

Claims (3)

[Claims] 1. A module program storage means for storing a plurality of module programs for digital signal processing, and start address data corresponding to a necessary module program among the plurality of module programs stored in the module program storage means. Start address data output means, data storage means capable of rewriting data for storing the start address data, and a module program corresponding to the start address data stored in the data storage means from the module program storage means. A digital signal processing device for audio equipment, comprising: a module program read control means for performing sequential read control. 2. A module program storage means for storing a plurality of module programs for digital signal processing, each of which has a return instruction written as a control code at a final address of the program, and a plurality of modules stored in the module program storage means. A start address data output means for outputting start address data corresponding to a necessary module program among programs, a data storage means capable of rewriting data for storing the start address data, and a data storage means stored in the data storage means. Start address data is supplied, addressing means for addressing the module program storage means from an address corresponding to the start address data, and addressing by the addressing means, Instruction code decoding means for decoding the instruction code read from the corresponding address of the module program storage means, and the head start address data stored in the data storage means to the address designating means, and When the control code decoded by the instruction code decoding means is the return instruction, there is provided means for controlling the supply of the next start address data stored in the data storage means to the address designating means. Signal processing equipment for audio equipment. 3. A module program storage means for storing a plurality of module programs for digital signal processing, and start address data corresponding to a necessary module program among the plurality of module programs stored in the module program storage means. Data storage means capable of rewriting data to be stored, and module program read control means for controlling to sequentially read the module program corresponding to the start address data stored in the data storage means from the module program storage means. A digital signal processing device for audio equipment, characterized in that