JPH06342910A - Thin-film semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the infiltration of impurities from a substrate, and to obtain desired characteristics by keeping the film thickness of a silicon thin-film within a specified range. CONSTITUTION:A semiconductor on an insulating substrate 1 such as alumina, sapphire, spinel, etc., is grown in an epitaxial manner in thickness of 0.01-2mum, and a source 5, a drain 6, a buried field insulator 3, a semiconductor direct contact 7, a self-alignment gate electrode 11, a gate insulating film 12, and a CVDSiO2 film 10 are formed. When the film thickness of a silicon thin-film is formed in thickness of 0.01-0.37mum, hydrogenation treatment is conducted under the state, in which a semiconductor device is completed or completed approximately. Accordingly, the density of the recombination center of an incomplete semiconductor layer is reduced even in the incomplete semiconductor layer 9, in which there are a large number of unpaired bonds in the semiconductor, and the layer 9 can be treated in the same manner as a single crystal. The hydrogenation treatment has an effect neutralizing the unpaired bonds existing in the semiconductor substrate and the gate insulating film 12, thus easily manufacturing a MIS-FET.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film semiconductor device having a non-single crystal semiconductor in at least a part of a semiconductor device. According to the present invention, at least a part of a channel region under a gate insulator of a thin film type insulated gate field effect transistor (MIS-FET) is composed of an amorphous or polycrystalline so-called non-single-crystal semiconductor, and , Hydrogen gas or halogen element such as chlorine is mixed with 0.1 mol% (atomic%) or more. The present invention also relates to a thin film semiconductor device in which the recombination centers due to dangling bonds or the like are neutralized and eliminated in this non-single crystal region.

The present invention relates to a thin film semiconductor device capable of making the mobility of electrons or holes equal or approximately equal to that in the case of a single crystal known so far. The present invention has a P or N type conductivity and has an impurity concentration of 2 × 10 ¹⁹ cm ⁻³ or less, particularly 10 ¹⁴ or less.
for non-single-crystal semiconductor in cm ^-3 to 10 ¹⁷ cm ^-3, the semiconductor formation and simultaneously or after formation, after you've particularly complete a semiconductor device, (including deuterium) hydrogen as a gas or chlorine The present invention relates to a thin film semiconductor device to which a halogen element is added.

[0003]

2. Description of the Related Art Conventionally, a semiconductor device has a thin film type insulated gate field effect transistor (MIS-FET) or a bipolar type transistor for a single crystal semiconductor substrate, or a capacitor, a resistor, It has been limited to manufacturing a device in which a diode or the like is compounded and integrated on the same substrate. For this reason, the active-element thin-film insulated gate field effect transistor (MIS-FET) is used.
Alternatively, the bipolar transistor is always provided on the single crystal substrate. In particular, in the thin film type insulated gate field effect transistor (MIS-FET), the carrier lifetime is slightly affected in the channel formation region below the gate, and in the bipolar type transistor, the base and collector regions. I'm giving. Therefore, in these regions, a single crystal semiconductor having a concentration in which a recombination center for an electron or a hole which is a carrier is sufficiently small is used.
Further, in the PN junctions of these transistors, the soft breakdown or the increase in the leak in the reverse breakdown voltage was mainly caused by the lattice defects and other lattice defects, and the recombination centers due to dangling bonds.

[0004]

A thin film type insulated gate field effect transistor formed on a single crystal substrate has the advantage of high electron or hole mobility as described above, but is expensive in manufacturing. Had the drawback. However, when a thin-film insulated gate field effect transistor made of a non-single crystal semiconductor is integrated, even if the thickness of the semiconductor film can be reduced, it has not been a practical integrated circuit. For example, in a thin film type insulated gate field effect transistor in which the thickness of the semiconductor film is 0.01 μm to 0.3 μm, impurities penetrated from the substrate and desired characteristics could not be obtained.

An object of the present invention is to solve the above problems, and an object thereof is to provide a thin film semiconductor device capable of promoting thinning of a non-single crystal semiconductor.
Another object of the present invention is to provide a thin film semiconductor device to which a gas degassed during fabrication is added. Further, the present invention is to add a halogen element such as hydrogen gas or chlorine in a chemically active or atomic state to a semiconductor device completed or mostly completed as a device which has undergone all or most of heat treatment steps. Is characterized by. In the present invention, by such addition, the element in the active state is bound to a dangling bond in a semiconductor, particularly a non-single crystal semiconductor, and further or dangling bonds are covalently bonded to each other to electrically neutralize. It has a feature.

[0006]

[Means for Solving the Problems]

(First Invention) In order to achieve the above object, a thin film semiconductor device of the present invention comprises a silicon thin film, a source, a drain, and a gate electrode on a gate insulating film on a substrate having an insulating surface. The film thickness of the silicon thin film is 0.01 μm to 0.3 μm.

(Second Invention) The thin film semiconductor device of the present invention is
It is characterized in that it is made of a polycrystalline semiconductor by adding hydrogen or a halogen element to a silicon thin film.

[0008]

[Work]

(First Invention) A thin film transistor having a silicon thin film, a source, a drain, and a gate electrode on a gate insulating film is formed on a substrate having an insulating surface. Although the thickness of the silicon thin film in the above thin film transistor is 0.01 μm to 0.3 μm, desired characteristics as a thin film transistor can be obtained without impurities entering from the substrate.

(Second Invention) Since the silicon thin film is made of a polycrystalline semiconductor to which hydrogen or a halogen element is added,
Even in the non-single-crystal region, the density of recombination centers due to dangling bonds can be lowered, and impurities are less likely to enter from the substrate. Therefore, the thin film semiconductor device of the present invention can obtain desired characteristics even as an integrated circuit.

[0010]

EXAMPLE An example of the present invention will be described below. FIG. 1A is a vertical cross-sectional view for explaining a thin film type insulated gate field effect transistor. In this example,
An insulating film (2) of silicon oxide or silicon nitride having a thickness of 200 Å to 2 μm is formed on a silicon semiconductor substrate (1). Then, oxygen or nitrogen is implanted into the silicon semiconductor substrate (1) from the surface thereof by an ion implantation method of 150 KeV to 300 KeV. Then, the silicon semiconductor substrate (1) is annealed at 900 ° C. to 1100 ° C. for 10 to 30 minutes in a vacuum state or a hydrogen atmosphere. Further, a silicon film is formed on the upper surface by the reduced pressure vapor phase method. This is silane (SiH ₄ ), dichlorosilane (SiH ₂ Cl ₂ ), and other silicides as reactive gases.
500 ℃ on the condition of 1 torr to 10 torr (mmHg)
Or by the so-called reduced pressure gas phase method carried out at a temperature of 900 ° C. For heat generation, an induction heating method using a high frequency of 1 MHz to 10 MHz is used. However, the heat generation may be resistance heating.
The formation of a semiconductor film by the reduced pressure vapor phase method is described in Japanese Patent Publication No. 51-138.
It is based on the technology described in Publication No. 9. of course,
The glow discharge method or the sputtering method may be used at a temperature of room temperature to 500 ° C.

Thus, a silicon semiconductor film having a thickness of 0.1 μm to 2 μm is formed on the upper surface of the insulating film (2). This semiconductor film is made of pure SiO ₂ whose insulating film (2) is
Alternatively, Si ₃ N ₄ has a polycrystalline structure. However, the insulating layer in which the amount of oxygen or nitrogen is 10 ¹⁸ cm ^-3 to 10 ²¹ cm ^-3 has an epitaxial structure including a part of non-single crystal. In this embodiment, the recombination centers of the semiconductor film having such a high density of recombination centers are removed by induced electric energy. The field insulator (3) is formed based on the patents (Japanese Patent Publication No. 52-20312 and Japanese Patent Publication No. 50-37500) proposed by the present applicant so as to have a thickness of 1 μm to 2 μm. After this, the gate insulating film (12) is 100 Å or
It is made to a thickness of 1000Å, and silicon semiconductor contacts (7) are formed if necessary. Also, the gate insulation film
(12) is a gate electrode on top of it by self-alignment method
(11) is made of a semiconductor film by the low pressure CVD method.

In addition, the SiO ₂ film overcoat (10) is
It is formed to a thickness of 0.5 μm to 2 μm. At this time, a polyimide resin (PIQ) or the like may be used instead of the SiO ₂ film in order to make the upper surface a flat surface. Drilling holes in aluminum electrodes, and aluminum electrodes and leads
It is formed on the SiO ₂ overcoat film. Source (5),
Drain (6), a channel formation region (4) is N ⁺ type impurity to 10 ²¹ cm ^-3 10 ¹⁸ cm ^-3 is not a P-type, for example phosphorus, is formed by arsenic. The gate electrode (11) is
A metal such as molybdenum or tungsten may be used.
The impurities may be mixed with phosphorus or the like at a concentration of 10 ¹⁹ cm ^-3 or more to form a low resistance semiconductor lead. When the impurities in the semiconductor of the gate electrode (11) are mixed in a large amount of 10 ¹⁹ cm ^-3 or more, particularly 10 ²¹ cm ^-3 , the effect of neutralization by hydrogenation of this example is not observed. It was On the other hand, the channel region (4) has an impurity concentration of 10 ¹⁴ cm ⁻³ to 10 ¹⁷
It has a low concentration of cm ⁻³ and is extremely sensitive to the effect of hydrogen addition.

It is known that electron or hole carriers generally have structure sensitivity in a single crystal.
However, the Applicant has discovered that such structure sensitivity is not due to the crystal structure, but to the reaction of recombination centers present therein. As a result, the present example is intended to neutralize and eliminate the recombination centers that give the above-mentioned sensitivity. Therefore, in this embodiment, 0.1 mol% of hydrogen is added here. As a result, after the structure of FIG. 1A was completed, the carrier lifetime was increased by 10 ³ to 10 ⁵ times by the addition of hydrogen. Even the CV diode showed almost the theoretical CV characteristic of the order of Qss≈10 ¹⁰ cm ^-2 . Addition of a halogen element such as hydrogen gas or chlorine heats the substrate to 300 ° C. to 500 ° C. by a resistance heating furnace, and thereafter, the induction furnace is voltage-excited. When the current is excited, only the metal wall or the metallic portion of the substrate is locally heated, which is not preferable. Therefore, activation of the reaction furnace gas is performed by voltage excitation. Further, at a temperature of 300 ° C. or higher, hydrogen atoms can move freely in this solid due to interstitial atoms. Therefore, these atoms can be added to the semiconductor to a sufficient equilibrium concentration.

After this, the temperature was lowered to room temperature. The upper limit of the heating temperature was 500 ° C when there was a material such as aluminum that could be alloyed or melted at a relatively low temperature, but in other cases, a higher temperature (600 ° C to 1000 ° C) was used.
℃). The method of this embodiment is shown in FIG.
Although the semiconductor device as shown in (B) was tested, the amount of the excitation gas added was quantified by mixing the gas into the semiconductor, heating the substrate in vacuum, and releasing the gas. So called gas chromatograph or
It was quantified by J. J. spectroscopy. In that case, the hydrogen atom is 0.1 mol%, especially 1 mol% or
It was found that 20 mol% was added.

In the following examples of the present invention, induction curing was performed by the same method as described above. FIG. 1B shows an embodiment of silicon-on-sapphire (SOS). A semiconductor on an insulating substrate (1) such as alumina, sapphire, or spinel is epitaxially grown to a thickness of 0.01 μm to 2 μm, and further, a source (5), a drain (6) and a buried field insulator ( 3), semiconductor direct contact (7), self-aligned gate electrode (11),
This is an example of the gate insulating film (12) and the CVD SiO ₂ film (10). In this case, the alumina component of the insulating substrate and the semiconductor are bonded at the portion (9), and a non-single crystal state is exhibited. For this reason,
The formation of the source (5) and the drain (6) causes abnormal diffusion.

Therefore, until now, even if the thickness of this semiconductor film could be made 0.01 μm to 0.3 μm, it has not been practically useful. However, even if the semiconductor film has a thickness of 0.01 μm to 0.3 μm as in the present embodiment, if the hydrogenation treatment is performed in the state where the semiconductor device is completed or almost completed, the impurities in the semiconductor will be lost. Even in the imperfect semiconductor layer (9), which has many pairs of bonds, the density of recombination centers can be reduced to 1/100 to 1/10000, and it can be handled in the same way as the single crystals known so far. become. This hydrogenation treatment has a remarkable effect of neutralizing the interface state existing between the semiconductor substrate (1) and the gate insulating film (12) or the dangling bonds existing in the gate insulating film (12). This is a very preferable method for improving the manufacturing method of a thin film insulated gate field effect transistor (MIS-FET).

FIG. 2 shows another embodiment of the present invention. 2A and 2B show a second thin film type insulated gate field effect transistor (MIS-FET) with respect to the upper or upper surface of one thin film type insulated gate field effect transistor (MIS-FET). MIS-FET). In addition, this embodiment is intended to manufacture an integrated circuit (LSI, VLSI) having a density which is 2 to 4 times higher than that in the past. A description will be given below with reference to the drawings. In FIG. 2 (A), an insulating film (13) such as silicon oxide is formed on the silicon semiconductor substrate (1).
It is formed to a thickness of 0.1 μm to 2 μm. In this case, the substrate does not necessarily have to be a semiconductor. It may be an insulator as long as it satisfies the conditions such as subsequent heat treatment, practical heat conduction, and processing. Here, polycrystalline silicon is used. The insulating film (13) is formed by oxidizing the silicon semiconductor substrate (1).

Further, a non-single crystal semiconductor silicon film having a thickness of 0.01 μm to 0.3 μm was formed on this upper surface by using the low pressure CVD method. It is a P type and has an impurity concentration of 10 ¹⁸ cm ⁻³ to 10 ¹⁶ cm ⁻³ , and a field insulator is formed by a selective oxidation method using this semiconductor film as a mask of a double film of silicon nitride and silicon oxide. (3) is formed by being embedded in the semiconductor layer. At this time, the field insulator (3) and the semiconductor layer may be etched so that the field insulator (3) and the semiconductor layer are substantially flush with each other. It may be removed. Further, the gate insulating film (12) is 100 Å to 10
It is formed with a thickness of 00Å. The gate insulating film (12) is a thermal oxide film formed by oxidizing the semiconductor layer. Further, it may have a double structure of a thermal silicon oxide insulating film and phosphor glass, alumina, or silicon nitride, or may be a non-volatile memory in which a cluster or a film is formed of a semiconductor or a metal in this gate insulator.

After that, the second semiconductor layer (1
1), source (25), channel forming region (29), drain (2
4) is formed to a thickness of 0.1 μm to 2 μm, and selectively removes unpaired bonds. In FIG. 2A, the one thin film type insulated gate field effect transistor has a gate electrode (11) and the source (25) of another second thin film type insulated gate field effect transistor. ), A drain (24), and a channel formation region (29). Using the gate electrode (11) as a mask, the source (5) and the drain (6) of the first thin film type insulated gate field effect transistor are formed by the ion implantation method. Of course, a thermal diffusion method may be used. Further, as is apparent from FIG. 2A, the gate electrode 11 is connected to the second thin film type source 25 through the field insulator 3 not shown. There is. The second thin film type insulated gate field effect transistor has a structure in which after the third semiconductor layer (21) is formed, the gate electrode (21) and the gate insulator (2) below it are formed.
By 2), the source (25) and the drain (24) are diffused by using the ion implantation method or the thermal diffusion method. This Figure 2
In (A), a second thin film type insulated gate field effect transistor is provided obliquely above the first thin film type insulated gate field effect transistor. However, the layout, size, and wiring of each thin-film type insulated gate field effect transistor are made according to free design considerations.

Further, as shown in FIG. 2B, a resistor and a capacitor may be simultaneously formed on the same substrate, and a diode such as a protection diode may be formed. In FIG. 2B, a field insulator (3) is formed on the silicon semiconductor substrate (1) by selective oxidation to a thickness of 0.5 μm to 2 μm.
In addition, the gate electrodes (11) and (11 ') of semiconductor etc. are provided, and the source (5), drain (6), source (6) and drain (5) are connected.
Boron or phosphorus is mixed at a concentration of 10 ¹⁹ cm ^-3 to 10 ²¹ cm ^-3 to form a P channel or N channel thin film type insulated gate field effect transistor. The impurity region is the drain (6) of one thin film type insulated gate field effect transistor, and the inverter region is used as the source (5) of the other thin film type insulated gate field effect transistor. Here is an example. Further, an insulating film (10) for overcoat is formed on the upper surface of 0.5 μm to 2 μm.
It is formed to a thickness of μm. When the upper surface of the overcoat insulating film (10) is a flat surface, fine processing can be performed on the third thin film type insulated gate field effect transistor formed on the upper side.

Then, a 0.2% non-single crystal semiconductor is formed on the upper surface.
It is formed to a thickness of μm to 2 μm. The impurity concentration is 10 ¹⁴ cm ^-3 to 10 ¹⁶ cm ^-3, which is P-type, and is conditioned that the channel forming region (29) functions sufficiently as a channel in an operating state. Further, the non-single crystal resistor is connected to the source of the third thin film type insulated gate field effect transistor by the photomask and is connected to the lead (38).
The drain (37) is connected to the lower electrode (34) of the capacitor. The gate insulating film on the upper surface is the dielectric of the capacitor and the gate insulator of the third thin film type insulated gate field effect transistor. The gate electrode (2
1) and the upper electrode (36) of the capacitor is formed. In this embodiment, these are aluminum metals.

The substrate electrode of the third thin film type insulated gate field effect transistor is connected to the gate electrode of the first thin film type insulated gate field effect transistor so that the substrate bias is applied. The gate electrode (11) can control the channel states of the two thin film type insulated gate field effect transistors substantially. Of course, if a gate insulator is formed between the channel forming region (29) and the gate electrode (11), the third
The thin film type insulated gate field effect transistor is a double gate thin film type insulated gate field effect transistor having gate electrodes on the lower side and the upper side. Of course, the upper gate electrode may be removed. In addition, not only leads but also active elements such as thin film type insulated gate field effect transistors, resistors, capacitors and diodes can be provided on the same substrate. In addition, if a plurality of these elements are integrated, it is possible to use the two or
It is possible to have a density of 10 times.

In this embodiment, of course, this FIG.
In (B), adding hydrogen again to the non-single crystal semiconductor layer that has been degassed by thermal oxidation completes these devices or completes them in large part, as already detailed in FIG. After that, not only the recombination center in the single crystal semiconductor is removed by performing, but also the semiconductor or insulating object having a polycrystalline or amorphous characteristic, or the interface state existing at the interface between the semiconductor and the insulating object, Offset with an inert gas or neutralize with hydrogen or the like. In the above description, it is preferable that after the semiconductor devices of FIGS. 1 and 2 are cured, silicon nitride is formed by the plasma method and the overcoat (40) is performed. Because silicon nitride is
This is because it also has a masking effect on atoms such as hydrogen helium, which has the effect of sealing hydrogen once added to the semiconductor device and preventing it from going out. Therefore, the effect of improving the reliability is remarkable in addition to the prevention of sodium contamination from the outside.

This embodiment makes it possible to sufficiently reduce the density of recombination centers, which is the root cause of these, even in non-single-crystal (polycrystal or amorphous) which is not a single crystal, and as a result, was completed for the first time. . In this embodiment, the semiconductor material has been mainly described as a silicon semiconductor. However, this is also the case with semiconductors such as germanium. In addition, the semiconductor device is not limited to a thin film type insulated gate field effect transistor, but may be a bipolar transistor or an IC or LSI such as an IIL or SIT in which they are integrated. , Effective for all semiconductor devices.

[0025]

According to the present invention, the thickness of the silicon thin film in the thin film semiconductor device is 0.01 μm to 0.3 μm.
Despite the thinness, there was no invasion of impurities from the substrate, and those having desired characteristics were obtained. Also,
By adding hydrogen or a halogen element to the silicon thin film, recombination centers due to dangling bonds in the non-single crystal semiconductor can be neutralized. Therefore, the mobility of electrons or holes in the thin film semiconductor device can be made substantially the same as that of the single crystal semiconductor.

[Brief description of drawings]

FIG. 1A is a vertical cross-sectional view for explaining a thin film type insulated gate field effect transistor. (B) is an example of silicon-on-sapphire (SOS).

2 (A) and 2 (B) show a second thin film type insulated gate field effect transistor (MIS-FET) with respect to the upper or upper surface of one thin film type insulated gate field effect transistor (MIS-FET). MIS-FET).

[Explanation of symbols]

 1 ... Silicon semiconductor substrate 2 ... Insulating film 3 ... Field insulator 4 ... Channel formation region 5 ... Source 6 ... Drain 7 ... Contact 8 ... Drilling 10 ... -Overcoat 11 ... Gate electrode 12 ... Gate insulating film 13 ... Insulating film 21 ... Third semiconductor layer (gate electrode) 22 ... Gate insulator 24 ... Drain 25 ...・ Source 29 ・ ・ ・ Channel forming region 34 ・ ・ ・ Lower electrode 36 ・ ・ ・ Upper electrode 37 ・ ・ ・ Drain 38 ・ ・ ・ Lead 40 ・ ・ ・ Overcoat

Claims (2)

[Claims] 1. A thin film transistor comprising a silicon thin film, a source, a drain, and a gate electrode on a gate insulating film on a substrate having an insulating surface, wherein the silicon thin film has a thickness of 0.01 μm to 0.3 μm.
A thin film semiconductor device having a thickness of μm. 2. A thin film semiconductor device according to claim 1, wherein the silicon thin film is made of a polycrystalline semiconductor to which hydrogen or a halogen element is added.