JPH0357613B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an insulated gate field effect semiconductor device (hereinafter referred to as MIS-FET),
The second MIS-FET is intended to be provided above or on the upper surface of the first MIS-FET provided on the substrate. The present invention relates to a semiconductor device having a non-single crystal semiconductor in at least a portion of the semiconductor device. The present invention provides that at least a part of a channel region under a gate insulator of an insulated gate field effect transistor (hereinafter referred to as MIS-FET) is made of an amorphous or polycrystalline non-single crystal semiconductor, and that Relates to mixing 0.1 mol% or more of hydrogen element. In this non-single crystal region, recombination centers due to dangling bonds and the like are neutralized and eliminated by the hydrogen. As a result, the mobility of electrons or holes is to be made equal or approximately equal to that of previously known single crystals. Traditionally, semiconductor devices were manufactured using single-crystal semiconductor substrates.
MIS-FET or bipolar transistor,
In addition, devices have only been produced in which capacitors, resistors, diodes, etc. are combined and integrated on the same substrate. For this reason, the active element MIS-
FETs were always mounted on single-crystal substrates. especially
In MIS-FETs, the channel region below the gate, and in bipolar transistors, the base and collector are subtly affected by the carrier lifetime, so the recombination center for carrier electrons or holes is sufficiently small in that region. Concentrated single crystal semiconductors were used. When a single crystal semiconductor is not used in such an active region, soft breakdown or increased leakage is observed in the reverse breakdown voltage even in the PN junction, and these are caused by lattice defects, other lattice misalignments, and recombination due to dangling bonds. The presence of the center was the main cause of the deterioration. The present invention makes it possible to sufficiently reduce the density of recombination centers, which is the root cause of these problems, even in non-single crystals (polycrystals or amorphous), and has been completed for the first time as a result. Generally, when forming a semiconductor device using single crystal silicon, heat treatment at various temperatures is required. For example, in silicon semiconductors
Thermal diffusion of impurities at 900-1200℃, alloying of aluminum contacts at 400-550℃,
The film is fabricated using a vapor phase method (low-pressure CVD) of silicon oxide, silicon nitride, and silicon at 350 to 900°C.
The present invention is characterized in that hydrogen is added in a chemically active or atomic state to a semiconductor device that has undergone all or most of these heat treatment steps and has been completed or mostly completed. In the present invention, such additive action is also collectively referred to as induction curing. In particular, hydrogen (including deuterium) is induced to be excited by high frequency energy or microwave energy to be brought into a chemically active state.
By exposing the semiconductor device to this atmosphere, especially an atmosphere with a pressure of 10 ^-2 mmHg or more for 5 minutes to 2 hours, the elements in the active state combine with the dangling bonds in the semiconductor, especially in the non-single crystal semiconductor, and further It is also characterized by covalently bonding unpaired bonds to each other and electrically neutralizing them. The present invention will be explained below with reference to Examples. FIG. 1 is a longitudinal sectional view of an MIS type field effect semiconductor according to the present invention. In this invention, a 200 Å film is formed on a silicon semiconductor substrate 1.
~2μ thick silicon oxide or silicon nitride thin film 2
was formed. This was accomplished by implanting oxygen or nitrogen into the semiconductor substrate from the surface using ion implantation at 150 to 300 KeV. This is heated at 900 to 1100℃ for 10 to 10 minutes in a vacuum or hydrogen atmosphere.
Annealing was performed for 30 minutes. Further, a silicon film was formed on the upper surface by a reduced pressure vapor phase method. This uses silane (SiH ₄ ), dichlorosilane (SiH ₂ Cl ₂ ), and other silicides as reactive gases at 0.1 to 10 torr (mmHg).
The so-called reduced pressure gas phase method was used, which was carried out at a pressure of 500 to 900°C. High frequency induction of 1 to 10 MHz was used to generate heat. However, resistance heating may also be used.
The formation of a semiconductor film by this reduced pressure vapor phase method was based on Japanese Patent Publication No. 1389/1989, which was patented by the present inventor. Of course, a glow discharge method or a sputter method may be used at a temperature of room temperature to 500°C. In this way, a silicon semiconductor film with a thickness of 0.1 to 2 μm was formed on this upper surface. This insulating layer 2 is pure
SiO ₂ and Si ₃ N ₄ were polycrystalline, but
When the amount of oxygen or nitrogen was 10 ¹⁸ to 10 ²¹ cm ^-3 , the semiconductor layer formed thereon had an epitaxial structure partially containing non-single crystals. In this example, the structure was substantially epitaxial. However, it is extremely important to make the semiconductor more equivalent to a perfect crystal by reducing the number of recombination centers. An object of the present invention is to reduce the number of such recombination centers in a semiconductor film in which a large number of them exist by adding hydrogen to the recombination centers. The field insulator 3 was made to have a thickness of 1 to 2 μm based on patents invented by the present inventor (Japanese Patent Publication No. 52-20312, Japanese Patent Publication No. 50-37500). After this, a gate insulator 12 is formed to a thickness of 100 to 1000 Å, and a silicon semiconductor contact 7 is formed as required, and a gate electrode 11 is formed on it by a self-aligning method and a semiconductor film is formed by a low pressure CVD method. I made it. In addition, overcoat 10 of SiO ₂ film with a thickness of 0.5 to 2μ
It was formed to a thickness of . At this time, in order to make the upper surface flat, PIQ or the like may be used instead of the SiO ₂ film. Holes 8 were formed for aluminum electrodes, and aluminum electrodes and leads 8 were formed. When the channel forming region 4 is P type, the source and drain 6 are formed of N ⁺ type impurities such as phosphorus and arsenic at a concentration of 10 ¹⁸ to ^{10 21} cm ^-3 . The gate electrode may also be made of metal such as molybdenum or tungsten.
Phosphorus or the like may be mixed at a concentration of 10 ¹⁹ cm ^-3 or higher to form a low-resistance semiconductor lead. On the other hand, the channel region has a low impurity concentration of 10 ¹⁴ to 10 ¹⁷ cm ^-3 ;
Extremely sensitive. It was known that electron or hole carriers are generally structurally sensitive in single crystals. However, the present invention has discovered that such structural sensitivity is not due to the crystal structure but to reactions at recombination centers present therein. As a result, the present invention attempts to neutralize and eliminate the recrystallization centers that give rise to this sensitivity. For this reason, in the present invention, 0.1 mol %, particularly 5 to 20 mol %, of hydrogen is added here. As a result, the first
After the structure shown in Figure A was completed, the carrier lifetime was increased by 10 ³ to ^{10 5} times by adding hydrogen.
Qss≒10 ¹⁰ cm even when evaluated by C-V diode characteristics
It showed a C-V characteristic of the order of ^-2 , which is almost in accordance with the theory. The results of changing various conditions during this hydrogenation are shown below.

【table】

【table】

[Table] The above processing results are obtained when the substrate is held in a hydrogen atmosphere, the temperature is lowered, and the substrate is taken out from the reaction tube. Chemical excitation of hydrogen gas followed the following method.
That is, the experiment was carried out by spirally winding a high-frequency induction furnace around a horizontal quartz tube with a diameter of 5 to 20 cm, particularly 15 cm (height 2 m), and a copper tube capable of water cooling in a ring shape. The frequency of the high frequency used is 1
~20MHz. Furthermore, a resistance heating furnace was placed outside of this, with a heating element arranged at right angles to the electromagnetic waves of this induction furnace. Into this reaction tube, 5 to 50 substrates, such as silicon substrates (diameter 10 cm) on which the semiconductor device shown in FIG. The pressure was further reduced to 10 ^-3 mmHg. Afterwards, hydrogen was introduced to bring the pressure back to near normal pressure. Furthermore, the vacuum was once again reduced to 10 ^-2 to 10 ^-3 mmHg, and then to 10 ^-1 to 10 mmHg. Hydrogen and helium were constantly introduced into the reaction system from one side, and the other side was continuously evacuated using a rotary pump or the like. Hydrogen is added to the substrate in a resistance heating furnace for 300 to 500 ml.
℃ and then the induction furnace was voltage excited. When current is excited, only the metal wall or metallic portion of the substrate is locally heated, which is not preferable. Therefore, the reactor gas was activated by voltage excitation. Furthermore, when the temperature is above 300°C, hydrogen atoms can freely move around in this solid because they are interstitial atoms. Therefore, these atoms could be added into the semiconductor to a sufficient equilibrium concentration. After this time the temperature was lowered to room temperature. During this time, the reactor gas continued to be excited. That is, heating + excitation was continued for 5 to 60 minutes, especially 30 minutes, and then excitation at room temperature was continued for 5 to 60 minutes, especially 15 minutes. The upper limit of the heating temperature was 500°C when there was a material that alloyed or melted at a relatively low temperature, such as aluminum. Therefore, in order to add hydrogen after the semiconductor device was completed, the temperature had to be below 500°C. In other cases, it may be treated at higher temperatures (600 to 1000℃), but one important thing is that hydrogen bonds with atoms in the semiconductor at temperatures higher than the 300 to 500℃ temperature range. As a result, _hydrogen is no longer added to the film. Therefore, when induction curing is performed at a high temperature, it is necessary to continue applying electrical energy for induction curing even if the processing temperature is lowered to room temperature. Furthermore, it is preferable that the pressure in the reaction vessel is as high as possible in a range that allows glow discharge or other high-frequency induced excitation or induced curing. In other words, in a hydrogen atmosphere, the higher the substrate processing temperature, the easier hydrogen moves in the film, and as a result, the easier it is for hydrogen to be added and the easier it is to desorb to the outside of the film. It is difficult to move through the membrane, and as a result, hydrogen is difficult to be added and is difficult to desorb to the outside of the membrane. Therefore, in the hydrogenation treatment, it is preferable to add hydrogen at a high temperature that does not dissolve the materials used, and to quickly lower the substrate temperature in a hydrogen atmosphere and take out the substrate from the reaction tube. This frequency may be microwave. In particular, when the frequency was 50 to 1000 MHz, the effect was remarkable even if the pressure inside the reaction tube was normal pressure, which was preferable. In that case, the reaction tube is preferably a waveguide. When creating a TEM mode, the size of the waveguide is inevitably determined, so it is preferable to radiate microwaves into a Quring oven, such as in a microwave oven. During induction curing, the pressure in the reaction tube may be increased or decreased. At high temperatures, there is a large equilibrium between the outside air and the gas-solid phase in the semiconductor, and a large amount of additives can be added to the semiconductor. For this reason, rapid cooling while performing induction curing at a high temperature was more effective than completing the process by gradually cooling from a high temperature state. For example, by rapidly cooling from 500°C to room temperature, it was possible to add 3 to 10 times the concentration compared to slow cooling. The reactive gas may be hydrogen alone or may contain some helium. However, while hydrogen bonds with dangling bonds, helium hits half-finished dangling bonds to promote mutual bonding, so it is actually preferable to first excite with helium and then with hydrogen. i.e. Quring 5-15 minutes with He, 0.1-100mmHg especially 10mmHg
and then 0.01 to 10 mmHg for 5 to 15 minutes, especially
Curing was performed in hydrogen at 0.1 mmHg. In addition, in practical terms, 100% hydrogen or 5 to 30%
% helium or neon was mixed as an excitation gas. The present invention was implemented in a semiconductor device as shown in FIG. 1, and the amount of excitation gas added was tested by mixing the gas into the semiconductor, heating the substrate in vacuum, and releasing the gas. Quantification was carried out by so-called gas chromatography or Augier spectroscopy. In that case, it was found that the excitation gas was added in an amount of 0.1 mol %, in particular from 1 to 20 mol %. Of course, it is more preferable to add 20 mol% or more. However, in general, a tendency towards saturation was observed. In the following examples of the present invention, induced cuering was carried out in the same manner as described above. Figure 1B is SOS (Silicon-on-Sapphire)
This is an example. A semiconductor such as alumina, sapphire, spinel, etc. on the substrate 1 is epitaxially grown to a thickness of 0.02 to 2 μm, and a source 5, a drain 6, a buried field insulator 3, a semiconductor direct contact 7, and a self-aligned gate electrode 31 are formed. , a gate insulating film 12, and a CVD SiO ₂ film 10. In this case, the alumina component of the substrate and the semiconductor are bonded at the portion 9, resulting in a non-single crystal state. For this reason, the formation of the source and drain caused abnormal diffusion. For this reason, even if this semiconductor film could be made to have a thickness of 0.01 to 0.3 μm, it was of no practical use. However, even if the thickness is 0.01 to 0.5 μm as in the present invention, if the excitation treatment is performed after these semiconductor devices are completed or almost completed, this incomplete layer 9 will have a recombination center of 1/2. 100～1/10000
and its density decreased, making it possible to handle it in the same way as previously known single crystals.
This excitation treatment has a remarkable effect of neutralizing the interface states existing between the semiconductor substrate (channel region) and the gate insulating film or the dangling bonds existing in the gate insulating film, and is effective in neutralizing the dangling bonds present in the gate insulating film. This was an extremely favorable method for improving FIG. 2 shows an embodiment of the invention. This figure 2 shows that a second MIS-FET is provided above or above one MIS-FET, and a high-density integrated circuit (LSI,
It was an attempt to manufacture VLSI). This will be explained below with reference to the drawings. In FIG. 2A, an insulating film 2 such as silicon oxide is formed on a semiconductor substrate 1 to a thickness of 0.1 to 2 μm. in this case,
The substrate does not necessarily have to be a semiconductor. Subsequent heat treatment An insulating material may be used as long as it satisfies practical conditions such as heat conduction and processing. Polycrystalline silicon was used here. The insulating film 2 was formed by oxidizing the substrate 1. Furthermore, a semiconductor silicon film was formed on this upper surface using a low pressure CVD method to a thickness of 0.1 to 2 μm. The field insulator ³ is buried in the semiconductor layer by a selective oxidation method using a ^double film of ^silicon nitride and silicon oxide as a mask. It was formed by At this time, the field film may be etched so that the field insulator 3 and the semiconductor layer are approximately on the same plane, or a portion of the semiconductor layer may be removed before oxidation. Further, a gate insulating film 12 was formed to a thickness of 100 to 1000 Å. This gate insulating film may be a thermal oxide film formed by oxidizing a semiconductor layer, or may have a double structure of oxide and phosphorus glass, alumina, or silicon nitride, or may have a cluster or film in this gate insulating material. It may also be a nonvolatile memory formed of semiconductor or metal. After this, a second semiconductor layer is formed on this top surface.
It was formed to a thickness of 0.1 to 2μ and selectively removed. In this drawing, one of the second semiconductor layers is used as the gate electrode 11. Another application is to have the source 25, drain 24 of the second MIS-FET on the upper surface,
It was provided as a channel region 29. Gate electrode 11
As a mask, the source 5 of the first MIS-FET,
The drain 6 was formed by ion implantation. Of course, a thermal diffusion method may also be used. Furthermore, as is clear from the drawing, the gate electrode 11 is connected to the second MIS-FET via the field insulator 3, which is not clearly shown.
source 25. In the second MIS-FET, after forming the third semiconductor layer 21, the source and drain are diffused into the gate electrode 21 and the gate insulator 22 therebelow using ion implantation or thermal diffusion. Created. In this drawing, the second MIS-FET is provided on the upper surface of the first MIS-FET, that is, diagonally above the first MIS-FET. However, the arrangement, size, and wiring of these MIS-FETs are determined according to free design considerations. Furthermore, a resistor and a capacitor as shown in FIG. 2B may be made simultaneously on the same substrate, and diodes such as a protection diode may also be made. In FIG. 2B, a field insulator 3 is formed on a single crystal semiconductor substrate 1 by selective oxidation to a thickness of 0.5 to 2 μm. In addition, a gate electrode 11 such as a semiconductor,
11', and the source 4, drain 31 and source 31, drain 5 are mixed with boron or phosphorus at a concentration of 10 ¹⁹ to 10 ²¹ cm ^-3 to form a P channel or N channel.
This is a channel MIS-FET formed.
Impurity region 31 is one MIS-FET (left side of the drawing)
drain and the other MIS-FET (right side of the drawing)
This is an example of an inverter that acts as a source. Furthermore, an insulating film 10 for overcoat is formed on this upper surface.
If it is formed to have a thickness of 0.5 to 2 μm and its upper surface is flat, microfabrication of the third MIS-FET to be formed on the upper side is possible. Thereafter, a non-single crystal semiconductor was formed on the upper surface to a thickness of 0.2 to 2 μm. The impurity concentration was 10 ¹⁴ to 10 ¹⁶ cm ^-3 to make it P type, and the condition was that the channel region 29 sufficiently functions as a channel in the operating state. Furthermore, a non-single crystal resistor 37 is attached to this third MIS-FET using a photomask.
source and connected to lead 38. Drain 24 was connected to the lower electrode 34 of the capacitor. This upper insulating film is the dielectric material 33 of the capacitor.
It is also the gate insulator 22 of the third MIS-FET. The gate electrode 21 and the upper electrode 36 of the capacitor were formed on this upper surface. The substrate electrode of the channel forming region 29 of the third MIS-FET is connected to the gate electrode 11 of the first MIS-FET so that a substrate bias is applied, and the gate electrode 11 is substantially connected to the two MIS-FETs. −
The FET channel state can be controlled. Of course, if a gate insulator is formed between the channel region 29 and the gate electrode 11,
The third MIS-FET is a double-gate MIS-FET having gate electrodes on the lower and upper sides. Of course, the upper gate electrode may be removed and the lower gate electrode 11 may simultaneously control the lower first MIS-FET and the upper third MIS-FET. In other words, one gate can control two MIS-FETs, or two gates can control one MIS-FET.
A feature of the present invention is that the FET is controlled.
In addition, there are not only leads on the same board, but also MIS-
active elements or resistors like FETs,
In addition to the capacitor, a diode can also be provided. In addition, if a plurality of these elements are integrated, it is possible to achieve a density 2 to 10 times that of the single-layer element shown in FIG. Of course, the present invention can be applied to non-single-crystal semiconductors by performing "induction curing" after these devices are completed or mostly completed, as already detailed in the explanation of FIG. 1 in A and B. This becomes possible not only by removing recombination centers but also by lowering the density of interface states existing at the interface between a polycrystalline or amorphous semiconductor or a semiconductor and an insulating object using hydrogen or the like. In the above description, after the semiconductor devices shown in FIGS. 1 and 2 are cured, it is preferable to form an overcoat 40 of silicon nitride by a plasma method. This is because silicon nitride also has a masking effect on atoms such as hydrogen, and has the effect of sealing up hydrogen and the like once added into a semiconductor device and preventing them from escaping. Therefore, in addition to preventing contamination with sodium, etc. from the outside, the reliability is significantly improved. In the embodiments of the present invention, silicon semiconductor was mainly used as the semiconductor material. However, this is the same even for germanium etc.
The same applies to compound semiconductors such as GaP, GaAs, GaAlAs, SiC, and BP. In addition, the semiconductor device is not limited to simply MIS-FETs, but can also be integrated ICs or LSIs, and is effective for all semiconductor devices.

[Brief explanation of drawings]

FIG. 1 is a longitudinal sectional view showing an embodiment of the present invention. FIG. 2 is a longitudinal sectional view showing another embodiment of the present invention.

Claims (1)

[Claims] 1. In a semiconductor device in which at least a part of a channel region adjacent to a gate insulator of an insulated gate field effect transistor is made of a non-single crystal semiconductor,
After the semiconductor device is completed or largely completed, it is heated for 500 hours in a hydrogen-added atmosphere.
By holding the temperature below ℃ and then rapidly cooling it,
A method for manufacturing a semiconductor device, comprising neutralizing dangling bonds between a semiconductor and a gate insulator in the channel region, and reducing an interface state density existing at an interface between the channel region and the gate insulator.