JPH06342401A - Secondary memory controller - Google Patents

Abstract

PURPOSE:To enable effective utilization by improving the hit rate of a buffer memory for storing the partial data of a secondary storage device. CONSTITUTION:A buffer storage device 40 stores the data blocks of secondary storage devices 70 and 71. When an access request 1 is inputted, a buffer control circuit 60 refers to a buffer managing table 30 and when there is any relevant block in a buffer 40, it is sent to a data line 2. When there is not such a block, the block is transferred from the secondary storage device to the buffer 40, and the secondary memory address or the like is registered on the table 30. On the other hand, a sequential access detection circuit 10 inputs the access request 1 as well and predicts whether the buffer is accessed continuously even after the address of the access request or not and when the prediction is made successful, the secondary memory address or the like is registered on a first read control table 12. A first read control circuit 50 first reads the relevant block from the secondary storage device to the buffer 40 while referring to the table 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a secondary storage control device, and more particularly to a control device for a secondary storage device using buffer storage.

[0002]

2. Description of the Related Art In a secondary storage device having a relatively slow access mechanism, such as a magnetic disk storage device, conventionally, the access arm has been efficiently operated to substantially improve the performance. On the other hand, like the main memory,
If the buffer storage device is also used in the secondary storage device, the data of the area to be accessed thereafter is read into the high-speed buffer storage in advance, so that when the access request is actually issued to that area, Service is possible. As a conventional technique of this kind, for example, Japanese Patent Laid-Open No.
The disk cache control method described in Japanese Patent Publication No. 157056 is cited.

[0003]

In order to effectively use the buffer storage device and shorten the average access time, it is necessary to increase the hit rate of the buffer. To do this, predict the areas that are likely to be accessed as accurately as possible,
Just before use, read from secondary storage to buffer storage,
Return the unusable area to secondary storage,
It is necessary to free that buffer.

An object of the present invention is to provide a means for automatically predicting that a request for a physically close address will be made to a secondary storage device having an access mechanism with a slow operation, and the access will be predicted. It is an object of the present invention to provide a secondary storage controller which can issue separate requests for consecutive addresses as a single request, reduce the input / output overhead, and at the same time effectively use buffer storage.

[0005]

In order to achieve the above object, the present invention provides a secondary storage control device for processing and executing an access request to a secondary storage device such as a magnetic disk. A buffer memory for storing a part of the data, and a buffer control unit for accessing the buffer memory when the access request data is stored in the buffer memory, and the secondary storage device. The prefetch control means for prefetching the data and storing it in the buffer memory, and a plurality of recently accepted access requests for the current access request are checked to see if the data after the address of the current access request is continuously accessed. It is characterized by having a forward access detection means for activating the prefetch control means when it is predicted and judged to be accessed. To.

Further, the forward access detecting means is characterized in that the prediction is performed by checking whether or not the address adjacent to the address of the current access request is included in the plurality of recently received access requests. To do.

[0007]

A large number of files are stored in the secondary storage device, and they are often in continuous areas. If these files are accessed in the order of address, the order of use can be predicted. It is possible. By detecting that the sequential access is started and prefetching the area predicted to be sequentially accessed thereafter into the buffer, it is possible to service the subsequent sequential access request from the buffer. Particularly, by predicting the sequential access based on a plurality of recently received access requests, for example, in the case where the secondary storage device is shared by a plurality of processing devices and the access from each processing device is mixed. If the access request from a certain processing device is for consecutive addresses (in this case,
From the side of the secondary storage device, continuous addresses seem to come and go), but the continuous data can be predicted efficiently, and the buffer utilization efficiency can be improved.

[0008]

The present invention will be described in detail below with reference to an embodiment shown in the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. In the figure, reference numerals 70 and 71 are secondary storage devices such as a magnetic disk storage device, and 40 is a high-speed buffer storage device for storing some data blocks in the secondary storage device in advance. The block transfer control between the secondary storage devices 70 and 71 and the buffer storage device 40 is controlled by the prefetch control circuit 50 and the buffer control circuit 60. The buffer storage device 40 is composed of n buffers 1 to n each having a basic size. The buffer management table 30 manages the blocks read to the buffer storage device 40, and each entry thereof corresponds to each basic buffer 1 to n of the buffer storage device 40. 1 of the buffer management table 30
The entry is the secondary storage address (disk address) DA read in the corresponding buffer, the prefetch flag LA,
Unused flag U and free entry display bit F
Consists of. The forward access detection circuit 10 is a circuit for predicting, in response to an access request from the secondary storage device, whether or not the address and subsequent addresses can be forward accessed.
A register and the like for stacking individual access requests are provided. The buffer use completion detection circuit 11 is a circuit that monitors the access request and detects that the use of each buffer is completed. Completion of use of individual buffers can be recognized by detecting that the last block in each buffer has been accessed.

The prefetch control table 12 is a memory for registering information necessary for prefetching a desired data block from the secondary storage devices 70 and 71 to the buffer storage device 40 for each area where forward access is expected. Is. One entry of the prefetch control table 12 is DA, BT, IOT.
And SZ. DA is the head secondary storage address that is predicted to be accessed sequentially, and is searched and registered by the sequential access detection circuit 10 when an input / output request (access request) is made. BT represents the retention time of the prefetch data in the buffer storage device 40. In other words, it is the time from the pre-reading of the data contained in the corresponding buffer to the completion of the use, and the pre-reading control circuit 50 adds and updates the usage time at regular time intervals. It IOT indicates the input time until the data is read from the secondary storage device to the buffer, and this time is monitored and registered by the prefetch control circuit 50. SZ is a buffer size for read-ahead, which is created by the read-ahead size determination circuit 20, and
Set via 02. For the signal line 101, the prefetch size determination circuit 20 uses the prefetch control table 12 to read BT, I
It is a line for inputting OT. The read-ahead size determination circuit 20 is a circuit that determines the buffer size for read-ahead, and initially sets an initial value with a predetermined size.
After that, the optimum buffer size to be read next is determined and set according to BT, IOT, or the like.

Next, the operation of FIG. 1 will be described. Now, an access request from the central processing unit to the secondary storage device is issued by the signal line 1
It is supposed to be issued to. When the access request to the secondary storage device is input, the buffer control circuit 60 searches the DA field of the buffer management table 30 to check whether or not the block to be accessed has been read out to the buffer storage device 40, and the buffer is already buffered. If present, it is used to serve via the central processing unit and the data line 2.
Further, when the block to be accessed is not read in the buffer storage device 40, the buffer control circuit 60 actually executes an access request to the secondary storage devices 70 and 71, and the buffer storage device 40 for the read data. To the buffer management table 3 such as the secondary storage address
The data is read out to the buffer, and the central processing unit is serviced again.
In addition, the buffer control circuit 60 uses the secondary storage devices 70 and 71.
When newly registering the data read from the buffer storage device 40 into the buffer storage device 40, a buffer in the buffer storage device that is unlikely to be used is selected, and the contents thereof are written to the secondary storage devices 70 and 71 to create an empty buffer. ,
Used as a new buffer entry. Since various algorithms related to this have already been proposed, detailed description thereof will be omitted.

On the other hand, when a secondary storage access request is issued to the signal line 1, the forward access detection circuit 10 detects that the most recently received access request has an adjacent input / output address. It is checked whether or not there is, and if there is, it is predicted that subsequent sequential access will be performed after the address of the access request. Then, the forward access detection circuit 10 prefetches the first secondary storage address predicted to be forward accessed to the prefetch control table 1
Pre-reading size determination circuit 2 registered in the AD field 2
0 and the prefetch control circuit 50 are activated. As a result, the read-ahead size determination circuit 20 determines the initial read-ahead size according to the state of the input / output load applied through the signal line 21 and registers it in the SZ field of the read-ahead control table 12. The prefetch control circuit 50 inputs the contents of the DA field and SZ field newly registered in the prefetch control table 12 to access the secondary storage devices 70 and 71, and the S address from the address indicated by the DA field.
Data equal to the buffer size of the Z field is read and stored in the buffer storage device 40. At the same time, the prefetch control circuit 50 registers the secondary storage address in the DA field of the corresponding entry (entry corresponding to the buffer in which data is stored) on the buffer management table 30, and also matches the prefetch flag LA and the incomplete use flag U. Set. Further, the prefetch control circuit 50 is provided in the buffer storage device 4
The use start time and the required input time for the area read out to 0 are registered in the BT field and the IOT field of the prefetch control table 12. After that, the contents of the BT field are updated by the prefetch control circuit 50 at regular time intervals to indicate the retention time of the buffer.

As described above, the buffer control circuit 60 searches the buffer management table 30 when an access request is issued to the signal line 1. As a result, the block to be accessed is read by the prefetch control circuit 50 and stored in the buffer storage device 40. Once pre-read, it can be used to immediately service the central processing unit. If the block to be accessed is not on the buffer, the buffer control circuit 60 stores the requested block in the secondary storage devices 70 and 7.
Although the data is read from 1 to the buffer, it is conceivable that this actually requested area and the preread area by the preread control circuit 50 overlap. This gives priority to the block actually requested by the buffer control circuit 60,
It is solved by providing a means to prevent overlap with the prefetch block.

The secondary storage access request issued to the signal line 1 is also input to the buffer use completion detection circuit 11. The buffer use completion detection circuit 11 monitors the access request, and when detecting the input / output request for the last block in the corresponding buffer, resets the use incomplete flag U in the corresponding buffer entry of the buffer management table 30. , Buffer control circuit 60. Whether or not the access request is for the last block in the corresponding buffer can be detected as follows. That is,
First, the buffer management table 30 is searched to find out in which buffer of the buffer storage device 40 the block requested to be accessed exists. Then, a fixed number is added to the contents of the DA field to determine the end of the buffer containing the block. The block address of is obtained, and the final block address is compared with the access request address.

When the buffer control circuit 60 receives the report of the completion of use of the buffer, if the buffer is changed, the buffer control circuit 60 performs the writing process to the secondary storage devices 70 and 71,
The corresponding entry in the buffer management table 30 is cleared so that it can be used as an empty buffer, and its F bit is set as an empty entry. Note that the writing process to the secondary storage device may be performed as one output process together with other prefetched buffers. Don't write back the unchanged buffer again. As a result, the time for input / output can be further shortened.

By detecting the completion of use of the buffer, the retention time of data in the corresponding buffer is determined. When the prefetch size determination circuit 20 receives the report that the forward access detection circuit 10 predicts that the forward access will be continued after the address of the access request, the BT field of the corresponding entry of the prefetch control table 12,
The contents of the IOT field and SZ field are sent to the signal line 10
1 to input the buffer retention time per single buffer from the BT and SZ, and according to the buffer retention time, the input / output time per single buffer, and the load mode given from the signal line 21, The optimum buffer size to be read is determined and set in the corresponding SZ field of the prefetch control table 12 through the signal line 102. That is,
When it is predicted that subsequent sequential access will be performed after the address of the actual access request, the read-ahead size determination circuit 20 initially determines a predetermined buffer size based on the load state, etc. The read-ahead buffer size is dynamically adjusted each time the buffer is completely used, and the optimum buffer size to be read next is determined. The read-ahead control circuit 50 executes the read-ahead by the newly set buffer size.

It should be noted that it is possible to prevent misprediction of sequential access,
When the sequential access is completed, it is necessary to cancel the prefetch control for the relevant area. This can be done as follows. The buffer retention time of the BT field of the prefetch control table 12 is recorded and updated by the prefetch control circuit 50, and when the subsequent access is lost, the value is increasing. Therefore, the prefetch control circuit 50 checks the value of each BT field of the prefetch control table 12, and when it exceeds a certain value, the corresponding entry is deleted from the prefetch control table 12.

Next, a method of determining the look-ahead buffer size will be described in some detail. Now, let us say that the maximum and minimum buffer sizes are bmax and bmin, respectively. The buffer retention time L and the input / output time I per single buffer show the tendency as shown in FIG. 2 depending on the read-ahead buffer size b.
Which buffer size is optimal depends on the load (usage rate) on the secondary storage device. Therefore, when the load on the secondary storage device is high, increase the buffer size,
If the load on the buffer is heavy, you can reduce the buffer size. When the loads on the secondary storage device and the buffer are balanced, the buffer size may be selected so that the loads on both are minimized. The load state is given to the prefetch size determination circuit 20 by a load mode signal line 21 which is set and reset by a command from the central processing unit, whereby the current state is either a high input / output load state or a CPU load. You can know whether it is high or both are in balance.

As described above, as one embodiment of the present invention, the case where various control circuits and the like are respectively configured by hardware as shown in FIG. 1 has been shown. However, a part or all of these circuits or devices may be a microcomputer or the like. It is needless to say that the present invention is not limited to the configuration shown in FIG.

[0020]

As is apparent from the above description, according to the present invention, in the secondary storage device using the buffer storage,
For the current access request, predict whether data after that address may be accessed subsequently, and if so, by prefetching the data in the secondary storage device and storing it in the buffer It is possible to increase the hit rate of the buffer storage and effectively use the buffer storage. In particular, by predicting forward access based on recently received multiple access requests, for example,
In the case where the secondary storage device is shared by a plurality of processing devices and the accesses from the respective processing devices are mixed, and the access request from a certain processing device is to consecutive addresses ( In this case, from the side of the secondary storage device, even if continuous addresses seem to be scattered, the continuous data can be predicted efficiently, and the buffer utilization efficiency can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a prefetch size determination method.

[Explanation of symbols]

 1 Secondary Storage Access Request Line 2 Data Line 10 Forward Access Detection Circuit 11 Buffer Usage Completion Detection Circuit 12 Prefetch Control Table 20 Prefetch Size Determination Circuit 30 Buffer Management Table 40 Buffer Storage Device 50 Prefetch Control Circuit 60 Buffer Control Circuit 70, 71 2 Next storage device

Claims (2)

[Claims] 1. A secondary storage control device for processing and executing an access request to a secondary storage device such as a magnetic disk, and a buffer memory for storing a part of data of the secondary storage device, and an access. When the requested data is stored in the buffer memory, buffer control means for accessing the buffer memory, and prefetch control means for prefetching the data in the secondary storage device and storing it in the buffer memory , In response to the current access request, check the multiple access requests that have been recently received, predict whether data after the address of the current access request will be subsequently accessed, and if it is judged that there is a possibility of being accessed, the prefetch control will be performed. And a sequential access detection means for activating the means. 2. The forward access detection means makes the prediction by checking whether or not a neighbor of the address of the current access request is included in the plurality of recently received access requests. The secondary storage control device according to claim 1.