JPH09128325A - Hierarchical bus control system and bus bridge - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the latency at the time of transferring a transaction from one bus to the other bus by snooping a cache when the transaction is issued to one of a high-order bus or a low-order bus and precedingly executing the arbitration of the other bus before deciding whether or not the transaction is transferred to the other bus. SOLUTION: When the transaction of a high-order bus is inputted to a bus bridge 30, the index part of an address in the transaction is inputted to a tag- read circuit 32 and a tag corresponding to the index is read from a tag RAM 50. The tag is compared with the tag of the actual address in a mis-hit judging circuit 38. At the time of non-coindidence, the mis-hit judging circuit 38 issues a mis-hit signal, it is inputted to an arbitration circuit 44 with an OR circuit 112 and the arbitration of a low-order bus is executed. After that, the transaction to be transferred is issued to the low-order bus.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus control method for transferring a transaction from one bus (upper bus or lower bus) to another bus (lower bus or higher bus) in a hierarchical bus system.

[0002]

2. Description of the Related Art A bus sharing type multiprocessor system in which a plurality of CPUs are commonly connected to a main memory or an I / O device via a bus and data is transmitted and received to and from other CPUs, main memories, and the like is prevalent. . In this multiprocessor system, if the number of parallel CPUs is increased in order to improve the computing power, the load on the bus is increased, so that the throughput and the latency are deteriorated, and the total processing power is not improved enough to meet the increase in the number of CPUs. .

On the other hand, the present applicant has filed Japanese Patent Application No. 7-28.
No. 5829, parallel CPUs are connected to different upper buses in small numbers, and a bus bridge having a cache memory is provided for each upper bus, and each upper bus is connected to the main memory via each bus bridge. We proposed a hierarchical bus system that connects to a lower-level bus connected to the bus. FIG. 5 is a diagram showing a schematic configuration of such a hierarchical bus system. The CPU 10 is connected to one upper bus 12 in a relatively small number, and each upper bus is connected to the main memory 20 via the bus bridge 14. It is connected to the connected lower bus 18. A cache 16 is connected to each bus bridge 14, and the cache 16 is shared by the upper CPU 10.

According to such a hierarchical bus system, C
When the total number of PUs is the same, the number of CPUs connected to the upper bus is smaller than that in the case where no hierarchization is performed, so the load on the upper bus is reduced. Also, by providing a cache on the bus bridge, it is not necessary to read the data to the main memory when the requested data for the transaction on the upper bus is in the cache on the bus bridge. I won't. Therefore,
According to the multiprocessor system having the hierarchical structure, it becomes possible to efficiently operate a large number of CPUs.

[0005]

In such a hierarchical bus system, when a transaction is issued to the upper bus or the lower bus, the bus bridge searches (snoops) the cache and transfers the transaction to the lower bus or the upper bus. Determine if it is not necessary to For example, if the requested data for a transaction from one bus is in the cache, the bus bridge does not transfer the transaction, and if it is not in the cache, the bus bridge transfers the transaction to the other bus.

In this way, when it is decided to transfer a transaction from one bus to the other,
The bus bridge needs to arbitrate for the right to use the other bus. Conventionally, arbitration from the bus bridge to the bus has been performed after the snoop of the cache is completed and it is decided to transfer the transaction.

FIG. 6 is an explanatory diagram showing the flow of processing in the conventional hierarchical bus system until the transaction issued to the upper bus is transferred to the lower bus. As shown in FIG. 6, when issuing a transaction to the upper bus, the CPU first arbitrates the upper bus and thereby acquires the bus use right. Then, C
The PU issues a transaction to the upper bus. The bus bridge connected to this upper bus detects this transaction and either does not have the address of this transaction (the address of the data requested by the transaction) or snoops its cache. Then, the bus bridge determines whether the bus bridge transfers the transaction of the upper bus to the lower bus based on the result of this snoop, that is, whether the bus bridge cache has data required by the transaction. Determine whether. Then, when it is determined in this determination that the transaction should be transferred to the lower bus, the bus bridge issues a bus request signal to the lower bus to arbitrate the lower bus and acquire the bus use right. A transaction to be transferred to the lower bus was issued later.

As described above, in the conventional hierarchical bus system,
The arbitration for the transfer destination bus was performed only after it was decided to transfer the transaction from one bus to the other bus by the snoop of the bus bridge cache. On the other hand, the cache of the bus bridge needs to have a relatively large capacity, that is, a relatively low speed in order to support a plurality of CPUs connected to the upper bus, so it takes some time to snoop this cache. . Therefore, in the conventional hierarchical bus system, every time a transaction is transferred via the bus bridge,
There is a problem that processing delay occurs.

The present invention has been made in order to solve such a problem, and in a hierarchical bus system, reduces latency in transferring a transaction from an upper bus to a lower bus or from a lower bus to an upper bus. It is an object to provide a hierarchical bus control method.

[0010]

In order to achieve the above object, a hierarchical bus control system according to the present invention is a bus bridge in which a plurality of processors are connected to an upper bus and a cache is provided for the plurality of upper buses. In a hierarchical bus system in which each upper bus is connected to a lower bus via each bus bridge and the lower bus is connected to the main memory, the bus bridge has a transaction on one of the upper bus and the lower bus. When issued, before deciding whether to snoop the cache and transfer the transaction to the other bus, the other bus is arbitrated in advance.

According to this structure, when a transaction is issued to one bus, the bus bridge arbitrates the other bus before the snooping of the bus bridge cache, which takes a relatively long time, is completed. The timing of completing the arbitration will be faster than before. Therefore, when the cache snoop ends and the transaction transfer to the other bus is decided, the bus bridge can issue the transaction to the other bus earlier than before, so that the transaction is transferred from one bus to the other bus. The latency when doing can be reduced.

[0012] In this configuration and the configuration described below, the bus bridge "transfers" a transaction from one bus to the other bus means that the bus bridge receives a transaction from one bus. It means issuing a transaction determined on the basis of the type of the transaction and the state of the cache to the other bus. Therefore, the transaction issued by the bus bridge to the other bus is not always the same type of transaction as the transaction received from the one bus by the bus bridge.

Further, in another configuration of the present invention, in the above configuration, the bus bridge may transfer the transaction to the other bus based on the type or address of the transaction issued to the one bus. Arbitration to the other bus (ie, whether to snoop the cache and transfer the transaction to the other bus) only if it is determined that the transaction is likely to be transferred. Arbitration that precedes the above) is performed.

This structure is intended to reduce wasteful preceding arbitration. That is,
If, as a result of snooping, the data requested by a transaction on one bus is present in the bus bridge cache, then the transaction will not be transferred to the other bus and the previous arbitration performed before snooping will be wasted. However, this configuration is intended to reduce such waste. Here, since the probability of the transaction being transferred from one bus to the other can be estimated to some extent from the transaction type or address, in this configuration, the type of transaction issued to one bus or The transferability of the transaction is determined from the address, and the preceding arbitration is performed only when it is determined that the transferability is high. Therefore, according to this configuration, useless preceding arbitration can be reduced and the load on the bus can be reduced.

Another structure of the present invention is to connect a plurality of processors capable of splitting to an upper bus, provide a bus bridge having a cache for each of the plurality of upper buses, and provide each of the upper buses. In the hierarchical bus system in which the lower bus is connected to the main memory via the bus bridge of, and when the transaction of the upper bus is split and transferred to the lower bus in the hierarchical bus system, the transfer is performed. It is characterized in that arbitration for the upper bus is preceded after a predetermined time interval from the transfer processing without waiting for a response from the lower bus for the transaction.

This configuration is intended to reduce the latency when the bus bridge splits a transaction issued from a processor on the upper bus and transfers it to the lower bus when the upper bus is a split bus. is there. That is, in this configuration, the arbitration of the upper bus required for returning the split response for this split transaction to the original processor is performed in advance before the response from the lower bus for that transaction is received. Advance the timing of issuing a split response to. According to this configuration, when the transaction issued from the processor is split, the time until the split response to the transaction is returned to the processor can be shortened.

In this configuration, the upper bus is separated from the occupation of the original processor until the upper bus is arbitrated after the split transfer of the transaction. Therefore, the upper bus is used for another transaction in the meantime. be able to. Therefore, the time interval between the transaction split transfer and the arbitration of the upper bus depends on how much the processor is allowed to occupy the upper bus and how long the arbitration delay for split response is allowed. It is necessary to make a decision by comprehensively considering

Another structure of the present invention is characterized in that the preceding arbitration to the upper bus is prohibited when the total bus occupation ratio of the processors connected to the bus bridge exceeds a predetermined threshold value. To do.

In this configuration, the bus occupancy is the time during which one device occupies the bus per unit time. In the case of a processor, the bus occupation rate can be obtained from the performance of the processor. According to this configuration, when the bus load of the upper bus is predicted to be high,
It is possible to prevent the preceding arbitration of the upper bus.

Further, according to another configuration of the present invention, the preceding arbitration to the lower bus is prohibited when the sum of bus occupancy rates of the processors and I / O devices included in the hierarchical bus system exceeds a predetermined threshold value. It is characterized by doing.

According to this configuration, when the bus load of the lower bus is predicted to be high, it is possible to prevent the preceding arbitration of the lower bus from being performed.

Further, another configuration of the present invention is that each bus bridge constantly monitors the bus loads of the upper bus and the lower bus, and when the bus load of each bus exceeds a predetermined threshold, It is characterized in that the preceding arbitration is prohibited for a bus exceeding a threshold value.

That is, when the preceding arbitration is wasted, the bus occupied as a result of the preceding arbitration is wasted. For example, when the bus is busy, such wasteful bus occupation causes a decrease in throughput. Therefore, in this configuration, the bus load of each bus is constantly detected, and when the bus load exceeds a predetermined threshold value, the preceding arbitration for the bus is prohibited. That is, in this configuration, by dynamically switching between the mode in which the preceding arbitration is permitted and the mode in which the preceding arbitration is prohibited, an increase in bus load is prevented and a decrease in throughput is prevented.

Further, the bus bridge according to the present invention extracts a tag from a compressed tag memory storing a table obtained by compressing information in the tag memory by a predetermined method and an address of a transaction issued to one of the buses, and the predetermined tag. Tag compression means for compressing in accordance with the method, compressed tag detection means for extracting an index from the address of a transaction issued to one bus, and reading compressed tag information corresponding to the index from the compressed tag memory, and a tag Comprising a comparison means for comparing the output of the compression means and the output of the compression tag detection means, the result of the comparison by the comparison means,
When the output of the tag compression unit and the output of the compressed tag detection unit do not match, an arbitration signal is output to the other bus without waiting for the end of the search of the tag memory.

In this structure, if the compression tag read from the compression tag memory based on the transaction index and the compression tag of the transaction do not match, the transaction request is stored in the cache. There is no data to do. This comparison of compressed tags is done by searching the tag memory (snoop).
Can be done in less time. Therefore, according to this configuration, it is possible to know that the requested data of the transaction does not exist based on the comparison of the compressed tags before the result of the tag memory search, which takes a relatively long time, is obtained, so that the transaction is transferred. You can know things faster. Therefore, in this configuration, when the output of the tag compression unit and the output of the compressed tag detection unit do not match,
Since the bus bridge outputs the arbitration signal to the transfer destination bus, the arbitration is completed faster, and the time required for transferring the transaction can be shortened.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings.

The following embodiments are applied to the hierarchical bus system shown in FIG. 5, for example. In each of the following embodiments, the CPU will be described as having its own cache (hereinafter referred to as a CPU cache). Further, in each embodiment, the CPU cache and the cache of the bus bridge (hereinafter referred to as bridge cache) are write-back type caches, and in order to maintain the consistency of the contents of each cache (cache consistency), The MESI protocol is used to maintain multi-level inclusion (MLI) between the CPU cache and the bridge cache.

The MLI is a C connected to a certain upper level bus.
It means that the data in the PU cache also exists in the bridge cache of the bus bridge connected to the upper bus. Therefore, in the following embodiments, the bridge cache has a capacity that is at least larger than the sum of the capacities of the CPU caches above it.

The MESI protocol is a state of each cache block.
Is one of the methods of maintaining the cache consistency by providing the data indicating the above, and each cache block is controlled by using four kinds of states of M, E, S, and I.
Here, the meanings of the M, E, S, and I states are as follows.

M (Modify): Only the cache has updated data of the block (that is, the latest data of the block).

E (Exclusive): Only the cache has data having the same contents as the main memory for the block.

S (Shared): Although the block has the same data as the main memory, there is a possibility that another cache also has the data.

I (Invalid): The block is invalid.

The above states basically indicate the relationship between caches at the same level. That is, the state of the CPU cache shows the relationship with other CPU caches, and the state of the bridge cache shows the relationship with other bridge caches. Therefore, even if the state of the bridge cache is M, that does not mean that the bridge cache itself has the latest data, and either the bridge cache itself or the CPU cache above it has the latest data. It means having.

An embodiment of the present invention will be described below by taking a system adopting such a protocol as an example. However, this is merely an example, and the present invention is also effective for a system that employs a protocol other than the above.

Embodiment 1. In the present embodiment, when a transaction is issued to either the upper bus or the lower bus, the other is preceded by the snooping of the bridge cache before determining whether to transfer the transaction to the other bus. By performing arbitration of the bus, the processing delay caused by the transaction transfer is shortened.

The method of this embodiment will be described below with reference to FIG. 1 by taking transaction transfer from the upper bus to the lower bus as an example.

As shown in FIG. 1, when issuing a transaction to the upper bus, the CPU first arbitrates the upper bus to acquire the bus use right. After that, the CPU issues a transaction to the upper bus. The bus bridge connected to this upper bus detects this transaction and either does not have the address of this transaction (the address of the data requested by the transaction) or snoops its cache.

Conventionally, the arbitration of the lower bus is started after it is determined that the transaction needs to be transferred from the upper bus to the lower bus based on the result of the snoop, but in the present embodiment, the snoop of the bridge cache is started. Arbitration of the lower bus is started before is completed. That is, in the present embodiment, when the bus bridge receives a transaction from the upper bus, it starts snooping the bridge cache and outputs an arbitration signal (bus request signal) to the lower bus to confirm the arbitration of the lower bus. Start. Here, the method of arbitration of the lower bus may be either centralized arbitration or distributed arbitration.

According to the method of performing arbitration prior to this transaction transfer decision (hereinafter referred to as "preceding arbitration"), for example, it is determined that the snoop of the bridge cache is completed and the transaction is transferred to the lower bus. If the arbitration of the lower bus is completed before the operation, the transaction to be transferred can be issued to the lower bus from the bus bridge at the same time when the transaction transfer is decided.
Even if the arbitration of the lower bus is not completed before it is decided to transfer the transaction to the lower bus, the timing of starting the arbitration is earlier than before, so the transaction issuance timing to the lower bus in any case. Will be faster than before. Therefore, according to the present embodiment, the processing time when a transaction is transferred from the upper bus to the lower bus can be shortened, so that the latency of the entire bus system can be reduced.

In this embodiment, when arbitration of the lower bus is started after the receipt of the transaction from the upper bus and before the completion of the cache snoop (that is, determination of transaction transfer / non-transfer), It is decided in consideration of the trade-off between the load condition of the bus and the request for shortening the transaction transfer processing time. For example, if the arbitration start timing is advanced, the transaction is issued to the lower bus earlier, but the time when the bus bridge unnecessarily occupies the lower bus when the arbitration ends before the snoop is completed. Will occur. Therefore, when the bus load of the lower bus is large, the start of arbitration is delayed in order to shorten or eliminate the time when the bus bridge unnecessarily occupies the lower bus.
On the contrary, when the bus load is small, the effect of shortening the processing time can be enhanced by advancing the arbitration start timing.

In the above example, the transaction transfer from the upper bus to the lower bus has been described as an example. However, in the case of the transaction transfer from the lower bus to the upper bus, the processing time can be shortened in the same manner as in the above example. You can

Next, a modification of the first embodiment will be described. In the first embodiment described above, when a transaction is issued to one bus, the bus bridge basically performs the preceding arbitration of the other bus, so that the request data of the transaction resulting from the snoop of the bridge cache is stored in the bridge cache. If so, the transaction is not transferred to the other bus and the preceding arbitration is wasted. This modification is a method for reducing such wasteful preceding arbitration.

In this method, the bus bridge determines the possibility of transferring the transaction to the other bus based on the type or address of the transaction issued to the one bus, and the transaction may be transferred. Only when it is determined to be high, the preceding arbitration to the other bus is performed.

As a method of determining the possibility of transaction transfer in the bus bridge, there are the following methods, for example.

First, when a transaction is transferred from the upper bus to the lower bus, the transfer possibility is determined based on the address of the transaction. This method is based on the following principle.

It is highly possible that the instruction code group representing a series of processing is stored in consecutive addresses on the main memory.
Therefore, when the CPU reads a new instruction code group, bridge cache mishits are likely to occur continuously. That is, in the case of reading a series of instruction code groups, the CPU sequentially issues a series of read transactions to a series of addresses in which the instruction code groups are stored (however, here, the CPU has its own cache). Since the address of the read transaction actually issued from the CPU is continuous in cache block units, if a miss hit occurs in the bridge cache for a certain transaction, the next transaction may miss hit. The nature is high. On the other hand, when the consecutive transactions are transactions for consecutive addresses in cache block units, the series of transactions is highly likely to be a series of instruction code groups. Therefore, according to the first method, the request address when the transaction is transferred from the upper bus to the lower bus is recorded in the bus bridge, and the address of the next transaction given to the bus bridge is recorded as the previously recorded address. It is determined whether or not the cache blocks are continuous, and if they are continuous, it is determined that a subsequent transaction is likely to be transferred to the lower bus.
In the first method, the address record of the transfer transaction in the bus bridge is updated every time the transfer is performed.

The second method of determining the possibility of transaction transfer is the method of determining the transfer possibility based on the type of transaction in the transaction transfer from the lower bus to the upper bus. Transactions issued on the bus include read (Read), invalidate (Invalidate), and read and invalidate (Read & Invalidate). Here, a read is a transaction issued when the CPU reads data that is not in its own cache, and an invalidate is a consistency with another cache when the CPU rewrites the data that it has. This is a transaction for invalidating the corresponding block in another cache in order to maintain The lead and invalidate is CP
This is a transaction issued when U writes data that is not in its own cache, and simultaneously instructs reading of a block containing the corresponding data and invalidation of the corresponding block in another cache. Among such transactions, transactions that instruct invalidation of other caches such as invalidate and read-and-invalidate are collectively referred to as invalidate transactions. In the second method, the type of transaction is determined by the bus bridge, and the possibility of transaction transfer is determined.

That is, in the second method, when the bus bridge receives a transaction issued to the lower bus, the type of the transaction is specified by the bus bridge, and the transaction is an invalidate type transaction. Is that the preceding arbitration is performed, and if the transaction is a non-invalidating type, the preceding arbitration is not performed. The reason why such a method is adopted is as follows.

When performing a data write (rewrite) operation for a certain address in a certain CPU, in order to maintain the cache consistency, the CP on the same upper bus is used.
CPU not only on U but also on bus bridges and other upper buses
Also, it is necessary to instruct invalidation of the corresponding block. In such a case, an invalidate transaction is issued to the lower bus from the bus bridge to which the CPU is connected. When an invalidate transaction is issued to the lower bus in this way, the bus bridge that received it determines that the cache cache state is M, E, or S, and the upper CPU of the bus bridge is the corresponding cache cache state. Since there is a possibility of having data, the bus bridge must issue an invalidate transaction to the upper bus.

On the other hand, the transaction issued to the lower bus is a non-invalidate system (eg, read).
In this case, maintaining the cache consistency is required only when the cache state of the bus bridge that received the transaction is M. In the non-invalidate transaction, the latest data needs to be read out only when the other CPU has the latest data (that is, the state M). Therefore, the transaction is transferred to the upper bus. There is a need.

Here, the possibility that the state of the block with the bridge cache is M is naturally lower than the possibility that it is M, E, or S. Moreover, the state becomes M when the data is rewritten,
It is unlikely that the block of instruction code will be M. Summarizing the above, it can be said that the possibility that the transaction of the lower bus is transferred to the upper bus is much higher in the invalidate system than in the non-invalidate system.

For the above reasons, in the second method, if the transaction issued to the lower bus is an invalidate type transaction, the invalidate type transaction must be issued to the upper level bus, that is, transferred. It is highly likely that it will not happen.

Although some examples of the method of determining the possibility of transaction transfer from the type or address of the transaction have been given above, the method of determining the possibility of transaction transfer is not limited to the above examples. Absent. In any case, any method may be used as long as the possibility of transaction transfer can be determined in a shorter time than the time required for cache snooping.

Then, the possibility that a transaction is transferred from one bus to the other bus is judged by such a judging method, and only when it is judged that the transfer possibility is high, the preceding arbitration is performed for the other bus. By performing the above, it is possible to reduce the number of useless preceding arbitrations.

The method for reducing useless preceding arbitration by determining whether or not to perform the preceding arbitration based on the transaction type and address has been described above. However, if the bus load of the bus of the transaction transfer destination is small, the throughput is not so much affected even if the wasteful preceding arbitration is performed. Therefore, the method of the modified example is not essential for implementing the first embodiment.

Embodiment 2 The second embodiment of the present invention aims to reduce the latency due to arbitration during split response when the upper bus is a split bus.

The reason why the split bus is adopted as the upper bus in the hierarchical bus system is to improve the throughput of the upper bus. That is, when a transaction is issued from the CPU to the upper bus, if the corresponding data does not exist in the bridge cache and the transaction is transferred to the lower bus, the upper bus waits for a response to the transaction from the lower bus. Remain occupied by the original CPU. In this case, other CPUs cannot issue transactions in the meantime, and the throughput of the upper bus becomes low. On the other hand, if the CPU is capable of splitting and the upper bus is configured as a split bus, when the transaction of the upper bus is transferred to the lower bus, the transaction can be split and the original CPU can relinquish the bus. It is possible to issue another transaction in the meantime. Therefore, in this case, the throughput of the upper bus is improved. CP that can handle splits in recent years
U has been developed and can be used to realize splitting of the upper bus.

When the transaction of the upper bus is split and transferred to the lower bus, the response from the lower bus to the transaction must be returned to the original CPU through the bus bridge. Bus bridge to original CPU
Such a response to is called a split response. When performing this split response, the bus bridge needs to perform arbitration to acquire the right to use the upper bus. This is because the original CPU has abandoned the right to use the upper bus when the split is performed.

The arbitration at the time of split response may be performed after the bus bridge receives a response from the lower bus to the transferred transaction, as shown in FIG. 2, for example, but this waits for the arbitration. The output timing of split response will be delayed by that much.

Therefore, in the present embodiment, when the bus bridge splits the transaction of the upper bus, the bus bridge does not wait for a response from the lower bus to the bus bridge, and the bus bridge arbitrates the upper bus after a predetermined time interval from the split time. To do.

FIG. 3 is an explanatory diagram showing the flow of processing at this time.
It is. In FIG. 3, with respect to the transaction issued to the upper bus, the process flow is the same as that of FIG. 1 up to the point where the lower bus arbitration is performed before the completion of the cache snoop of the bus bridge. However, in this embodiment, since the transaction is split, the bus bridge returns a response indicating the split to the original CPU when the transfer of the transaction is decided as a result of the snoop, which is the point of FIG. Different from the case. The original CPU that received this response
Abandon the upper bus and wait for the split response from the bus bridge.

In the lower bus, the transferred transaction is snooped to another bus bridge, and a response to the transaction is generated based on the result of this snoop. Then, the bus bridge that receives this response generates a split response and outputs it to the upper bus.

In this embodiment, in order to acquire the bus use right necessary for this split response, the upper bus is arbitrated without waiting for the response of the lower bus to be returned to the bus bridge. In other words, in the present embodiment, the upper bus arbitration for split response is not started with the response from the lower bus as a trigger, but a predetermined time from the time when the bus bridge determines split transfer of the transaction as a result of cache snoop. Start after the interval. In the present embodiment, starting the upper bus arbitration for the split response without waiting for the response from the lower bus is called the preceding arbitration.

This time interval is set so that the upper bus arbitration starts at least earlier than the response from the lower bus. The smaller the time interval is, the earlier the completion timing of the upper bus arbitration is. Therefore, the timing of issuing the split response from the bus bridge can be advanced. However,
If this time interval is set too small, the bus bridge will wastefully occupy the upper bus, so consider the time required from split transfer to the lower bus to the response and the time required for arbitration of the upper bus. Set an optimal time interval.

During the predetermined time interval from the split transfer to the start of upper bus arbitration, each CP is
U can issue another transaction to the upper bus.

As described above, according to this embodiment, the completion timing of the upper bus arbitration for the split response can be accelerated, so that the issuance timing of the split response can be accelerated, and the CPU first executes the transaction. It is possible to shorten the time required for the entire series of transaction processing from the issuance of the statement to the completion of the split response.

In the second embodiment, if the predetermined time interval is changed according to the type of transaction issued to the lower bus as a result of split transfer,
The leading arbitration can be performed more efficiently. In other words, the time required for snooping the lower bus generally differs depending on the transaction type.Therefore, by changing the start time of the upper bus arbitration according to the time required for the lower bus snoop, the upper bus arbitration can be performed at the optimum timing for each transaction type. It becomes possible to execute.

As described in the modification of the first embodiment,
The possibility that a transaction on the lower bus is transferred to the upper bus is higher in the invalidate system than in the non-invalidate system. Therefore, when the transaction issued to the lower bus as a result of the split transfer is an invalidate system, there is a high possibility that another bus bridge will issue the transaction to the upper bus. Therefore, in the case of an invalidate transaction, the result of snoop of the lower bus is not determined until the processing in the upper bus of the other bridge is completed, so the time required for the lower bus snoop in FIG. 3 is shorter than that of the non-invalidate transaction. Tend to be long.

Therefore, as the value of the predetermined time interval from the split transfer to the start of the upper bus arbitration, different values are set for the invalidating transaction and the non-invalidating transaction, and the value for the invalidating transaction is set. By making the value larger than the value for the non-invalidate system, arbitration can be performed at an appropriate timing according to each transaction type. In this case, the bus bridge always detects the type of transaction to be split-transferred to the lower bus.

The first and second embodiments of the hierarchical bus control system according to the present invention have been described above. However, if the respective systems described above are switched by configuration control from software, a flexible hierarchical bus can be obtained. System configuration becomes possible. That is, the method of each of the above-described embodiments is specifically realized as a function of a bus bridge. However, when the bus bridge is configured, the means for the plurality of preceding arbitration methods described above is incorporated, and each of these methods is implemented. And the mode for prohibiting the preceding arbitration is switched by the configuration control. According to such switching,
For example, one bus bridge always performs leading arbitration for both upper and lower buses, another bus bridge performs leading arbitration based on transaction address for lower buses, and does not perform leading arbitration for upper buses. The optimum preceding arbitration method can be executed for each bus bridge.

In this switching method, the mode in which the preceding arbitration is prohibited can be switched in order to prevent a decrease in throughput due to useless preceding arbitration.

The prohibition mode is selected based on, for example, the prediction of the bus load. That is, for the upper bus, the prohibit mode is selected when, for example, T _CPU × (number of CPUs)> threshold. Here, T _CPU is the CPU bus occupancy rate (CPU bus occupancy time per unit time), and this value can be predicted from the CPU performance. The number of CPUs is the number of CPUs connected to the upper bus of the bus bridge itself.

For the lower bus, the prohibit mode is selected when, for example, T _CPU × (number of CPUs) + T _{I / O} × (number of I / Os)> threshold. Here, T _{I / O} is the bus occupation rate of the I / O device (bus occupation time of the I / O device per unit time), and this value can be predicted from the performance of the I / O device. The number of CPUs, I /
The O number is the number for the entire hierarchical bus system.

As described above, by prohibiting the preceding arbitration for the bus whose bus load is expected to increase for each bus bridge, the throughput and latency can be optimized according to the configuration of the bus system.

It is also possible to monitor the bus loads of the upper bus and the lower bus by the bus bridge and dynamically switch the permission / prohibition of the preceding arbitration based on the monitoring result. That is, the bus bridge is provided with a configuration for monitoring the bus load, and the preceding arbitration is prohibited when the bus load of each bus exceeds a predetermined threshold value. Here, the bus load is obtained, for example, from the number of bus requests generated during a certain period. According to this dynamic preceding arbitration control, it is possible to prevent the throughput of the hierarchical bus system from decreasing.

Embodiment 3. FIG. 4 shows a third embodiment of the present invention.
3 is a block diagram showing a main configuration of a bus bridge according to FIG. The actual bus bridge contains various circuits,
FIG. 4 shows only the configuration related to the preceding arbitration. Note that FIG. 4 shows only the processing system for transactions from the upper bus.

In this example, the address is specified by 32 bits, the upper 12 bits of which are used as a tag (Tag), the next 15 bits are used as an index (Index), and the lower 5 bits are used as an offset (Offset). Has become. That is, in this example, the address space of 4 Gbytes and the bridge cache are 1 cache block = 32
It is mapped in bytes, and the bridge cache has a capacity of 10 ¹⁵ blocks or 1 Mbytes. The bridge cache is composed of a cache RAM that stores 1 Mbytes of data, and a tag RAM that stores the address of the data stored in each block of the cache RAM in the form of a correspondence between an index and a tag. However, in FIG. 4, only the tag RAM is shown. Since the bridge cache has such a large capacity, it is formed as a chip separate from the bus bridge body.

The structure shown in FIG. 4 is composed of a structure for normal cache search (snoop) and a structure for preceding arbitration.

The normal cache snoop is composed of a tag read circuit 32, a tag RAM 50 and a mishit determination circuit 38.
Done by That is, when the transaction of the upper bus is input to the bus bridge 30, the index portion of the address of the transaction is input to the tag read circuit 32. The tag read circuit 32 is a tag RAM
From 50, the tag corresponding to this index is read. The tag output from the tag RAM 50 is compared with the tag of the actual address in the mishit determination circuit 38.
If the two match, the requested data for the transaction exists in the cache RAM. In this case, the bus bridge reads the desired data from the cache RAM via a cache controller (not shown), and sends the request data via the host bus. Return to CPU. In this case, no transaction is transferred to the lower bus. On the other hand, if the two do not match, the mishit determination circuit 3
8 outputs a mishit signal, and this mishit signal is input to the arbitration circuit 44 via the OR circuit 42. In this case, the arbitration circuit 44 issues an arbitration signal to the lower bus to arbitrate the lower bus. Then, the transaction to be transferred is issued to the lower bus.

The above is the flow of the normal cache snoop. However, since the bridge cache has a large capacity and is configured as a separate chip from the bus bridge 30 in this embodiment, it takes a relatively long time to search the tag RAM 50. Requires.

On the other hand, the structure for the preceding arbitration comprises a compression tag table 34, a tag compression circuit 36 and a mishit determination circuit 40. The compression tag table 34 stores information obtained by compressing the correspondence information between the index and the tags stored in the tag RAM 50. That is, the compression tag table 34 stores a value (called a compression tag) obtained by compressing a corresponding tag by a predetermined data compression method for each index. As the data compression method, for example, a method such as exclusive OR of all bits of the tag is used. The compression tag table 34 is the tag RAM 5
Since the size is much smaller than 0, it can be mounted in the chip of the bus bridge 30 and high-speed access is possible. When the index of the address of the transaction is given, the compression tag table 34 outputs the compression tag corresponding to the index.
On the other hand, the tag compression circuit 36 compresses the transaction address tag by the same data compression method as the compression tag table 34.

The mishit determination circuit 40 compares the output of the compression tag table 34 with the output of the tag compression circuit 36. Here, if the compressed tags do not match, the original tags also always do not match. Therefore, if the comparison result in the mishit determination circuit 40 does not match, the transaction is always transferred to the lower bus. Therefore, the mishit determination circuit 40 instructs the arbitration circuit 44 to arbitrate the lower bus by outputting a mishit signal when the values of both inputs do not match. This mishit signal is the OR circuit 4
It is input to the arbitration circuit 44 via 2.

Since the search of the compressed tag table 34 is shorter than the search of the tag RAM 50, the mishit signal of the mishit determination circuit 40 is output earlier than the mishit signal of the mishit determination circuit 38. . Therefore, according to this configuration, it is possible to detect in advance the case where the transaction transfer reliably occurs by comparing the compression tags with each other, so that the preceding arbitration of the lower bus can be started before the completion of the cache snoop.

In the configuration of FIG. 4, when the mishit signal is output from the mishit determination circuit 40, transaction transfer always occurs, so that useless preceding arbitration does not occur.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining prior arbitration for transaction transfer according to a first embodiment.

FIG. 2 is a diagram for explaining prior arbitration for split response.

FIG. 3 is a diagram for explaining prior arbitration for split response according to the second embodiment.

FIG. 4 is a block diagram showing a main configuration of a bus bridge according to a third embodiment.

FIG. 5 is an explanatory diagram showing a configuration of a hierarchical bus system.

FIG. 6 is a diagram for explaining a conventional transaction transfer process from an upper bus to a lower bus.

[Explanation of symbols]

10 CPU, 12 upper bus, 14 bus bridge,
16 cache, 18 lower bus, 20 main memory, 22 I / O device.

Claims (10)

[Claims] 1. A plurality of processors are connected to a host bus,
In a hierarchical bus system in which a bus bridge having a cache is provided for each of a plurality of upper buses, each upper bus is connected to a lower bus via each bus bridge, and the lower bus is connected to a main memory, the bus bridge When a transaction is issued to either the upper bus or the lower bus, the arbitration of the other bus is preceded before the cache is snooped and the transaction is transferred to the other bus. A hierarchical bus control method characterized by performing. 2. The hierarchical bus control method according to claim 1, wherein the bus bridge determines the possibility of transferring the transaction to the other bus based on the type or address of the transaction issued to the one bus. Then
A hierarchical bus control method, wherein the preceding arbitration to the other bus is performed only when it is determined that a transaction is likely to be transferred. 3. The hierarchical bus control method according to claim 2, wherein the bus bridge stores the address of the transaction when the transaction is transferred from the upper bus to the lower bus, and the stored address is stored after the transaction. A hierarchical bus characterized in that when a transaction for an address in a cache block consecutive to a cache block containing an address is issued to an upper bus, it is determined that the latter transaction is likely to be transferred to a lower bus. control method. 4. The hierarchical bus control method according to claim 2, wherein the bus bridge invalidates (In) the lower bus.
validate) transaction is issued, it is determined that the transaction is highly likely to be transferred to the upper bus. Hierarchical bus control method. 5. A plurality of processors capable of splitting are connected to an upper bus, a bus bridge having a cache is provided for each of the plurality of upper buses, and each upper bus is connected to a lower bus via each bus bridge. In the hierarchical bus system in which the lower bus is connected to the main memory, when the bus bridge splits the transaction of the upper bus and transfers it to the lower bus, the response from the lower bus to the transferred transaction is transmitted. Arbitration for the higher-order bus is performed after a predetermined time interval from the transfer processing without waiting. 6. The hierarchical bus control method according to claim 5, wherein the bus bridge detects the type of transaction transferred from the upper bus to the lower bus, and the detection result is an invalidate system. In the hierarchical bus control method, the time interval until the arbitration of the higher-order bus is made larger than when the detection result is a non-invalidate system. 7. The hierarchical bus control method according to claim 1, wherein if the total bus occupancy of the processors connected to the bus bridge exceeds a predetermined threshold value, the upper bus A hierarchical bus control method, wherein the preceding arbitration is prohibited. 8. The hierarchical bus control method according to claim 1, wherein the sum of bus occupancy rates of processors and I / O devices included in the hierarchical bus system exceeds a predetermined threshold value. A hierarchical bus control method, wherein the preceding arbitration for the lower bus is prohibited. 9. The hierarchical bus control method according to claim 1, wherein the bus bridge monitors a bus load of each of an upper bus and a lower bus connected to the bus bridge, and A hierarchical bus control method, wherein when the bus load exceeds a predetermined threshold value, the preceding arbitration is prohibited for the bus exceeding the threshold value. 10. A bus bridge that connects an upper bus to which a plurality of processors are connected and a lower bus to which a main memory is connected, and includes a tag memory storing tag information and a cache memory storing data. Connected to the cache unit, the tag memory is searched from the index included in the address of the transaction issued to one of the buses, and the tag obtained as a result of the search does not match the tag included in the transaction address. In the case of determining that the transaction address is not included in the cache memory in the case, in the bus bridge that transfers the transaction to the other bus, a compressed tag memory that stores a table in which the information in the tag memory is compressed by a predetermined method, Transaction issued to one of the buses Tag compression means for extracting a tag from an address and compressing it in the predetermined method, and extracting an index from an address of a transaction issued to the one bus, and compressing tag information corresponding to the index to the compression tag memory. Compression tag detection means for reading from the output, and comparison means for comparing the output of the tag compression means and the output of the compression tag detection means, and the comparison result by the comparison means, the output of the tag compression means and the A bus bridge which outputs an arbitration signal to the other bus without waiting for the end of the search of the tag memory when the output of the compressed tag detection means does not match.