JPH0634201U - Stacked thermistor - Google Patents

Stacked thermistor

Info

Publication number
JPH0634201U
JPH0634201U JP7367092U JP7367092U JPH0634201U JP H0634201 U JPH0634201 U JP H0634201U JP 7367092 U JP7367092 U JP 7367092U JP 7367092 U JP7367092 U JP 7367092U JP H0634201 U JPH0634201 U JP H0634201U
Authority
JP
Japan
Prior art keywords
thermistor
electrodes
internal electrodes
internal
pair
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP7367092U
Other languages
Japanese (ja)
Inventor
和彦 大山
信幸 西村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiyo Yuden Co Ltd
Original Assignee
Taiyo Yuden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiyo Yuden Co Ltd filed Critical Taiyo Yuden Co Ltd
Priority to JP7367092U priority Critical patent/JPH0634201U/en
Publication of JPH0634201U publication Critical patent/JPH0634201U/en
Withdrawn legal-status Critical Current

Links

Abstract

(57)【要約】 【目的】 積層型サーミスタの抵抗を下げ且つ抵抗値の
バラツキを抑える。 【構成】 抵抗体1の中のP1 、P2 、P3 を通る各仮
想平面に一対の内部電極2〜7をそれぞれ設ける。一方
の側の内部電極2、4、6を第1の外部電極8に接続
し、他方の側の内部電極3、5、7を第2の外部電極9
に接続する。抵抗体1の上面に対して垂直な方向から見
て一方の側の内部電極2、4、6と他方の側の内部電極
3、5、7とが重ならないように構成する。
(57) [Summary] [Purpose] To reduce the resistance of the laminated thermistor and suppress variations in resistance. [Structure] A pair of internal electrodes 2 to 7 is provided on each virtual plane passing through P1, P2, and P3 in the resistor 1. The inner electrodes 2, 4, 6 on one side are connected to the first outer electrode 8, and the inner electrodes 3, 5, 7 on the other side are connected to the second outer electrode 9.
Connect to. The internal electrodes 2, 4, 6 on one side and the internal electrodes 3, 5, 7 on the other side do not overlap with each other when viewed from the direction perpendicular to the upper surface of the resistor 1.

Description

【考案の詳細な説明】[Detailed description of the device]

【0001】[0001]

【産業上の利用分野】[Industrial applications]

本考案は、電子機器の温度補償、電流制御、温度検出などに使用するための積 層型サーミスタに関する。 The present invention relates to a laminated thermistor for use in temperature compensation, current control, temperature detection, etc. of electronic devices.

【0002】[0002]

【従来の技術】[Prior art]

典型的なサーミスタは、角柱あるいは板状のサーミスタ抵抗体と、この両端に 浸漬法等で形成された一対の電極とから成る。この種のサーミスタは構造が簡単 であるために安価に製造できるという長所を有する半面、一対の電極の相互間隔 を所定値にすることに困難を伴うので、抵抗値にバラツキが生じるという欠点を 有する。また、このサーミスタでは所定の耐圧を確保して低い抵抗値を得ること に困難を伴う。 A typical thermistor is composed of a prismatic or plate-shaped thermistor resistor and a pair of electrodes formed at both ends by a dipping method or the like. This type of thermistor has the advantage that it can be manufactured at low cost due to its simple structure, but on the other hand, it is difficult to set the mutual distance between a pair of electrodes to a predetermined value, and therefore it has the drawback that the resistance value varies. . Further, it is difficult for this thermistor to secure a predetermined breakdown voltage and obtain a low resistance value.

【0003】 上述のような問題を解決するために、図5に示すように、サーミスタ抵抗体1 0の中に第1及び第2の内部電極11、12を配置し、これ等を第1及び第2の 外部電極13、14に接続して積層セラミックコンデンサと同様な積層構造にす ることが例えば特公昭50−11585号公報で知られている。このように構成 すれば第1及び第2の内部電極11、12の対向面積が大きくなり、また積層枚 数を増やせば複数の内部電極の並列接続されるために初期抵抗値(25℃の抵抗 値)及び一般にB定数と呼ばれているサーミスタ定数を小さくすることができる 。In order to solve the above-mentioned problem, as shown in FIG. 5, first and second internal electrodes 11 and 12 are arranged in the thermistor resistor 10, and the first and second internal electrodes 11 and 12 are arranged in the thermistor resistor 10. It is known, for example, from Japanese Patent Publication No. 50-11585 to connect to the second external electrodes 13 and 14 to form a laminated structure similar to a laminated ceramic capacitor. With this configuration, the facing area of the first and second internal electrodes 11 and 12 becomes large, and when the number of laminated layers is increased, a plurality of internal electrodes are connected in parallel, so that the initial resistance value (resistance at 25 ° C. Value) and the thermistor constant generally called B constant can be reduced.

【0004】[0004]

【考案が解決しようとする課題】[Problems to be solved by the device]

ところが、積層構造を採用すると、第1の内部電極11と第2の内部電極12 とのパターンずれが生じやすくなり、両者の対向面積が変化すれば抵抗値の変化 が生じる。すなわち、設計通りの抵抗値を有するサーミスタを得ることが困難で ある。 また、積層構造にすれば低抵抗化を容易に図ることができるが、積層枚数が一 層増えるごとの抵抗減少率が大きくなり過ぎる。従って、内部電極のパターンの 変更をしないで積層枚数のみを変更して抵抗値を変更しようとすると、目標の抵 抗値のサーミスタを得ることが困難になる。 However, when the laminated structure is adopted, the pattern shift between the first internal electrode 11 and the second internal electrode 12 is likely to occur, and the resistance value changes when the facing area of the two changes. That is, it is difficult to obtain a thermistor having a resistance value as designed. Further, if the laminated structure is used, it is possible to easily reduce the resistance, but the resistance decrease rate becomes too large as the number of laminated layers increases. Therefore, if the resistance value is changed by changing only the number of stacked layers without changing the internal electrode pattern, it becomes difficult to obtain a thermistor having a target resistance value.

【0005】 そこで、本考案は抵抗値のバラツキを小さくすることができ、且つ目標とする 抵抗値を容易に得ることができる積層型サーミスタを提供することを目的とする 。Therefore, an object of the present invention is to provide a laminated thermistor capable of reducing the variation in resistance value and easily obtaining a target resistance value.

【0006】[0006]

【課題を解決するための手段】[Means for Solving the Problems]

上記目的を達成するための本考案は、温度変化に応じて抵抗値が変化する抵抗 材料から成るサーミスタ抵抗体と、前記抵抗体の中の互いに平行な複数の仮想平 面にそれぞれ配置された一対の内部電極と、前記抵抗体の両側面に設けられた第 1及び第2の外部電極とから成り、前記一対の内部電極の一方は前記第1の外部 電極に接続され、前記一対の内部電極の他方は前記第2の外部電極に接続され、 前記一方の内部電極と前記他方の内部電極とは前記仮想平面に対して垂直な方向 から見て互いに重ならないように配置されている積層型サーミスタに係わるもの である。 In order to achieve the above object, the present invention provides a thermistor resistor made of a resistance material whose resistance value changes in response to temperature changes, and a pair of thermistor resistors arranged on a plurality of parallel virtual planes in the resistor. Internal electrodes and first and second external electrodes provided on both side surfaces of the resistor, one of the pair of internal electrodes being connected to the first external electrode, and the pair of internal electrodes. The other is connected to the second external electrode, and the one internal electrode and the other internal electrode are arranged so as not to overlap each other when viewed from a direction perpendicular to the virtual plane. It is related to.

【0007】[0007]

【考案の作用及び効果】[Operation and effect of the device]

本考案においてはサーミスタの抵抗値が同一仮想平面上に配置された一対の内 部電極の間隔によって決まるので、抵抗値のバラツキが少なくなる。即ち、同一 仮想平面上の一対の内部電極は同時に形成されるので、これ等の相互間隔は積層 のずれに無関係であり、抵抗値のバラツキが小さくなる。 また、同一仮想平面上の一対の内部電極間の抵抗値を小さくすることができる ので、積層枚数の変更による全体の抵抗値変化を小さくすることができ、種々の 抵抗値のサーミスタを容易に得ることができる。即ち、内部電極のパターンを変 更しないで積層枚数を変えることによって種々の抵抗値のサーミスタを得ること ができる。 In the present invention, since the resistance value of the thermistor is determined by the distance between the pair of inner electrodes arranged on the same virtual plane, the variation in resistance value is reduced. That is, since a pair of internal electrodes on the same virtual plane are formed at the same time, the mutual spacing between them is irrelevant to the stacking deviation, and the variation in the resistance value is reduced. Also, since the resistance value between a pair of internal electrodes on the same virtual plane can be reduced, the change in the overall resistance value due to the change in the number of laminated layers can be reduced, and thermistors with various resistance values can be easily obtained. be able to. That is, thermistors having various resistance values can be obtained by changing the number of laminated layers without changing the pattern of the internal electrodes.

【0008】[0008]

【実施例】【Example】

次に、図1〜図4を参照して本考案の実施例に係わる積層型NTCサーミスタ を説明する。 図1に示すサーミスタは、NTCサーミスタ材料から成る抵抗体1と、第1、 第2、第3、第4、第5及び第6の内部電極2、3、4、5、6、7と、第1及 び第2の外部電極8、9とから成る。第1及び第2の内部電極2、3は直方体形 状の抵抗体1の上面に平行であり且つこの厚み方向の第1の位置P1 を通る第1 の仮想平面上に図3に示すパターンに形成されたAg−Pd導体層から成り、こ れ等の一端は距離Lを有して互いに離間している。第3及び第4の内部電極4、 5はP2 を通る第2の仮想平面に図3と同様なパターンにAg−Pd導体層で形 成されている。第5及び第6の内部電極6、7はP3 を通る第3の仮想平面に図 3と同様なパターンにAg−Pd導体層で形成されている。なお、P1 、P2 、 P3 を通る第1、第2及び第3の仮想平面は互いに平行である。 Next, a laminated NTC thermistor according to an embodiment of the present invention will be described with reference to FIGS. The thermistor shown in FIG. 1 comprises a resistor 1 made of an NTC thermistor material, first, second, third, fourth, fifth and sixth internal electrodes 2, 3, 4, 5, 6, 7; It is composed of first and second external electrodes 8 and 9. The first and second internal electrodes 2 and 3 are parallel to the upper surface of the rectangular parallelepiped-shaped resistor 1 and on the first imaginary plane passing through the first position P1 in the thickness direction to form the pattern shown in FIG. The formed Ag-Pd conductor layers are formed, and one ends of these are separated from each other with a distance L. The third and fourth internal electrodes 4, 5 are formed of Ag-Pd conductor layers in a pattern similar to that shown in FIG. 3 on a second virtual plane passing through P2. The fifth and sixth internal electrodes 6, 7 are formed of Ag-Pd conductor layers in a pattern similar to that of FIG. 3 on a third virtual plane passing through P3. The first, second and third virtual planes passing through P1, P2 and P3 are parallel to each other.

【0009】 図1において左側に配置された第1、第3及び第4の内部電極2、4、6は一 方の側面に露出し、Ag−Pd導体層から成る第1の外部電極8に接続されてい る。図1において、右側に配置された第2、第4及び第6の内部電極3、5、7 は他方の側面に露出し、Ag−Pd導体層から成る第2の外部電極9に接続され ている。The first, third, and fourth inner electrodes 2, 4, 6 arranged on the left side in FIG. 1 are exposed on one side surface, and are formed on the first outer electrode 8 made of an Ag—Pd conductor layer. It is connected. In FIG. 1, the second, fourth, and sixth inner electrodes 3, 5, 7 arranged on the right side are exposed on the other side surface and connected to the second outer electrode 9 composed of an Ag-Pd conductor layer. There is.

【0010】 次に、図4を参照してサーミスタの製造方法を説明する。 まず、所定量の酸化マンガン及び酸化コバルトに原子価制御剤及び焼結助剤を 加え、湿式ボールミルにて攪拌の後に脱水、乾燥を行い、仮焼きをし、再度湿式 ボールミルにて攪拌の後に脱水、乾燥を行なって、セラミック・NTCサーミス タ材料の粉体を得た。次に、この粉体に所定量のポリビニルブチラール系の有機 バインダーと可塑剤とトルエン系溶媒を加え湿式ボールミルにて攪拌し、脱胞し てスラリーを得た。次に、このスラリーを使用してドクターブレード法で厚さ5 0μmのグリーンシート(未焼成セラミックシート)を複数枚形成した。図4に 示すようにグリーンシート1a〜1dは1枚から多数のサーミスタを得ることが できるように大面積に形成されている。次に、第1、第2及び第3のグリーンシ ート1a、1b、1cに第1〜第6の内部電極2〜7を得るための導体層2a〜 7aをAg−Pdペーストのスクリーン印刷によって形成した。次に、第1、第 2、第3及び第4のグリーンシート1a、1b、1c、1dを図4に示す順に積 層し、圧着し、しかる後、図4で破線で示す位置をカットしてサーミスタの成形 体を得、脱バインダーのために成形体を大気中で400℃、2時間加熱し、しか る後、大気中で1100℃、2時間焼成して図1及び図2に示す抵抗体1を得た 。最後に、抵抗体1の両側面にAg−Pdペーストを塗布して焼付けることによ って第1及び第2の外部電極8、9を形成した。Next, a method of manufacturing the thermistor will be described with reference to FIG. First, a valence control agent and a sintering aid are added to a predetermined amount of manganese oxide and cobalt oxide, stirred in a wet ball mill, dehydrated and dried, calcined, and again stirred in a wet ball mill and dehydrated. Then, it was dried to obtain a powder of ceramic / NTC thermistor material. Next, a predetermined amount of a polyvinyl butyral-based organic binder, a plasticizer, and a toluene-based solvent were added to this powder, and the mixture was stirred with a wet ball mill to remove the cells to obtain a slurry. Next, using this slurry, a plurality of green sheets (unfired ceramic sheets) having a thickness of 50 μm were formed by a doctor blade method. As shown in FIG. 4, the green sheets 1a to 1d are formed in a large area so that a large number of thermistors can be obtained from one sheet. Next, conductor layers 2a to 7a for obtaining the first to sixth internal electrodes 2 to 7 are screen-printed with Ag-Pd paste on the first, second and third green sheets 1a, 1b and 1c. Formed by. Next, the first, second, third, and fourth green sheets 1a, 1b, 1c, and 1d are laminated in the order shown in FIG. 4 and pressure-bonded, and then the position shown by the broken line in FIG. 4 is cut. To obtain a thermistor compact, and to remove the binder, the compact is heated in air at 400 ° C for 2 hours, and then fired in air at 1100 ° C for 2 hours to obtain the resistance shown in Figs. 1 and 2. I got body 1. Finally, the first and second external electrodes 8 and 9 were formed by applying and baking an Ag-Pd paste on both side surfaces of the resistor 1.

【0011】 この実施例の積層型サーミスタにおいては、第1の外部電極8に接続された第 1、第3及び第5の内部電極2、4、6と第2の外部電極9に接続された第2、 第4及び第6の内部電極3、5、7とが仮想平面に対して垂直な方向から見て重 なっていない。従って、積層時に置けるパターンずれによる抵抗値変化が生じな い。In the laminated thermistor of this embodiment, the first, third and fifth inner electrodes 2, 4, 6 connected to the first outer electrode 8 and the second outer electrode 9 were connected. The second, fourth, and sixth internal electrodes 3, 5, and 7 do not overlap with each other when viewed in a direction perpendicular to the virtual plane. Therefore, the resistance value does not change due to the pattern shift that can be placed during stacking.

【0012】[0012]

【変形例】[Modification]

本考案は上述の実施例に限定されるものでなく、例えば次の変形が可能なもの である。 (1) 第5及び第6の内部電極6、7を有する層を省いた構成にすること、 又は第1〜第6の内部電極2〜7と同様に内部電極を設けた層を増やすことがで きる。 (2) 図4では上側に1枚のカバー用グリーンシート1dを配置したが、更 に多くのカバー用グリーンシートを上及び下に配置することができる。 (3) 第1及び第2の外部電極8、9を焼成後に形成せずに、焼成前に成形 体に対して導体ペーストを塗布し、内部電極と外部電極とを同時に形成すること ができる。また、第1及び第2の外部電極8、9をメッキ法、浸漬法等で形成す ることもできる。 The present invention is not limited to the above-mentioned embodiments, and the following modifications are possible, for example. (1) The structure having the layers having the fifth and sixth internal electrodes 6 and 7 may be omitted, or the number of layers having the internal electrodes may be increased similarly to the first to sixth internal electrodes 2 to 7. it can. (2) In FIG. 4, one cover green sheet 1d is arranged on the upper side, but more cover green sheets can be arranged on the upper and lower sides. (3) Without forming the first and second external electrodes 8 and 9 after firing, the conductor paste can be applied to the molded body before firing to form the internal electrodes and the external electrodes at the same time. Also, the first and second external electrodes 8 and 9 can be formed by a plating method, a dipping method, or the like.

【図面の簡単な説明】[Brief description of drawings]

【図1】本考案の実施例の積層型サーミスタを示す中央
縦断面図である。
FIG. 1 is a central longitudinal sectional view showing a laminated thermistor according to an embodiment of the present invention.

【図2】図1のサーミスタの斜視図である。FIG. 2 is a perspective view of the thermistor of FIG.

【図3】図1のP1 位置における電極パターンを示す平
面図である。
3 is a plan view showing an electrode pattern at a position P1 in FIG. 1. FIG.

【図4】図1のサーミスタの製造方法を示す図である。FIG. 4 is a diagram showing a method of manufacturing the thermistor of FIG.

【図5】従来の積層型サーミスタを示す断面図である。FIG. 5 is a cross-sectional view showing a conventional laminated thermistor.

【符号の説明】[Explanation of symbols]

1 抵抗体 2〜7 内部電極 8,9 外部電極 1 Resistor 2-7 Internal electrode 8,9 External electrode

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 【請求項1】 温度変化に応じて抵抗値が変化する抵抗
材料から成るサーミスタ抵抗体と、 前記抵抗体の中の互いに平行な複数の仮想平面にそれぞ
れ配置された一対の内部電極と、 前記抵抗体の両側面に設けられた第1及び第2の外部電
極と、 から成り、前記一対の内部電極の一方は前記第1の外部
電極に接続され、前記一対の内部電極の他方は前記第2
の外部電極に接続され、前記一方の内部電極と前記他方
の内部電極とは前記仮想平面に対して垂直な方向から見
て互いに重ならないように配置されていることを特徴と
する積層型サーミスタ。
1. A thermistor resistor made of a resistance material whose resistance value changes according to temperature change, a pair of internal electrodes respectively arranged on a plurality of virtual planes parallel to each other in the resistor, and the resistance. First and second external electrodes provided on both side surfaces of the body, and one of the pair of internal electrodes is connected to the first external electrode, and the other of the pair of internal electrodes is the second external electrode.
Connected to external electrodes of the above, and the one internal electrode and the other internal electrode are arranged so as not to overlap each other when viewed in a direction perpendicular to the virtual plane.
JP7367092U 1992-09-29 1992-09-29 Stacked thermistor Withdrawn JPH0634201U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7367092U JPH0634201U (en) 1992-09-29 1992-09-29 Stacked thermistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7367092U JPH0634201U (en) 1992-09-29 1992-09-29 Stacked thermistor

Publications (1)

Publication Number Publication Date
JPH0634201U true JPH0634201U (en) 1994-05-06

Family

ID=13524912

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7367092U Withdrawn JPH0634201U (en) 1992-09-29 1992-09-29 Stacked thermistor

Country Status (1)

Country Link
JP (1) JPH0634201U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100342305B1 (en) * 1999-10-26 2002-06-27 유니썸테크놀로지 주식회사 Laminated NTC infrared detector and fabricating method therefor
DE19904727B4 (en) * 1998-02-10 2007-07-19 Murata Mfg. Co., Ltd., Nagaokakyo Resistance elements and methods of making same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19904727B4 (en) * 1998-02-10 2007-07-19 Murata Mfg. Co., Ltd., Nagaokakyo Resistance elements and methods of making same
DE19964532B4 (en) * 1998-02-10 2010-07-08 Murata Manufacturing Co., Ltd., Nagaokakyo Resistance elements and methods of making same
KR100342305B1 (en) * 1999-10-26 2002-06-27 유니썸테크놀로지 주식회사 Laminated NTC infrared detector and fabricating method therefor

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Effective date: 19970306