JPH0727140U - Multilayer chip capacitor - Google Patents

Abstract

(57) [Summary] (Modified) [Configuration] Two or more internal electrodes 12, 13 are formed on the same surface of the dielectric substrate 11 such that their end faces 12a, 13a face each other. Laminated body 14
Is formed, and external electrodes 15 and 16 to which one ends 12b and 13b of the internal electrodes 12 and 13 are connected are formed on both ends of the multilayer chip capacitor. [Effect] End surfaces 12 a of the internal electrodes 12, 13 facing each other,
A capacitor can be formed by 13a, a high Q value can be obtained, and it is possible to easily cope with a high frequency region. Further, it is possible to structurally increase the Q value in a high frequency region, it is not necessary to use a ceramic material having a high Q value for the dielectric substrate 11, and the laminated body 14 is made of a low temperature sintering material having a relatively low Q value. It can be formed, and a low resistance metal can be used for the internal electrodes 12 and 13. Further, the ESR in the high frequency region can be reduced. Also, the self-resonant frequency can be shifted to the high frequency side.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a multilayer chip capacitor, and more specifically to a multilayer chip having a small capacity and excellent in high frequency characteristics, which can be effectively used in various electronic devices such as mobile communication devices and cordless phones, which are used particularly in a high frequency region. Regarding capacitors.

[0002]

[Prior art]

 In recent years, with the miniaturization and multi-functionalization of various electronic devices such as TVs and VTRs, capacitors widely used in these electronic devices are also required to have smaller size, larger capacity and higher Q value. ing.

A multilayer chip capacitor is known as a capacitor whose size is reduced and whose capacity is increased.

FIG. 9 is a partially sectional perspective view showing an example of a conventional multilayer chip capacitor, and reference numeral 21 in the figure shows a dielectric substrate. Between the laminated dielectric substrates 21, an internal electrode 22 formed on almost one surface excluding the left end and an internal electrode 23 formed on almost one surface excluding the right end are formed every other layer. The body substrate 21, the internal electrodes 22, and the internal electrodes 23 form a laminated body 24. Further, an external electrode 25 to which one end of the internal electrode 22 is connected and an external electrode 26 to which one end of the internal electrode 23 is connected are formed at both ends of the laminated body 24, and the laminated body 24 and the external electrode are formed. The multilayer chip capacitor 20 is configured to include 25 and the external electrode 26.

The circuit configuration of the multilayer chip capacitor 20 thus configured can be represented by the equivalent circuit shown in FIG. Therefore, the total capacitance value of the multilayer chip capacitor 20 is the sum of the capacitance values C ₁ , C ₂ , C ₃ , C ₄ , C ₅ formed between the facing laminated surfaces of the internal electrode 22 and the internal electrode 23. Even if it is small, a large capacity can be obtained.

[0006]

[Problems to be solved by the device]

 By the way, in recent years, there has been a rapid increase in the number of electronic devices used in the high frequency range of several 100 MHz to several GHz such as mobile communication devices such as car phones and mobile phones, BS tuners and cordless phones. The capacitors used are required to have a small capacity and a high Q value.

However, the above-described conventional multilayer chip capacitor 20 has a problem that it cannot be used because the Q value becomes low in a high frequency region.

In order to solve such a problem, it is necessary to use a dielectric material having a high Q value for the dielectric substrate 21 and a low resistance metal for the internal electrodes 22, 23 and the external electrodes 25, 26. . MgTiO ₃ —CaTiO ₃ system and Ba (Mg _1/3 Ta _2/3 ) O ₃ system ceramics are known as dielectric materials having a high Q value, and these ceramics have a temperature range of 1400 ° C. to 1600 ° C. A high Q value can be obtained by sintering at a high temperature. The low resistance metals include Ag, Au, Cu, etc., but the melting points of these metals (Ag; 961 ° C, Au; 1063 ° C, Cu; 1083 ° C) are higher than the sintering temperature of the ceramic dielectric. Quite low.

Since the laminated body 24 is usually formed by integrally sintering the dielectric substrate 21 and the internal electrodes 22 and 23, the ceramics is used for the dielectric substrate 21 and Ag, Au, and When Cu or the like is used, it is necessary to sinter the ceramic at a temperature equal to or lower than the melting point of the low resistance metal, and a high Q value cannot be obtained in the ceramic. On the other hand, if an attempt is made to obtain a high Q value in the ceramic, the sintering temperature exceeds the melting point of the low resistance metal, so that it is not possible to use a low resistance metal such as Ag, Au, or Cu for the internal electrodes 22 and 23. . Therefore, a dielectric material having a high Q value cannot be used for the dielectric substrate 21 and a metal having a low resistance cannot be used for the internal electrodes 22 and 23, so that the Q value of the multilayer chip capacitor 20 cannot be increased. There were challenges.

The present invention has been made in view of the above problems, and provides a multilayer chip capacitor capable of achieving a high Q value in a high frequency range without using a dielectric material having a high Q value. It is an object.

[0011]

[Means for Solving the Problems]

 In order to achieve the above object, the multilayer chip capacitor according to the present invention has two or more internal electrodes formed on the same surface of a dielectric substrate such that their end faces face each other, and the dielectric substrate is laminated. It is characterized in that a laminated body is formed, and external electrodes to which one ends of the respective internal electrodes are connected are formed at both ends of the laminated body.

[0012]

[Action]

In the multilayer chip capacitor having the above-described structure, for example, two internal electrodes are formed on the same surface of a dielectric substrate so that their end faces face each other, and the dielectric substrates are laminated to form a laminated body. When the external electrodes to which one ends of the respective internal electrodes are connected are formed at both ends of the body and the internal electrodes are formed in five layers, the circuit configuration of the laminated capacitor is represented by the equivalent circuit shown in FIG. It One capacitor is formed by the two inner electrodes 12 and 13 connected to the outer electrodes 15 and 16, and the total capacitance C of the multilayer capacitor is five capacitors C ₁₀ , C ₂₀ , C ₃₀ , It is approximately equal to the sum of the capacities of C ₄₀ and C ₅₀ . In each of these capacitors C ₁₀ , C ₂₀ , C ₃₀ , C ₄₀ , and C ₅₀ , the capacitance is formed by the end faces of the internal electrodes 12 and 13 that face each other, and the area of the end faces that face each other is much smaller than the area of the laminated surface. Therefore, the total capacitance of the multilayer capacitor is significantly smaller than that of the conventional multilayer capacitor having the same overall size and the same area and number of internal electrodes.

According to the multilayer chip capacitor of the present invention, two or more internal electrodes are formed on the same surface of a dielectric substrate such that their end faces are opposed to each other, and the dielectric substrates are laminated to form a laminated body. Is formed, and the outer electrodes connected to one end of each internal electrode are formed at both ends of the laminated body. A high Q value can be obtained even if it is made extremely small, and it becomes easy to deal with high frequency regions. Further, structurally, a high Q value is achieved in a high frequency region, it is not necessary to use a ceramic material having a high Q value for the dielectric substrate, and the laminated body is formed by using a low temperature sintering material having a relatively low Q value. Can be formed. Therefore, it becomes possible to use a low resistance metal such as Ag, Au, or Cu as the internal electrode. Further, the equivalent series resistance (hereinafter, referred to as ESR (Equivalent Series Resistance)) in the high frequency region becomes smaller. Also, the self-resonant frequency shifts to the high frequency side.

[0014]

[Examples and Comparative Examples]

 Examples and comparative examples of the multilayer chip capacitor according to the present invention will be described below with reference to the drawings.

FIG. 2 is a schematic cross-sectional view showing the multilayer chip capacitor according to the example, and FIG. 3 is a schematic cross-sectional view of the multilayer chip capacitor according to the example taken along line XX in FIG. Is. Reference numeral 11 in the figure shows a dielectric substrate. Two internal electrodes 12, 13 are formed on the same surface of the dielectric substrate 11 such that their end faces 12a, 13a face each other. Are laminated to form a laminated body 14. An external electrode 15 to which one end 12b of the internal electrode 12 is connected and an external electrode 16 to which one end 13b of the internal electrode 13 is connected are formed at both ends of this laminated body 14, and these dielectric substrates 11 are formed. The multilayer chip capacitor 10 is configured to include the internal electrodes 12, 13 and the external electrodes 15, 16.

In order to manufacture the multilayer chip capacitor 10 having such a structure, first, a dispersant, an organic binder, and a plasticizer are added to BaO—Nd ₂ O ₃ —TiO ₂ powder containing a glass-based sintering aid. After kneading, the mixture is kneaded and then formed into a sheet having a thickness of about 30 μm by a doctor blade method to obtain a dielectric sheet.

Next, after cutting the dielectric sheet into a size such that the baked size is 1.6 mm in length and 0.8 mm in width, Au paste or Ag is applied to one main surface of the dielectric sheet. An internal electrode pattern 18a as shown in FIG. 6 is formed by a screen printing method using / Pb (90/10) paste.

Thereafter, 20 dielectric sheets having the internal electrode patterns 18a printed thereon are laminated, and dielectric sheets having no internal electrode patterns 18a printed on the upper and lower surfaces of the laminated dielectric sheets are laminated and laminated. Form a dielectric sheet.

Next, this laminated dielectric sheet is cut along the alternate long and short dash line (FIG. 6) and then fired in the air at 880 ° C. to form the laminated body 14. After that, Ag paste is applied to the entire end surfaces of the laminated body 14 and then baked to form the external electrodes 15 and 16, whereby the laminated chip capacitor 10 is manufactured.

[0020]

[Table 1]

Table 1 shows the results obtained by measuring the capacitance value and the Q value at 1 MHz with a capacitance meter in Example 1, Example 2, Comparative Example 1 and Comparative Example 2, and the frequencies at 1 GHz, 2 GHz and 3 GHz. The results of measuring the ESR value, Q value, and self-resonant frequency using a network analyzer when changed are shown. Example 1 is a dielectric substrate having a relative dielectric constant of 75, a material Q of 2500 at 1 GHz, a sintering temperature of 880 ° C., a dielectric sheet having a thickness of 30 μm and an Au paste, and 20 layers of internal electrodes. This is a laminated chip capacitor 10 in which 12, 13 are formed and the distance between the electrode ends is 0.057 mm. In Example 2, 20 / layer internal electrodes 12, 13 were formed by using a Ag / Pd (90/10) paste on a 30 μm thick dielectric sheet made of the same material as the dielectric substrate 11 according to Example 1. Is formed and the distance between the electrode ends is set to 0.086 mm 2. In Comparative Example 1, the relative dielectric constant is 21, the material Q at 7 GHz is 7500, the sintering temperature is 1320 ° C., the thickness of the dielectric sheet is 60 μm, and the paste of 100% Pd is used. , 33 are formed in the conventional multilayer chip capacitor 30 (FIG. 8). Comparative Example 2 is a conventional layered chip capacitor 20 (FIG. 9) in which 20 layers of internal electrodes 2 are formed using the same material as that of Example 1. The shape of each of these four laminated chip capacitors was 1.6 mm in length × 0.8 mm in width × 0.8 mm in thickness. At frequencies above the self-resonant frequency, they become inductive components and do not function as capacitors.

As is clear from Table 1, in Example 1, the capacitance value at 1 MHz is 4.7 pF, and the Q values at 1 GHz and 2 GHz are as high as 189 and 112, respectively. The Q value at 3 GHz is as high as 33, the ESR value is also good, and the self-resonant frequency is as high as 3.96. In Example 2, the capacitance value at 1 MHz is 3.8 pF, the Q values at 1 GHz, 2 GHz, and 3 GHz are high values of 220, 136, and 62, respectively, and the ESR value is good. In addition, the self-resonance frequency shows a high value of 4.42 GHz. On the other hand, in Comparative Example 1, the capacitance value at 1 MHz is 3.8 pF, which is the same as that in Example 2, and the Q value is as high as 9000, but at 1 GHz, 2 GHz, and 3 GHz. Has a low Q value of 140, 72, and 20, respectively, and the self-resonant frequency is a small value of 3.56 GHz. Also, in Comparative Example 2, the capacitance value at 1 MHz is 340 pF, which is very large, but the Q value is as low as 700, and it functions as a capacitor above the self-resonance frequency in the high frequency region above 1 GHz. There wasn't. In this way, by forming a capacitance with the end faces 12a, 13a of the internal electrodes 12, 13, it is possible to easily cope with a high frequency region, and even if a ceramic material having a high Q value is not used, structurally high frequency is achieved. It was possible to increase the Q value and the self-resonant frequency in the wave region.

[0023]

[Table 2]

Table 2 shows the deviation and relative value of the capacitance value of each of the multilayer chip capacitors according to Example 2 in Table 1 and the multilayer chip capacitor 30 according to Comparative Example 1 in Table 1 (FIG. 8). It shows the result of examining the deviation.

As is clear from Table 2, in the multilayer chip capacitor according to the second embodiment, the capacitance value deviation is 0.024 pF and the relative deviation is 0.63%. On the other hand, the multilayer chip capacitor 30 according to Comparative Example 1 has a capacitance value deviation of 0.057 pF and a relative deviation of 1.51%, which is 2. It is four times as large. By forming the capacitance by the end faces 12a and 13a of the internal electrodes 12 and 13 in this manner, it is possible to reduce the variation in the capacitance value and improve the accuracy of the deviation of the capacitance value.

[0026]

[Table 3]

Table 3 shows the capacitance at 1 MHz and 1 GHz, the capacitance in the high frequency region of 1 GHz, the ESR value and the Q value when the distance between the electrode ends in the multilayer chip capacitor 10 according to the example is variously changed. It shows the result of measurement. The value of the electrode end distance is obtained by actually measuring the cross section of the multilayer chip capacitor 10 using an optical microscope.

As is clear from Table 3, as the value of the distance between the electrode ends is smaller, the capacitance value at 1 MHz and the capacitance value at 1 GHz are higher, and the ESR at 1 GHz is smaller. Also, in all of Examples 1 to 7, the Q value at 1 GHz is 189 to 315, which is higher than the Q value (140) at 1 GHz in Comparative Example 1 of Table 1. A high Q value could be obtained even when the distance between the electrode ends was changed.

As described above, in the multilayer chip capacitor 10 according to the embodiment, two or more internal electrodes 12, 13 are arranged on the same surface of the dielectric substrate 11 so that their end faces 12a, 13a face each other. And the dielectric substrates 11 are laminated to form a laminated body 14, and external electrodes 15 and 16 to which one ends 12b and 13b of the internal electrodes 12 and 13 are connected are formed at both ends of the laminated body 14, respectively. Therefore, it is possible to form a capacitance by the end surfaces 12a and 13a of the internal electrodes 12 and 13 that face each other, obtain a high Q value, and easily cope with a high frequency region. In addition, it is possible to structurally increase the Q value in the high frequency region, it is not necessary to use a ceramic material having a high Q value for the dielectric substrate 11, and a laminated body is formed by a low temperature sintering material having a relatively low Q value. 14 can be formed. Therefore, a low resistance metal such as Ag, Au, or Cu can be used as the internal electrodes 12 and 13. Further, the ESR in the high frequency region can be reduced. Also, the self-resonant frequency can be shifted to the high frequency side.

Therefore, it can be effectively used as an excellent capacitor especially in an electronic device used in a high frequency region. When the internal electrode pattern 18a (FIG. 6) is formed, the position of the cutting line when cutting the laminated dielectric sheet may be any position as long as the width is constant with respect to the w direction. The distance between the facing end faces 12a and 13a does not change even if the direction is slightly deviated. Therefore, the fluctuation of the capacity can be reduced, and the deviation of the capacity value can be reduced. In addition, the precision in forming the internal electrode patterns 18a and 18b and in cutting the laminated dielectric sheets can be relaxed, and two types of dielectric sheets printed with the internal electrode patterns of high precision arrangement are alternately laminated. There is no need, and it is sufficient to stack one type of dielectric sheet in the same direction, and the labor and cost during manufacturing can be saved.

In the above-mentioned embodiment, the case where BaO—Nd ₂ O ₃ —TiO ₂ containing a glass-based auxiliary agent is used as the material of the dielectric substrate 11 has been described as an example, but in another embodiment. As the material of the dielectric substrate 11, other glass / ceramics low temperature firing substrate, organic polymer material or the like may be used.

In the above embodiment, the case where the internal electrode pattern 18a shown in FIG. 6 is formed has been described as an example, but in another embodiment, the internal electrode pattern 18b shown in FIG. 7 is used. May be formed, and in this case, there is no problem even if the position of the cutting line is slightly shifted.

Further, in the above-described embodiment, the case where the multilayer chip capacitor 10 has two terminals has been described, but in another embodiment, the multilayer chip capacitor 10 has, for example, the internal electrodes 12, 13, and 19 and has three terminals. (FIG. 4) The present invention can be similarly applied to the case having the above. 5 is an equivalent circuit diagram of FIG.

Further, in the above-described embodiment, the case where the multilayer chip capacitor 10 is a component having a single function of the capacitor has been described, but in another embodiment, the multilayer chip capacitor 10 has, for example, L (inductance) or R (resistance). The present invention can be similarly applied to the case where it is used as a part of a laminated component including

Further, in the above-described embodiment, the case where Au or Ag / Pb (90/10) is used for the internal electrodes 12, 13 has been described as an example, but in another embodiment, the internal electrodes 12, 13 are made of Ag. Alternatively, Cu or the like may be used.

[0036]

[Effect of device]

 As described in detail above, in the multilayer chip capacitor according to the present invention, two or more internal electrodes are formed on the same surface of the dielectric substrate so that their end faces are opposed to each other, and the dielectric substrates are laminated. Since the laminated body is formed and the external electrodes to which one ends of the respective internal electrodes are connected are formed at both end portions of the laminated body, a capacitance can be formed by the facing end faces of the internal electrodes. A Q value can be obtained, and it is possible to easily cope with a high frequency region. Further, it is possible to structurally increase the Q value in a high frequency region, and it is not necessary to use a ceramic material having a high Q value for the dielectric substrate, and the laminated body can be formed even with a material having a relatively low Q value. You can Therefore, if a low temperature sintered material is used, a low resistance metal such as Ag, Au, Cu can be used as the internal electrode. Further, the ESR in the high frequency region can be reduced. Also, the self-resonant frequency can be shifted to the high frequency side.

Therefore, it can be effectively used as an excellent capacitor particularly in an electronic device used in a high frequency region.

[Brief description of drawings]

FIG. 1 is an equivalent circuit diagram showing a circuit configuration of a multilayer chip capacitor according to the present invention.

FIG. 2 is a sectional view schematically showing an embodiment of the multilayer chip capacitor according to the present invention.

FIG. 3 is a schematic cross-sectional view of the multilayer chip capacitor according to the example taken along line XX in FIG.

FIG. 4 is a transverse cross-sectional view schematically showing internal electrode portions in a multilayer chip capacitor according to another example.

FIG. 5 is an equivalent circuit diagram showing a circuit configuration of a multilayer chip capacitor according to another example.

FIG. 6 is a top view showing internal electrode patterns according to an example.

FIG. 7 is a top view showing another example of the internal electrode pattern that can be formed on the dielectric sheet when the multilayer chip capacitor according to the example is manufactured.

8 is a cross-sectional view schematically showing a conventional multilayer chip capacitor according to Comparative Example 1. FIG.

FIG. 9 is a cross-sectional perspective view showing a conventional multilayer chip capacitor.

FIG. 10 is an equivalent circuit diagram showing a circuit configuration of a conventional multilayer chip capacitor.

[Explanation of symbols]

 10 Multilayer Chip Capacitor 11 Dielectric Substrate 12, 13, 19 Internal Electrodes 12a, 13a End Faces 12b, 13b One End 14 Laminated Body 15, 16 External Electrodes

Claims (1)

[Scope of utility model registration request] 1. A dielectric substrate having two or more internal electrodes formed on the same surface with their end faces facing each other, said dielectric substrates being laminated to form a laminated body, and both end portions of said laminated body are formed. An external electrode, to which one end of each of the internal electrodes is connected, is formed in the multilayer chip capacitor.