JPH06338781A - Semiconductor device - Google Patents

Abstract

PURPOSE:To effectively make respective terminal function by outputting data to the terminal on the other side when a clock generated at the outside is supplied to the terminal on one side. CONSTITUTION:The terminals 7, 8 are used as two terminals to which the data is outputted separately also as the two terminals to which an oscillation circuit 10 is connected. A first control circuit 9 outputs a signal to control the operations of an inverter 5 and buffers 3, 4. A second control circuit 12 and a decoder 13 which inputs the signals outputted from the first and second control circuits 9, 12 are provided, and the operation of the inverter 5 is controlled by the signal outputted from the first control circuit 9 and the signal outputted from the decoder 13. In other words, when both the signals outputted from the first and second control circuits 9, 12 are set at H levels, the signal generated at the outside is inputted to a functional block 11 by supplying to the terminal 7, and the terminal 8 functions as a port function to which the data is outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device provided with a terminal that also serves as a terminal to which data is output and a terminal to which an oscillator circuit is connected, and is used as a clock for a clock, for example. The present invention relates to a semiconductor device to which a 32 kHz oscillator circuit is connected.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram showing the structure of a conventional semiconductor device of this type. The data register 1 (2) is connected to the terminal 7 (8) via the buffer 3 (4). A ceramic oscillator circuit 10 including a ceramic oscillator, a resistor, and a capacitor is connected between the terminals 7 and 8, and an input side is connected to the terminal 8 to drive the oscillator circuit 10. 5 is installed. The terminal 7 is connected to one input terminal of the NAND circuit 6. The control circuit 9 is connected to the control terminals of the buffers 3 and 4, the other side input terminal of the NAND circuit 6, and the input side of the inverter IV. The output side of the inverter IV is connected to the control terminal of the inverter 5. The output terminal of the NAND circuit 6 is connected to the functional block 11 including a timer and a CPU.

Next, the operation of this semiconductor device will be described. When the signal output from the control circuit 9 is at L level, the NAND circuit 6
The other side input terminal becomes L level. Further, the output side of the inverter 11 becomes H level, the output of the inverter 5 becomes a floating state, and the voltage of the terminal 7 is not input from the NAND circuit 6 to the functional block 11. On the other hand, buffers 3 and 4
Become the operating state, and the data of the data registers 1 and 2 are output to the terminals 7 and 8 respectively.

Next, when the signal output from the control circuit 9 is at H level, the outputs of the buffers 3 and 4 are in a floating state. On the other hand, the output side of the inverter 11 becomes the L level, the inverter 5 becomes the operating state, and the oscillator circuit 10 connected to the terminals 7 and 8 oscillates. NA at this time
The oscillation clock of the terminal 7 is input from the ND circuit 6 to the functional block 11. The oscillation clock input to the function block 11 is used to drive the CPU and as the count source for the timer.

[0005]

In the semiconductor device having such a structure, a clock generated externally is applied to one terminal without operating the oscillator circuit to operate the functional block. When used, the terminal can be made to function as the count source input terminal of the timer, and the usage of the terminal is expanded. However, when using such a method, there is a problem that the other terminal connected to the output side of the inverter that drives the oscillator circuit is in an unused state, and the terminal does not function more effectively. . In view of such a problem, the present invention provides a semiconductor device in which, when an externally generated clock is applied to one terminal, data is output to the other terminal so that each terminal effectively functions. With the goal.

[0006]

A semiconductor device according to the present invention comprises a second control circuit for outputting a signal, and a decoder for inputting each signal output by the first control circuit and the second control circuit. , The operation of the inverter driving the buffer and the oscillator circuit is controlled by the signal output by the first control circuit and the signal output by the decoder, and when the clock generated externally is applied to one terminal, the other terminal The data is output to.

[0007]

When the output signal of the first control circuit is L level,
The buffer is in the operating state and the output of the inverter is in the floating state regardless of the output signal of the second control circuit, and the data is separately output to the two terminals. When the output signal of the first control circuit is at the H level and the output signal of the second control circuit is at the L level, the output of the buffer is in the floating state, the inverter is in the operating state, and the oscillator circuit oscillates. Apply the oscillation clock to one terminal. When the output signals of the first control circuit and the second control circuit are both at H level, the output of one buffer is in a floating state and the other buffer is in an operating state. Also, the output of the inverter becomes floating. When an externally generated clock is applied to one terminal, the data is output to the other terminal. As a result, when an externally generated clock is applied to one terminal, data is output to the other terminal and the other terminal functions as a port.

[0008]

The present invention will be described in detail below with reference to the drawings showing the embodiments thereof. FIG. 1 is a block diagram showing the configuration of a semiconductor device according to the present invention. The data register 1 is connected to the input side of the buffer 3, and its output side is connected to the terminal 7, one side input terminal of the NAND circuit 6 and the input side of the inverter 5 which drives the oscillator circuit described later. . The data register 2 is connected to the input side of the buffer 4, and its output side is connected to the terminal 8 and the output side of the inverter 5. An oscillator circuit 10 including a ceramic oscillator, a resistor, and a capacitor is connected between the terminals 7 and 8.

The first control circuit 9 is connected to the control terminal of the buffer 3, one side input terminal of the AND circuit 13a, and the other side input terminal of the NAND circuit 6. The second control circuit 12 is connected to the input side of the inverter 13c, and its output side is connected to the AND circuit 13
Connected to the other input terminal of a. The output terminal of the AND circuit 13a is connected to the control terminal of the buffer 4 and the input side of the inverter 13b. The output side of the inverter 13b is connected to the control terminal of the inverter 5. The output terminal of NAND circuit 6 is a functional block consisting of a timer and a CPU.
Connected with 11. In addition, AND circuit 13a, inverter
13b and 13c constitute a decoding circuit 13 that decodes the signals output from the first control circuit 9 and the second control circuit 12.

FIG. 2 is a block diagram showing a state in which an externally generated clock is input to the terminal 7 and is used as a count source of a functional block without connecting an oscillator circuit between the terminals 7 and 8. The configuration is the same as that of the semiconductor device shown in FIG. 1 except for the oscillator circuit, and the same components are designated by the same reference numerals.

Next, the operation of the semiconductor device will be described with reference to FIG. Now, when the signal output by the control circuit 9 is at the L level, the AND circuit 13 regardless of the signal output by the control circuit 12.
The output side of a becomes L level, and the buffers 3 and 4 are both in operation. At this time, the output side of the inverter 13b is H
The output level of the inverter 5 becomes a floating state. Since the other input terminal of the NAND circuit 6 is at the L level, the voltage of the terminal 7 is not input from the NAND circuit 6 to the functional block 11. Then, the data of the data registers 1 and 2 are separately output to the terminals 7 and 8, and the terminals 7 and 8 serve as a port function.

Next, when the signal output from the control circuit 9 is at the H level and the signal output from the control circuit 12 is at the L level, the output side of the AND circuit 13a becomes the H level, and the outputs of the buffers 3 and 4 become Both are in a floating state, while the output side of the inverter 13b is at the L level, so that the inverter 5 is in an operating state. At this time, since the other input terminal of the NAND circuit 6 is at the H level, if the oscillator circuit 10 is connected, the oscillator circuit 10 is driven by the inverter 5 and the oscillator circuit 10 oscillates. And this oscillation clock is NA
It is input from the ND circuit 6 to the functional block 11 and used for driving the CPU and as a count source for the timer.

Next, when the signal output from the first control circuit 9 is at H level and the signal output from the second control circuit 12 is at H level, the output of the buffer 3 is in a floating state. On the other hand, the buffer 4 is in the operating state because the output side of the AND circuit 13a is at the L level and outputs the data of the data register 2 to the terminal 8. The output of the inverter 5 is in a floating state because the output side of the inverter 13b is at H level. At this time, since the other input terminal of the NAND circuit 6 is at the H level, the voltage of the terminal 7 is input from the NAND circuit 6 to the functional block 11. Therefore, as shown in FIG. 2, when an externally generated clock is applied to the terminal 7, it is input to the functional block 11 and used for driving the CPU and as a count source for the timer. Therefore, the terminal 8 works as a port function for outputting data.

FIG. 3 is a block diagram showing the configuration of another embodiment of the semiconductor device according to the present invention. A series circuit of a Schmitt circuit 14 and a switch circuit 15 is interposed between the terminals 7 and 8, and an RC oscillator circuit 16 including a resistor and a capacitor is connected. The switch circuit 15 is turned on when the signal output from the inverter 13b is L level. The other configurations are similar to those shown in FIG. 1, and the same components are designated by the same reference numerals.

Next, the operation of this semiconductor device will be described. When the signal output from the first control circuit 9 is at L level, the second
The buffers 3 and 4 are both in operation regardless of the signal output from the control circuit 12. At this time, the switch circuit 15 is off and the other input terminal of the NAND circuit 6 is at the L level, so that the voltage from the NAND circuit 6 to the terminal 7 is a functional block.
11 is not entered. At this time, the data of the data registers 1 and 2 are output to the terminals 7 and 8, and
Acts as a port function.

Next, when the signal output from the first control circuit 9 is at the H level and the signal output from the second control circuit 12 is at the L level, the outputs of the buffers 3 and 4 are both in the floating state and the switch circuit. 15 turns on. RC at this time
When the oscillator circuit 16 is connected, the Schmitt circuit 14 and
It is driven by the RC oscillator circuit 16 and oscillates. At this time, since the other input terminal of the NAND circuit 6 is at the H level,
The oscillation clock is input from the NAND circuit 6 to the functional block 11, and the oscillation clock is used to drive the CPU and count source of the timer.

Next, when the signal output from the first control circuit 9 is at H level and the signal output from the second control circuit 12 is at H level, the output of the buffer 3 is in a floating state, while the buffer 4 is The operation state is entered, and the data of the data register 2 is output to the terminal 8. Further, the switch circuit 15 is turned off. At this time, since the other input terminal of the NAND circuit 6 is at the H level, when an externally generated clock is applied to the terminal 7, it is input from the NAND circuit 6 to the functional block 11 to drive the CPU and count source of the timer. Used as.

FIG. 4 is a block diagram showing the configuration of still another embodiment of the semiconductor device according to the present invention. Between the terminals 7 and 8, a series circuit of inverters 17, 18, and 19 is interposed, and an LC oscillator circuit 20 including an inductance and a capacitor is connected. The other configuration is the same as that of the semiconductor device shown in FIG. 1, and the same components are designated by the same reference numerals.

Next, the operation of this semiconductor device will be described. If the signal output from the first control circuit 9 is at the L level,
The buffers 3 and 4 are both in operation regardless of the output of the second control circuit 12. At this time, the output of the inverter 19 is in a floating state, and the other input terminal of the NAND circuit 6 is L
Since it is at the level, the voltage of the terminal 7 is not input from the NAND circuit 6 to the functional block 11. At this time, terminal 7,
The data of the data registers 1 and 2 are separately output to 8, and the terminals 7 and 8 function as port functions.

Next, when the signal output from the first control circuit 9 is at H level and the signal output from the second control circuit 12 is at L level, the outputs of the buffers 3 and 4 are both in a floating state, while The inverter 19 is in the operating state.
At this time, if the LC oscillator circuit 20 is connected, the inverter 1
7, 18 and 19 operate to drive the LC oscillator circuit 20 to oscillate. Then, this oscillation clock is input from the NAND circuit 6 to the functional block 11 and used for driving the CPU and as the count source of the timer.

Next, when the signal output from the first control circuit 9 is at the H level and the signal output from the second control circuit 12 is at the H level, the output of the buffer 3 is in a floating state, but the buffer 4 is The operation state is entered and the data of the data register 2 is output to the terminal 8. On the other hand, the output of the inverter 19 is in a floating state. At this time, since the other side input terminal of the NAND circuit 6 is at the H level, when an externally generated clock is given to the terminal 7, the NAND circuit 6 inputs the clock to the functional block 11 to drive the CPU and the count source of the timer. used. Therefore, the terminal 8 functions as a port function. By interposing the series circuit of the inverters 17, 18 and 19 between the terminals 7 and 8, it is possible to facilitate oscillation by utilizing the difference in the threshold voltage of each inverter.

[0022]

As described above in detail, according to the semiconductor device of the present invention, when the clock generated externally is applied to one terminal and input to the functional block, the other terminal outputs data. It can work as a function.
Therefore, there is an excellent effect that the function of the terminal that also serves as the terminal to which the data is output and the terminal to which the oscillator circuit is connected can be more effectively assigned.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor device according to the present invention.

FIG. 2 is a block diagram of a semiconductor device showing a state in which a clock generated externally is input.

FIG. 3 is a block diagram showing the configuration of another embodiment of the semiconductor device according to the present invention.

FIG. 4 is a block diagram showing a configuration of still another embodiment of the semiconductor device according to the present invention.

FIG. 5 is a block diagram showing a configuration of a conventional semiconductor device.

[Explanation of symbols]

 1, 2 Data register 3, 4 Buffer 5 Inverter 6 NAND circuit 7, 8 terminal 9 First control circuit 10 Ceramic oscillator circuit 12 Second control circuit

Claims (3)

[Claims] 1. A dual terminal for outputting data output from each buffer and two terminals to which an oscillator circuit is connected are also used, and are interposed between the two terminals. A semiconductor device comprising: an inverter that drives the oscillator circuit; and a first control circuit that outputs a signal that controls the operation of the buffer and the inverter,
A second control circuit that outputs a signal; and a decoder to which each output signal of the second control circuit and the first control circuit is to be input, the buffer and the output signal of the first control circuit When controlling the operation of the inverter and giving an externally generated clock to one terminal,
A semiconductor device having a structure in which data is output to the other terminal. 2. The semiconductor device according to claim 1, wherein a series circuit of a Schmitt circuit and a switch circuit is interposed between the two terminals. 3. A semiconductor device according to claim 1, wherein a series circuit of an odd number of inverters is interposed between the two terminals.