JPH06202755A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To obtain a low power consumption oscillating circuit part in which a test operation can be attained by a high frequency clock. CONSTITUTION:A constant voltage source 7 and a step-down power source stepped-down from the constant voltage source 7 by a step-down regulator 8 can be selectively connected through P channel MOS type transistors 9 and 10 constituting a switching means with an area in which a NAND gate 1 and a Schmidt trigger circuit 2 are included and the step-down power source is used at a normal time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having a low power consumption oscillation circuit section with a step-down regulator.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing a configuration of a conventional low power consumption oscillator circuit with a step-down regulator built in an IC. In the figure, 1 is a NAND gate, 2 is a Schmitt trigger circuit, and 3 is a level shifter. The circuit is shown. A "1" level signal is input to one input end of the NAND gate 1 during operation of the IC, and the other input end is an external input terminal 4. The output terminal of the NAND gate 1 is connected to an internal circuit (not shown) via the Schmitt trigger circuit 2 and the level shift circuit 3. An external output terminal 5 is provided at a connection point between the NAND gate 1 and the Schmitt trigger circuit 2, an oscillator (not shown) is connected to the external output terminal 5 and the external input terminal 4, and a source clock is input through the external input terminal 4. It is supposed to be done.

A constant voltage source 7 supplies a constant voltage V _CC directly to the level shift circuit 3 and also supplies a step-down voltage RGV _CC to the NAND gate 1 and the Schmitt trigger circuit 2 through a step-down regulator 8. It is like this.

Next, the operation of such a conventional oscillation circuit section will be described. From the constant voltage source 7 to the level shift circuit 3, a constant voltage V _CC , NAND gate 1, Schmitt trigger circuit 2
Is supplied with the step-down voltage RGV _CC via the step-down regulator 8, and the source clock is input from the external input terminal 4 in this state. The input source clock is noise-removed by the Schmitt trigger circuit 2 and then level-converted by the level shift circuit 3 to a value corresponding to the digital value used in the internal circuit and supplied to the internal circuit.

[0005]

By the way, in such a conventional oscillation circuit section, the voltage of the source power supply of the transistor of each section to which the source clock is input is low, and the oscillation circuit section operates with a low frequency clock. Since the drive capacity is suppressed and a high frequency clock cannot be input, the test takes a long time because the low frequency block lock is used when testing the internal circuit. was there. The present invention has been made in view of such circumstances, and an object thereof is to enable use of a low-frequency clock during normal operation and a high-frequency clock during testing, thereby enabling a significant reduction in test time. The present invention provides a semiconductor integrated circuit including an oscillation circuit section.

[0006]

A semiconductor integrated circuit according to the present invention shapes a source clock using a constant voltage source, a step-down circuit for stepping down the voltage of the constant voltage source, and a stepped-down power source,
In a semiconductor integrated circuit including a circuit for removing noise and another circuit that uses a clock from the circuit, switching for selectively connecting the constant voltage source or the step-down power source to the circuit using the step-down power source Means are provided.

[0007]

According to the present invention, the driving power is increased by switching the voltage of the source power supply of the transistor in the region where the step-down power supply is used during the test from the step-down voltage to the constant voltage, and the test time is increased by operating with a high frequency clock. Can be shortened.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to the drawings showing the embodiments.

(Embodiment 1) FIG. 1 is a block diagram showing a configuration of a low power consumption oscillation circuit portion incorporated in a semiconductor integrated circuit according to the present invention, in which 1 is a NAND gate, 2 is a Schmitt trigger circuit, and 3 Is a level shift circuit, and 7 is a constant voltage source.

A signal of "1" level is input to one input terminal of the NAND gate 1 during operation of the IC, and the other input terminal is an external input terminal 4 to which a source clock is externally input. The output terminal of the NAND gate 1 is connected to an internal circuit (not shown) via the Schmitt trigger circuit 2 and the level shift circuit 3. An external output terminal 5 is provided at a connection point between the output terminal of the NAND gate 1 and the Schmitt trigger circuit 2, and a clocked inverter 6 is interposed between the external output terminal 5 and the internal input terminal 4.

The constant voltage source 7 is directly connected to the level shift circuit 3
P channel that is connected to the
P-channel MOS with MOS type transistor 9 interposed, or with step-down regulator 8 and switching means
, The NAND gate 1,
Each is connected to the Schmitt trigger circuit 2.

Next, the operation of the semiconductor integrated circuit according to the present invention will be described. First, in normal operation as an IC, P
The channel MOS type transistor 10 is turned off and P
To-channel MOS transistor 9 is turned on, further clocks the clocked inverter 6 is turned off, the constant voltage V _CC to the level shift circuit 3 from the constant voltage source 7, also via the step-down regulator 8, P-channel MOS transistor 9 And supplies the step-down voltage RGV _CC to the NAND gate 1 and the Schmitt trigger circuit 2. In this state, the source clock is input from the external input terminal 4. The input source clock is noise-removed by the Schmitt trigger circuit 2 and then level-converted by the level shift circuit 3 to a digital value corresponding to the digital value used in the internal circuit and output to the internal circuit.

On the other hand, during the test, the P-channel MOS type transistor 9 is turned off, the P-channel MOS type transistor 10 is turned on, and the clocked inverter 6 is turned on. As a result, the constant voltage V _CC of the constant voltage source 7 is supplied to the level shift circuit 3 and the P channel MOS
Is also supplied to the NAND gate 1 and the Schmitt trigger circuit 2 via the transistor 10 of the type, and the source power supply voltage of the transistor used for these is V _cc . In this state, the source clock input from the external input terminal 4 is input from the NAND circuit to the Schmitt trigger circuit 2, but at the same time, it is also input from the output terminal 5 to the Schmitt trigger circuit 2 via the clocked inverter 6, and the NAND gate 1 Aiding driving capacity. The input source clock is the Schmitt trigger circuit 2
After the noise is removed at, the level shift circuit 3 adjusts it to a digital value corresponding to the test of the internal circuit and outputs it to the internal circuit.

In this embodiment, the source power of the transistors of the NAND gate 1 and the Schmitt trigger circuit 2 which normally use the step-down power supply is switched to the constant voltage source at the time of the test, so that the driving capability thereof is enhanced. The test time can be shortened by operating with a clock of a higher frequency.

(Embodiment 2) FIG. 2 is a block diagram showing another embodiment of the present invention. In the second embodiment, P-channel MOS type transistors 9 and 10 which constitute switching means.
Directly to the gate of the register circuit 11 or the inverter 12
The control signal is input via the.

In the second embodiment, the ON / OFF control register circuit 12 for the P-channel MOS type transistors 9 and 10 is used.
It is possible to switch it programmable by the value from. It is needless to say that the ON / OFF control of the clocked inverter 6 may be similarly controlled by the value from the register circuit 12 or the value of another register circuit.

In the second embodiment, the value of the register circuit 12 is given to the P-channel MOS type transistors 9 and 10, and further to the clocked inverter 6, so that the internal circuit can be tested at high speed as required. There are advantages. In the first and second embodiments described above, the switching means is a P channel MOS.
However, the present invention is not limited to this, and it is of course possible to use N-channel MOS type transistors and other various changeover switch means.

[0018]

As described above, the semiconductor integrated circuit according to the present invention is provided with the switching means for selectively connecting the step-down power source and the constant voltage source to the circuit which normally uses the step-down power source. Oscillates using a low-frequency clock, and a logic test can be performed using a high-frequency clock at the time of testing, so that the test work can be performed with high efficiency. It plays.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a circuit of the present invention.

FIG. 2 is a block diagram showing the configuration of another embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a conventional circuit.

[Explanation of symbols]

 1 NAND gate 2 Schmitt trigger circuit 3 Level shift circuit 4 External input terminal 5 External output terminal 6 Clocked inverter 7 Constant voltage source 8 Step-down regulator 9, 10 P-channel MOS type transistor 11 Register circuit 12 Inverter

Claims (1)

[Claims] 1. A constant voltage source, a step-down circuit for stepping down the voltage of the constant voltage source, a circuit for shaping a source clock using a stepped-down power source to remove noise, and a clock from the circuit. A semiconductor integrated circuit comprising another circuit to be used, characterized in that a switching means for selectively connecting the constant voltage source or the step-down power source is provided to the circuit using the step-down power source.