JPH06338777A - Driver circuit - Google Patents

Abstract

PURPOSE:To adjust the rising and falling time of an output waveform by connecting and interposing a resistor and a diode between a non-inversion circuit and the gate of a FET and between an inversion circuit and the gate of the FET by connecting in parallel, respectively, and varying input impedance on the FET. CONSTITUTION:First and second FETs 1, 2 are driven by the non-inverting signal and inversion signal of an input signal, and the output of the non- inversion circuit 9 and the inversion circuit 10 outputted respectively, and the non-inverting signal with the common mode as that of the input signal is outputted from a common terminal 17. The diode 5a and the resistor 7 are interposed by connecting in parallel between the output terminal of the non- inversion circuit 9 and the gate of the FET 1, and the diode 6a and the resistor 8 are interposed by connecting in parallel between the output terminal of the inversion circuit 10 and the gate of the FET 2. In such a case, it is possible to set the leading edge and trailing edge of an output signal waveform arbitrarily by selecting interposed diodes 5a, 6a and resistors 7, 8 appropriately, which enables a desired signal to be supplied at need.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driver circuit, and more particularly to a driver circuit used in a burn-in device to apply a waveform to a device under test.

[0002]

2. Description of the Related Art The structure of a conventional driver circuit will be described with reference to FIG. 21 and 22 are FETs, 23 and 24 are resistors, 2
Reference numeral 5 is a non-inverting circuit, and 26 is an inverting circuit.

In the driver circuit of FIG. 3, the drain of the FET 21 is connected to the power supply terminal, the source is connected to the output terminal 27 through the resistor 23, and the gate is connected to the output terminal of the non-inverting circuit 25.

The drain of the FET 22 is connected to the output terminal 27 through the resistor 24, the source is connected to the ground terminal, and the gate is connected to the output terminal of the inverting circuit 26.

The signal applied from the input is applied to the non-inverting circuit 2
5. The non-inverted signal and the inverted signal, which are 180 degrees out of phase with each other by the inverting circuit 26, are input to the control terminals of the FETs 21 and 22, and the waveform in phase with the non-inverting circuit 25 is output from the output terminal 27.

[0006]

In the conventional driver circuit, the rising time and the falling time of the output waveform are determined by the input capacitance of the FETs 21 and 22 and the output impedance of the inverting circuit 26 and the non-inverting circuit 25.
It was difficult to adjust the rise time and fall time.

According to the present invention, the rise time of the output waveform is
An object of the present invention is to provide a driver circuit whose fall time can be adjusted.

[0008]

In order to achieve this object, according to the present invention, a resistor and a diode are connected in parallel and are inserted between the non-inverting circuit and the gate of the FET and between the inverting circuit and the gate of the FET, respectively. By connecting and changing the input impedance to the FET, the rise and fall times of the output waveform are adjusted.

[0009]

When the resistance value of the diode in the forward direction is sufficiently smaller than the resistance value of the resistor, when the input waveform is applied, the output applied to the FET is only the resistance value in the forward direction of the diode when it goes from the low level to the high level. The input capacitance of the FET is charged and turned on. Further, when the level goes down from the high level to the low level, the diode goes in the opposite direction, and the electric charge stored in the input capacitance of the FET is discharged only by the resistance and turned off. Therefore, by considering the polarity of the diode and inserting and connecting it between the non-inverting circuit or the inverting circuit and the FET and selecting the resistance value of the resistor, the rise and fall times of the output waveform can be adjusted. .

[0010]

1 is a circuit diagram of a driver circuit according to an embodiment of the present invention. 1 and 2 are FETs, 3 and 4 are resistors, 5a and 6a are diodes, 7 and 8 are resistors, 9 is a non-inverting circuit, 10 is an inverting circuit, and 17 is an output terminal.

In FIG. 1, the circuit configuration is similar to the conventional circuit configuration shown in FIG. 3, but the output terminal of the non-inverting circuit 9 and the F
A point where a diode 5a and a resistor 7 are connected in parallel between the gate of ET1 and the output terminal of the inverting circuit 10 and F
The difference is that a diode 6a and a resistor 8 are connected in parallel between the gate of ET2 and the gate.

In the embodiment shown in FIG. 1, the diode 5a has an anode connected to the output terminal of the non-inverting circuit 9 and a cathode connected to the gate of the FET 1, and the diode 6a has a cathode connected to the output terminal of the inverting circuit 10 and an anode. Is FET2
Is configured to be connected to the gate of.

The signal waveform applied from the input becomes a signal waveform which is 180 degrees out of phase with each other by the non-inverting circuit 9 and the inverting circuit 10, and is applied to the gates of the FETs 1 and 2 through the resistors 7.8 and the diodes 5a and 6a. An output waveform that is applied and has the same phase as the non-inverting circuit 9 is output from the output terminal 17.

Since the forward resistance values of the diodes 5a and 6a are sufficiently smaller than the normal resistance values of the resistors 7 and 8, when an input waveform as shown in FIG. 4 (1) is applied to the input, the input to the gate of the FET1 is input. The waveform shows that only the forward resistance value of the diode 5a changes from the low level to the high level.
The charge stored in the input capacitance of the FET1 is non-inverted only by the resistance value of the resistor 7 because the diode 5a is in the reverse direction when the charge is stored in the gate input capacitance of Since the circuit 9 is pulled in and turned off, it becomes as shown in FIG.

Next, as for the waveform to the FET2, when the diode 6a goes in the reverse direction when going from low level to high level,
The charge is stored in the input capacitance of the FET 2 and turned on only by the resistance value of the resistor 8, and conversely when the diode 6a falls from the high level to the low level, the charge stored in the input capacitance of the FET 2 is inverted only by the resistance value in the forward direction. Since the circuit 10 is pulled in and turned off, it becomes as shown in FIG. Therefore, the output waveform at the output terminal 17 is a waveform with a fast rise and a slow fall, as shown in FIG.

FIG. 2 is a circuit diagram of a driver circuit according to another embodiment of the present invention. The difference from the embodiment shown in FIG. 1 is only the polarities of the diodes 5b and 6b.

That is, in this embodiment, the diode 5
In b, the anode is connected to the gate of the FET 1 and the cathode is connected to the output terminal of the non-inverting circuit 9. Also diode 6
In b, the anode is connected to the output terminal of the inverting circuit 10 and the cathode is connected to the gate of the FET 2.

When an input waveform as shown in FIG. 5 (1) is applied to the input, the waveform to the gate of the FET1 has only the resistance value of the resistor 7 because the diode 5b is in the reverse direction when it goes from low level to high level. When the electric charge is stored in the input capacitance of the gate of the FET1 and turned on, and when it goes down from the high level to the low level, the electric charge stored in the input capacitance of the FET1 is reversed by the resistance value of the diode 5b only in the forward direction.
Since it is pulled in and turned off, it becomes as shown in FIG.

Next, regarding the waveform to the FET2, when the diode 6b rises from the low level to the high level, the diode 6b stores the electric charge in the input capacitance of the gate of the FET2 and turns it on, and vice versa. Since the diode 6b goes in the opposite direction when it goes down to the
Since the electric charge stored in the input capacitance of 2 is drawn into the inverting circuit 10 and turned off, it becomes as shown in FIG.

Therefore, the output waveform at the output terminal 17 is shown in FIG.
As shown in (4), the waveform has a slow rising edge and a fast falling edge.

[0021]

According to the present invention, the rising and falling edges of the output signal waveform can be arbitrarily set by appropriately selecting the diode and the resistor that are inserted, so that the non-measurement device can be set as desired. Signal can be supplied.

[Brief description of drawings]

FIG. 1 is a configuration circuit diagram of a driver circuit according to an embodiment of the present invention.

FIG. 2 is a configuration circuit diagram of a driver circuit according to another embodiment of the present invention.

FIG. 3 is a configuration circuit diagram of a conventional driver circuit.

FIG. 4 is a waveform diagram according to the first embodiment.

FIG. 5 is a waveform diagram according to the second embodiment.

[Explanation of symbols]

 1 ・ 2 FET 3 ・ 4 Resistance 5a ・ 5b ・ 6a ・ 6b Diode 7 ・ 8 Resistance 9 Non-inverting circuit 10 Inversion circuit 17 Output terminal

Claims (1)

[Claims] 1. A non-inverting circuit (9) and an inverting circuit (10) that output a non-inverting signal and an inverting signal of an input signal, respectively, and are driven by the outputs of the non-inverting circuit (9) and the inverting circuit (10). A first and a second FET (1, 2), and a non-inverted signal of the same phase as the input signal is output from the common output terminal of the first and the second FET (1, 2). At the output terminal of the non-inverting circuit (9) and the first FET (1)
Of the first diode (5
a, 5b) and the first resistor (7) to the first diode (5a,
The anode (or cathode) of 5b) is the non-inverting circuit (9).
Is inserted so that it is connected to the output terminal side of the
Between the output terminal of (10) and the control terminal of the second FET, the second diode (6a, 6b) and the second resistor (8) connected in parallel are connected to the second diode (6a, 6a, 6b). A driver circuit characterized in that the cathode (or anode) of 6b) is inserted so as to be connected to the output terminal side of the inverting circuit (10).