JPH06338135A - Optical disc device - Google Patents

Abstract

PURPOSE:To reduce throughput, etc., regarding setting per one sector different in every zone. CONSTITUTION:A bit counter 51 and a segment counter 52 conduct counting when a PAT signal output from a pattern detector is asserted. A timing generating circuit 53 forms a timing signal for an SCK signal. A bit counter 58 is used as a counter circuit counting a DCK signal, and count values are changed in every zone by a CPU. A bit counter 59 and a sector counter 60 count the DCK signals. A timing generating circuit 54 form various signals on the basis of the counter values of the bit counter 58 and W/R Gate signals input from the timing generating circuit 53. A phase comparison circuit 55 and an LPF 56 from a voltage signal controlling a voltage-control oscillation circuit 57. Logical circuits 61-63 logically operate dataen signals, etc., respectively, and rst#2 signals, etc., are formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sample servo type optical disk device such as a magneto-optical disk in which data is recorded at different frequencies for each area.

[0002]

2. Description of the Related Art In an apparatus for recording data using an optical disk or a magneto-optical disk, a PLL (phase synchronization) circuit for generating a clock for writing data to the disk or reading data is For example, the one disclosed in Japanese Patent Laid-Open No. 3-156774 is known. FIG. 12 is a diagram showing a configuration of a conventional PLL circuit 8 used in an optical disc device for reproducing data recorded on an optical disc by a sample servo CAV (constant angular velocity) method.

In FIG. 12, the A / D conversion circuit 81 is
The analog RF signal read from the optical disk is converted into a digital signal. The servo pattern detection unit 82 detects the servo pattern recorded on the optical disc. The counter circuit 83 is initialized when the magneto-optical disk device detects a servo pattern, and the VCO 85
The clock signal (C-CLK) output by the counter is counted, and the count result is input to the decoder 84.

The decoder 84 generates a sample pulse corresponding to the counting result of the counter circuit 83 and inputs it to the sample circuit 88. The sample circuit 88 detects specific data in the output data string of the A / D conversion circuit 81 based on the sample pulse, and inputs it to the arithmetic unit 89. Arithmetic unit 8
9 calculates an RF signal, phase error data, and
Detect tracking error.

The D / A conversion circuit 87 converts the PLL error signal detected by the arithmetic unit 89 into an analog format signal. The phase compensation circuit 86 compensates the phase of the output signal of the D / A conversion circuit 87. The VCO 85 is an oscillation circuit controlled by the output signal voltage of the phase compensation circuit 86, and generates the C-CLK signal.

The operation of the PLL circuit 8 will be described below. The RF signal reproduced from the optical disk is the A / D conversion circuit 8
At 1, the signal is converted into a digital format signal and input to the servo pattern detection unit 82 and the sampling circuit 88. The servo pattern detection unit 82 detects a servo pattern such as “1000100” in the output signal of the A / D conversion circuit 81 and inputs it to the counter circuit 83.

When the output waveform of the servo pattern detector 82 has a logical value of 1, the counter circuit 83 is set to a predetermined value. The counter circuit 83 counts the C-CLK signal output from the VCO 85 and inputs it to the decoder 84,
The decoder 84 generates a sample pulse at a predetermined count value. The sample pulse is generated at the timing when the RF signal from the wobbling pit of the optical disc is converted by the A / D conversion circuit 81, etc.
8 is input.

The sample circuit 88 holds (latches) an output signal of the A / D conversion circuit 81 at the time when the sample pulse is input, that is, a digital RF signal corresponding to a plurality of positions of clock pits and wobbling pits.
To do. The arithmetic unit 89 generates a phase error signal and a tracking error signal based on the RF signal latched by the sample circuit 88.

This PLL error signal is converted into an analog signal by the D / A conversion circuit 87, further phase-compensated by the phase compensation circuit 86, and input to the VCO 85. V
The CO 85 generates a C-CLK signal having a frequency corresponding to the output signal of the phase compensation circuit 86.

By the above operation, a stable C-CLK signal is obtained in synchronization with the RF signal corresponding to the clock pit. This C-CLK signal is used as a reference clock for each part in the optical disk device in which the PLL circuit 8 is used.

[0011]

In the conventional sample servo CAV type disk storage medium described above, the outer track length corresponding to the same center angle of the disk is longer than the inner track length. , The amount of data stored in the tracks corresponding to the same central angle is the same. Here, when recording data on the outer track,
When data is stored by increasing the frequency of the clock for recording, and conversely, when data is stored in the inner track, the frequency of the clock is lowered and the same track length is used for both the outer and inner tracks. There is a request to record almost the same data.

In response to this request, for example, the disk is divided into a plurality of areas (zones) in the radial direction and used, and the frequency of the clock for recording data is changed for each zone so that the entire surface of the disk is the same. A method has been developed in which approximately the same amount of data is recorded with respect to the track length to increase the storage capacity of the disc.

Such a recording method is based on MCAV (Mod
This is called the "defined CAV" method or the zone CAV method. In the MCAV system, optimization is performed for each zone in order to maximize the storage capacity of the disc. Therefore, the number of segments included in one sector and the amount of data stored in one segment are different.

A conventional PLL circuit compatible with the CAV system generates a clock signal having substantially the same frequency on the entire surface of the disk and synchronizes this clock signal with an RF signal corresponding to a clock pit formed on the disk. Is configured. Therefore, there is a problem that it cannot be used as it is for recording and reproduction of an MCAV type disc that requires a clock of a different frequency for each zone of the disc.

MCA using variable frequency PLL circuit
It is possible to perform V-system disc recording and reproduction.
However, as described above, since the number of segments included in one sector and the number of bits included in one segment are different for each zone in MCAV discs, these are obtained by table search or calculation, and each time the zone to be accessed changes. It is necessary to make settings corresponding to the zone in this PLL circuit.

Further, since the correspondence between the segment and the sector, and the correspondence between these and the bit count is different for each zone, it is necessary to always take this correspondence into consideration during the recording and reproducing of the data for the recording and reproducing processing. . Therefore, when the processing such as the setting to the PLL described above is performed by the arithmetic processing in the control device of the disk device which generally performs the processing related to the recording and reproducing of the data, the load increases,
As a result, there is a problem that the performance of the disk device is deteriorated.

The present invention has been made in view of the above-mentioned problems of the prior art, and when recording / reproducing an MCAV type disc, a PLL circuit such as the number of segments per sector which is different for each zone is provided. And a disk circuit suitable for recording and reproducing a MCAV system disk using this PLL circuit The purpose is to provide.

[0018]

In order to achieve the above object, the optical disk device of the present invention is synchronized by a sample servo system, and data is recorded at different data rates for each predetermined range of the recording area. For MCAV type discs, a servo clock common to each of the ranges is used to manage timing for recording or reproducing data in each of the ranges, and is synchronized with the servo clock.
Data management means for performing sector management of the data for each of the ranges by using a data clock corresponding to the data speed and recording and / or reproducing the data by managing the bit unit of the data. When,
The data management means has a compensating means for compensating for a delay required for recording or reproducing data on the disc by using the data clock for each of the ranges.

Also, the compensating means prepares the servo clock earlier by a certain period of the servo clock from the time when the data is written to the disk, when the data is recorded, and the prepared data is stored in the data clock. The servo clock is supplied to the data management means earlier by the period corresponding to each range, and the delay from the preparation of the data to the writing to the disk is combined with the delay required for the recording processing in the data management means to obtain the servo clock. It is characterized in that the period is constant.

Further, the compensating means delays the data reproduced by the data managing means by a period corresponding to each range of the data clock when reproducing the data, and the data is transferred from the disc. The delay from the time of reading to the output from the compensating means is output as a fixed cycle of the servo clock together with the delay required for the reproduction processing in the data managing means.

Further, the data managing means has a PLL circuit for generating a data clock, and the PLL circuit is inputted with a servo clock frequency dividing means for dividing the servo clock by a predetermined frequency dividing ratio. A voltage controlled oscillator for generating the data clock having a frequency corresponding to a voltage signal,
The data clock frequency dividing means for dividing the data clock with a different frequency dividing ratio for each range, and the phases of these clocks divided by the servo clock frequency dividing means and the data clock frequency dividing means are compared. And a phase comparison means for converting the voltage signal corresponding to the phase difference and inputting the voltage signal to the voltage controlled oscillator circuit.

[0022]

By the control circuit of the disk recording / reproducing apparatus, the frequency division ratio of each zone of the magneto-optical disk in the MCAV system of the data clock used for recording / reproducing data is set in the register of the PLL circuit for the data clock. By matching the phases of the data clock divided by the division ratio and the servo clock divided by the constant division ratio, data clocks of different frequencies are generated for each zone.

Further, the write data to be recorded on the magneto-optical disk can be set in advance by a predetermined number of data clocks corresponding to each range based on the delay time required for data modulation or the like, so that the write data can be stored in advance. Is prepared earlier by a predetermined period of the servo clock to absorb the delay time in each zone. Similarly, by delaying by a predetermined number of data clocks corresponding to each range based on the delay time required for demodulation of read data read from the magneto-optical disk, the read data is provided late by a predetermined cycle of the servo clock. By doing
The delay time in each zone is absorbed.

Further, by setting the sector number in the counter for counting the sectors of the PLL circuit for the data clock when the predetermined segment of the predetermined zone is reached, a signal which occurs only once for one rotation of the magneto-optical disk. Recording / playback processing is performed without waiting for.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the optical disk device of the present invention will be described below. FIG. 1 is a diagram showing a configuration of a disc recording / reproducing apparatus 1 of the present invention. The disc recording / reproducing apparatus 1 is
A device for recording data on the magneto-optical disk 10 and reproducing the data recorded on the magneto-optical disk 10,
In particular, the DCK PLL circuit 5 is characterized. Unless otherwise specified, each signal of the disc recording / reproducing apparatus 1 is positive logic.

In FIG. 1, a magneto-optical disk 10 is a recording medium used in the disk recording / reproducing apparatus 1, and data is recorded by the magneto-optical effect and the recorded data is read out. The magneto-optical disk 10 is rotated at 1800 rpm, for example, and data is recorded and reproduced. The CPU 6 is, for example, a general-purpose microprocessor or a digital signal processor (DS) for signal processing.
P) and its peripheral circuits such as ROM and RAM,
The general processing of the disk recording / reproducing apparatus 1, the recording / reproducing of data, and the like are performed.

The magnetic head (MH) 11 converts the data recorded on the magneto-optical disk 10 into a magnetic signal,
The voltage is applied to the position on the magneto-optical disk 10 where the data is recorded.

To record data in the disk recording / reproducing apparatus 1, a magneto-optical disk 10 is irradiated with a laser beam from a pickup unit (PU) 12, heat is applied to a data recording position, and the magnetic head 11 is used to apply the heat. This is done by reversing the direction of the magnetic field at the position.

The pickup unit 12 comprises a laser light emitting element (not shown) and a plurality of light receiving elements,
The magneto-optical disk 10 is irradiated with a laser beam, and the laser beam reflected by each light receiving element is converted into an electric signal. The signal from each light receiving element is used for reproduction of data recorded on the magneto-optical disk 10, recording of data, reproduction of a clock used for reproduction, and the like.

The reproducing amplifier 13 amplifies the focus servo signal from the magnetic head 11 and inputs it to the focus servo circuit (FoErr) 16. Reproduction amplifier 14
Amplifies an embossed bit reproduction signal (PPRF) corresponding to a wobble bit or the like from the magnetic head 11, and an analog signal processing circuit (ASP) 19 via a switch 18.
To enter. The reproduction amplifier 15 amplifies the MO reproduction signal used for reproducing the data stored in the magneto-optical disk 10 and inputs it to the analog signal processing circuit 19.

The focus servo circuit 16 processes the output signal of the reproducing amplifier 13 to detect the focus error of the laser beam, and moves the pickup unit 12 in the direction perpendicular to the surface of the magneto-optical disk 10 based on this focus error signal. A focus correction signal to be moved is generated, and focus control of the laser beam applied to the magneto-optical disk 10 via the drive amplifier 17 is performed.

The switch 18 selects either the PPRF signal or the MORF signal in synchronization with the signal reproduced from the magneto-optical disk 10 and inputs it to the circuits after the A / D conversion circuit 20. That is, the switch 18 selects the PPRF signal side when the pickup unit 12 is reproducing the signal of the servo area on the track of the magneto-optical disk 10, and the MORF when the data area is selected.
Select a signal.

The A / D conversion circuit 20 synchronizes with the servo clock signal (SCK) or the data clock signal (DCK) selected by the switch 29, and the switch 18
The two types of reproduced signals in the analog format selected by are converted into digital format signals. The tracking error circuit 21 uses the PPR converted by the A / D conversion circuit 20.
A tracking error is detected based on the F signal, and a tracking correction signal for moving the pickup unit 12 in the radial direction with respect to the surface of the magneto-optical disk 10 is generated based on the tracking error signal, and a laser beam is transmitted via the drive amplifier 22. The irradiation position of is aligned with the center line of the track of the magneto-optical disk 10.

The address reproducing circuit (Add) 23 reproduces the track number and the sector number of the magneto-optical disk 10 being accessed by the magnetic head 11 and the pickup unit 12 and transfers them to the CPU 6. Pattern detection circuit (P
at) 24 detects the PR data shown in FIG. 5C to generate a PAT signal, and the above-described SCK PLL circuit, that is, the A / D conversion circuit 20 and the phase shift post-detection circuit (PE) 2
5, the loop by LPF27 and VCO28 is controlled.

The phase error detection circuit (PE) 25 detects an error between the embossed bit and the servo clock signal (SCK). The LPF 27 filters the output signal of the phase error detection circuit 25, passes a frequency component below a predetermined frequency, and inputs the frequency component to a voltage controlled oscillation circuit (VCO) 28.

The voltage controlled oscillator circuit 28 outputs a servo clock signal (S) having a frequency corresponding to the output signal voltage of the LPF 27.
CK) is generated. Phase error detection circuit 25, LPF2
7 and the voltage controlled oscillator circuit 28 constitute a PLL circuit for generating a servo clock signal (SCK).

The DCK PLL circuit 5 generates a data clock signal (DCK) used for reading and writing data from the magneto-optical disk 10 and other timing signals used in the disk recording / reproducing apparatus 1. . The configuration of the DCK PLL circuit 5 will be described later with reference to FIG.

The demodulation circuit (DEM) 26 demodulates the data recorded on the magneto-optical disk 10 from the MORF signal. The laser pulse generation circuit (PG) 30 generates a writing laser pulse signal for controlling the laser light emitting element of the pickup unit 12 at the time of data writing based on the data clock signal (DCK).

The timing generation circuit 33 is a DCK PL.
Bit count generated by the L circuit 5 (bitCNT)
A data control signal is generated based on the signal and the sector count (SctCNT) signal and is passed to the CPU 6. The command latch circuit (CMDL) 34 latches an instruction from the CPU 6. The pulse generation circuit (PG) 30 generates a laser pulse signal used to generate a laser control signal for controlling the laser light emitting element of the pickup unit 12, and inputs it to the gate circuit 31.

The gate circuit (Gat) 31 receives the laser pulse signal from the pulse generation circuit 30 and holds the command held by the command latch circuit 34 and the DCK P.
The read gate signal and the write gate signal (WGa) generated by the timing generation circuit (TG) 53 of the LL circuit 5.
te, RGate) to perform a logical operation to generate a laser control signal. There are three types of laser control signals: pulse generation, continuous light emission, and no light emission.

The laser drive circuit (LD) 32 drives the laser light emitting element of the pickup unit 12 based on the laser control signal generated by the gate circuit 31.
Although not shown in FIG. 1, the laser driving circuit 32 generates a high-frequency signal used for reading the data stored in the magneto-optical disk 10 and a circuit for controlling the power supplied to the laser light emitting element. Further, it has a circuit for superimposing on the laser control signal, and controls the power supplied to the laser light emitting element and superimposes a high frequency signal.

The modulation circuit (MOD) 35 modulates the data to be recorded on the magneto-optical disk 10 and converts it into a recording signal in a format recordable on the magneto-optical disk 10. The magnetic head drive circuit (MD) 36 drives the magnetic head 11 based on the recording signal generated by the modulation circuit 35.

The structure and operation of the DCK PLL circuit 5 will be described below. FIG. 2 shows a PLL for DCK of the present invention.
3 is a diagram showing a configuration of a circuit 5. FIG. In FIG. 2, a first bit counter (bitCNT) 51 and a segment counter (SegCNT) 52 are counter circuits that count a servo clock signal (SCK), and are in a relationship of a lower counter and an upper counter, respectively. .

The bit counter 51 and the segment counter 52 are the PAs output from the pattern detection circuit 24.
Counting is performed when the T signal is asserted. Although illustration is omitted for simplification of the illustration, the count value of each counter of the DCK PLL circuit 5 is configured to be read from the CPU 6.

The first timing generating circuit 53 has a write gate signal (WGate) and a read gate signal (R
A timing signal for the servo clock signal (SCK) such as a gate signal (R / WGate), a servo control signal, an address control signal, and a reference signal for the servo clock signal (SCK) is generated. The second bit counter 58 is a counter circuit that counts the data clock signal (DCK), and the count value is changed by the CPU 6 for each zone. The third bit counter 59 and the sector counter (SctCNT) 60 are counter circuits that count the data clock signal (DCK), and the bit counter 59 and the sector counter 60 have a lower counter and an upper counter, respectively. It is in.

The second timing generation circuit 54 includes the count value of the bit counter 58 and the timing generation circuit 5.
Various signals such as a data clock signal (DCK) basis are generated based on the W / R Gate signal input from the signal generator 3.
The phase comparison circuit 55 compares the phases of the reference signal of the data clock signal (DCK) and the reference signal of the servo clock signal (SCK) input from the timing generation circuits 53 and 54, and inputs the error signal to the LPF 56. To do.

The LPF 56 corrects the phase of the error signal output from the phase comparison circuit 55. The voltage controlled oscillator (VCO) 57 generates a clock signal (data clock signal (DCK)) having a frequency corresponding to the voltage of the signal output from the LPF 56.

The logic circuits 61 to 63 respectively output a data enable signal (dataen) and a segment initial signal (initse) output from the timing generation circuit 54.
g), logical operation is performed on the rotation initial signal (initrev # 1) to generate a reset signal (rst # 2) and an enable signal (en). The logics of the logic circuits 61 to 63 are as shown in FIG.

The operation of the DCK PLL circuit 5 will be described below. The servo clock signal (SCK) generated by the PLL circuit for the servo clock signal (SCK) is counted by the bit counter 51 and the segment counter 52 of the DCK PLL circuit 5. Since the servo clock signal (SCK) is the same as the data clock signal (DCK) in the zone 0, the bit counter 51 outputs the ripple carry (rc) signal every time the servo clock signal (SCK) is counted 320 times. The segment counter 52 is asserted and used as an enable signal (en).
To enter.

The segment counter 52 counts the servo clock signal (SCK) only when the enable signal (en) is asserted. Therefore, the bit counter 5
A count value of 1 represents a bit within a segment and a count value of the segment counter 52 represents a segment.

The segment counter 52 and the count value of the segment counter 52 are input to the timing generation circuit 53. The timing generation circuit 53 divides the R / W Gate signal and the servo clock signal (SCK) into eight based on the count values of the bit counter 51 and the segment counter 52 and the servo clock signal (SCK), and an SCK reference signal. And so on.

The bit counter 58 operates according to the zone information set by the CPU 6 to generate the data clock signal (D
CK) is a data clock signal (DCK) divided by (8 + n) to generate a DCK reference signal. Here, n is the zone number (0 to 8) of the magneto-optical disk 10 accessed by the disk recording / reproducing apparatus 1.

The timing generation circuit 54 is initially rotated every time the magneto-optical disk 10 makes one rotation based on the W / RGate signal input from the timing generation circuit 53 and the data clock signal (DCK). A signal (initrev # 1), a segment initial signal (initseg) indicating the servo area of the segment, and a data enable signal (dataen) indicating the data area of each segment are generated.

These signals and bit counter 5
The ripple carry (rc) signal asserted each time 9 counts the data clock signal (DCK) 5120 times is logically operated by the logic circuits 61 to 63, and the logic circuit 6
Enable counting of the bit counter 59 from 1 (en),
The logic circuit 62 inputs a signal for resetting the count of the bit counter 59 (rst), permitting the count of the sector counter 60 (en), and a signal for resetting the sector counter 60 (rst # 2) from the logic circuit 63.

The bit counter 59 to which these signals are input is a data clock signal (DCK) for the data area.
Is counted 5120 times when the ripple carry of the bit counter 59 itself is not asserted. Where the first
In the magneto-optical disk 10 of the embodiment, 5120 bits of data are recorded in one sector as will be described later, and the count value of the bit counter 59 represents the order of bits in the sector.

The sector counter 60 is a bit counter 59 in the servo area of the magneto-optical disk 10.
Counts when the ripple carry is asserted, the count value of the sector counter 60 indicates the order of the sectors.

The SCK reference signal and the DCK reference signal output from the timing generation circuit 53 and the timing generation circuit 54 are compared in phase by the phase comparison circuit 55, and the result of this phase comparison is input to the LPF 56. The voltage controlled oscillator circuit 57 generates and outputs a data clock signal (DCK) having a frequency corresponding to the output voltage of the LPF 56.

As described above, unlike the conventional PLL circuit, the DCK PLL circuit 5 of the present invention only sets the frequency division ratio corresponding to the zone from the CPU 6 to the bit counter 58, and the data clock signal ( DCK)
Can be generated. Furthermore, the CPU 6 can manage the relationship between different sectors, segments, and bits in each zone by reading the value of each counter. Is unnecessary. Therefore, the processing load on the CPU 6 can be reduced. The ripple carry signal of the bit counter 59 and the rotation initial signal (ini
Timings such as trev) will be described later with reference to FIG.

The MCAV system and the operation of the disc recording / reproducing apparatus 1 will be described below with reference to the drawings. First, the MCAV system will be described. FIG. 3 is a diagram for explaining the relationship between the radial position of the magneto-optical disk and the track length. In FIG. 3, the outer peripheral track shown in FIG. 3A is located at a position r in the radial direction from the center of the magneto-optical disk and corresponds to the central angle θ. The inner circumferential side track shown in (B) is located at a position r / 2 in the radial direction from the center and corresponds to the central angle θ.

The conventional CAV type magneto-optical disk is rotated at the same rotation speed regardless of which location is accessed, and the recording / reproducing clock of the same frequency is used, so that it is centered on each track. Certain data was recorded for the corners. That is, since the outer track and the inner track correspond to the same central angle, the outer track and the inner track are twice as long as the inner track, but they are the same. Record the amount of data.

On the other hand, as will be described below, the MCAV type magneto-optical disk is rotated at the same rotation speed when accessing any of the locations, and the magneto-optical disk is divided into a plurality of areas (zones). Data clock signal (DC) for recording / reproducing data for each zone.
By changing the frequency of K), almost the same data is recorded on the entire surface of the magneto-optical disk for the same track length.

FIG. 4 is a diagram for explaining zone division of the magneto-optical disk 10. In FIG. 4, the magneto-optical disk 1
0 is divided into zones 0 to 8 by the same length in the radial direction, where the radius of the inner circumference of zone 0 and the radius of the inner circumference of zone 8 are r / 2 and r, respectively. .

Here, the magneto-optical disk 10 is rotated at a constant rotation speed regardless of which location is accessed, and in the zone 8, the frequency is 16/8 times as high as the data clock signal (DCK) in the zone 0. Data is written and read using a data clock signal (DCK).

In the zone 8, the data clock signal (DCK) having a frequency 16/8 times that of the data clock signal (DCK) in the zone 0 is used to write and read data. Applies to each zone. That is, in a certain zone, data writing and reading are performed using a data clock signal (DCK) having a frequency proportional to the value of the ratio of the inner radius of the zone to the inner radius of the zone 0. .

This relationship will be described with reference to Table 1.

[Table 1] Table 1 is a table showing the relationship between the amount of data per segment for each zone (area) of the MCAV type magneto-optical disk 10, the number of segments per sector, and the recording / reproducing frequency (fdck) for zone 0 of each zone. is there.

When data is read from or written to the magneto-optical disk 10 by the sample servo method, since the segment is provided corresponding to the central angle of the magneto-optical disk 10, the amount of data per segment in each zone, and There is a difference in the number of segments per sector.

Further, in the magneto-optical disk 10, user data is handled in units of 512 bytes, and the user data includes, for example, an error correction code (ECC) or the like.
Since 40 bytes of bytes, sampling threshold information, and reproduction clock phase correction information are added, 640 bytes (5120 bits) of data are recorded per sector.

In the zone on the inner circumference side, the track length per segment becomes short even though the data quantity per same track length is the same in the zone on the outer circumference side. Therefore, the data quantity per segment is small. Become. Further, in the zone on the outer peripheral side, the opposite relationship holds, and therefore the relationship shown in the column of data per segment in Table 1 holds. Here, the data amount corresponding to each zone is described as 320 = 40 × 8 in order to clearly show the correspondence with the recording frequency.

Further, while it is necessary to record the same amount of data in one sector, the amount of data per segment is smaller in the inner zone, so the number of segments per sector is in the inner zone. More sectors. Further, in the zone on the outer peripheral side, since the opposite relationship is established, the relationship shown in the column of the number of segments per sector in Table 1 is established. Since the recording (reproducing) frequency of each zone is proportional to the inner radius of the zone as described above, the relationship shown in the recording frequency (fdck) column of Table 1 is established.

FIG. 5 is a diagram showing the segment structure of the magneto-optical disk 10 and the servo area structure of each segment. FIG. 6 is a diagram showing the relationship between the waveform of the signal obtained from the servo area and the clock. In FIG.
(A) shows the segment structure of zone 0, (B)
Shows the segment structure of zone 8, and (C) shows the structure of pits in the servo area of each segment.

As shown in FIGS. 5A and 5B, each sector is composed of a header segment and a data segment, and each data segment is a servo in which signals used for tracking control, focus control, etc. are recorded. It is composed of an area and a data area in which the data body is recorded.

Each servo area has a clock pit (CP) provided on the center of the track and a wobble pit (WP) provided at a position deviated from the center of the track. Clock reproduction is performed based on the signal obtained from the pits, and the servo clock signal (SCK) and the data clock signal (DC
K) is generated, and focus control and tracking control are performed.

These pits in the servo area are provided at the positions shown in the figure with the head of the servo area as the first bit, and the reflected laser beam from the tracking area is electrically picked up by the pickup unit 12 as shown in FIG. It is converted into a reproduction signal. The relationship between the servo clock signal (SCK) and each point indicated by a0 to a2, b1 to b2, and c0 to c2 in this reproduced signal is as shown in the figure. Note that 6-bit PR data is written in the data area prior to the data body (DATA), and PO data is placed after the data body.

The operation of the disc recording / reproducing apparatus 1 will be described below. FIG. 7 is a timing chart showing the timing of the W / R Gate signal and the laser control signal. FIG. 8 shows the dataen signal and the data clock signal (DC
8 is a timing chart showing the timing of (K) and the like.
Note that in FIGS. 7 and 8, the write data reference signal is duplicated to clarify the timing relationship in both figures. FIG. 9 is a timing chart showing the timing of the write data reference signal, the read data reference signal, and the like.

The operation when the disk recording / reproducing apparatus 1 writes data to the magneto-optical disk 10 will be described with reference to FIGS. 7 and 8. In FIG. 7, the read gate (RGate) signal at the time of writing is asserted at the timing of reading the signal in the servo area. On the other hand, the write gate (WGate) signal is asserted at the timing of accessing the data area in synchronization with the WGate reference signal. The WGate reference signal is a signal used inside the timing generation circuit 53 and is not shown in FIGS. 1 and 2.

The laser power control signal (LDP) signal is
This is a signal generated by the timing generation circuit 53 of the DCK PLL circuit 5, and is a signal for controlling the power supplied from the laser drive circuit 32 to the laser light emitting element of the pickup unit 12. When the LDP signal is asserted, the laser driving circuit 32 generates a laser control signal (LDD) for pulse generation, and increases the power supplied to the laser light emitting element to increase the intensity of the laser beam, thereby causing the magneto-optical disk 10 to operate. Output a laser beam for writing to.

Therefore, when the write gate signal (WGate) is asserted in the pickup unit 12, a pulsed LDD signal with high power is input, so that the laser emitting element emits a pulsed laser beam with high intensity. Irradiation of the magneto-optical disk 10. Data is written on the magneto-optical disk 10 by the magneto-optical action of the writing laser beam and the writing (MHD) signal applied from the magnetic head 11.

On the other hand, when the LDP signal is negated, the laser driving circuit 32 generates the LDD signal for continuous light emission, reduces the power supplied to the laser light emitting element to weaken the intensity of the laser beam, and Disk 10
The laser beam for reading to is output.

Therefore, when the read gate signal (RGate) signal is asserted in the pickup unit 12, a continuous LDD signal with weak power is input, so that the laser light emitting element continuously reads with low intensity. The laser beam for application is applied to the magneto-optical disk 10, and the reflected light allows the pickup unit 12 to read the synchronization signal in the servo area. The disc recording / reproducing apparatus 1 establishes synchronization when writing data on the magneto-optical disc 10 based on the synchronization signal.

In FIG. 8, data setup is the time required for processing such as input / output of write data and modulation of write data in the modulation circuit 35, and the length of this data setup depends on the data clock signal (DCK). Therefore, the timing relationship with WGate is different for each zone. Therefore, for example, when a shift register is provided in the modulation circuit 35 and the gate circuit 31 and the transmission of the LDD signal and the MHD signal shown in FIG. 7 is always delayed from the write data reference signal by the servo clock signal (SCK) for a certain period, To be done in.

For example, when the length of the data setup is eight cycles of the data clock signal (DCK), the data setup time is set to the servo clock signal (SCK).
By setting the period for 8 cycles, it is possible to absorb the time delay between the input / output of the write data and the output of the LDD signal and the MHD signal in all zones. That is, when this delay is a delay of k cycles of the data clock signal (DCK), the data setup time is set to k cycles of the data clock signal (DCK).

That is, in the zone 0, the cycle of the servo clock signal (SCK) and the data clock signal (D
CK) has the same cycle, and in this example, if the data setup time for eight cycles of the servo clock signal (SCK) is provided, data will not be lost. In the zones other than zone 0, the cycle of the data clock signal (DCK) is shorter than the cycle of the servo clock signal (SCK), so that the servo clock signal (SC
K) If the data setup time for 8 cycles is provided, the data will not be lost.

Therefore, the write data reference signal is set to DC
Servo clock signal (SCK) 8 for K reference signal
Assert at a timing earlier than the cycle. Considering the write data reference positions 1 and 2 shown in FIG.
Data reference position 1 for write data and data reference position 2
Between, the time when WGate was asserted, that is,
It is equal to the length of the data area.

If the delay time between the write data reference signal and the write gate signal (WGate) is the servo clock signal (SCK) 8n (n is an integer), the data enable signal (dataen) is asserted and negated. Since the servo clock signal (SCK) and the data clock signal (DCK) have the same phase,
The phase difference between the n signal and the servo clock signal (SCK) can be absorbed by performing the processing in synchronization with the data clock signal (DCK). The data enable signal (dataen) at the time of writing shown in FIG. 8 is a signal generated as described above.

Hereinafter, in the disc recording / reproducing apparatus 1,
The operation of reading data from the magneto-optical disk 10 will be described. In the case of writing data to the magneto-optical disk 10, write data was prepared earlier in the write gate signal (WGate) by the time shown in the data setup, but when reading, the analog signal processing circuit 19, A / D It takes time for the processing in the conversion circuit 20 and the demodulation circuit 26, and a delay occurs after the signal is read from the magneto-optical disk 10 until the data is output.

Therefore, when reading data, contrary to the case of writing data, as shown in FIG. 8, a data delay is given to generate a data enable signal (dataen). The length of this data delay is 8n cycles of the servo clock signal (SCK) in the first embodiment, similar to the data setup time at the time of writing.

FIG. 10 is a timing chart showing the timing of the segment end signal and the count value of the sector counter 60. In FIGS. 9 and 10, the timings of the servo area and the data area are overlapped to clarify the relationship between the timings in both figures. DCK
FIG. 6 is a diagram showing the timing of each signal generated by the timing generation circuit 54 of the PLL circuit 5 for use. It should be noted that in FIG. 10, the portion painted in black indicates a range in which no data is recorded.

Segment initial signal (initseg)
Is asserted at the position of the servo area of each segment, and the rotation initial signal (initrev) is asserted once per rotation of the magneto-optical disk 10. The bit counter 59 and the sector counter 60 are reset when the rotation initial signal (initrev) is asserted and the segment initial signal (initseg) is asserted.

The ripple carry signal is asserted when the bit counter 59 counts the DCK 5120 times, and when this signal is asserted and the segment initial signal (initseg) is asserted, the sector counter 60 is counted up. It Here, the count value of the bit counter 59 is shown, for example, in the case of zone 7, and in this case, as shown in black in the figure, data is stored from the last part of the sector to the data area of the next sector. May not be used for. MCAV
This is because, in the system, the end of the sector, that is, the 5120th bit of the data clock (DCK) does not necessarily become the end of the segment.

The second embodiment of the present invention will be described below.
The DCK PLL circuit 7 is a modification of the initialization method of the sector counter 60 of the DCK PLL circuit 5. FIG. 11 is a diagram showing the configuration of the DCK PLL circuit 7 in the second embodiment. In FIG. 11, a logic circuit 70
Performs an AND operation on the segment initial signal (initseg), the load sector signal (ldsct), and the enable load signal (enload) to generate a reset signal for the sector counter 60.

The comparison circuit (CMP) 72 compares the segment counter 52 and the comparison segment value set in the register 73, and when they match, the enable load signal (e
nload) is asserted. Register 73 is a CPU
The comparison segment value set by 6, the load segment signal (ldseg) which is a bit signal, and the enable load signal (enload) are held. Other D
Each part of the CK PLL circuit 7 has a DCK PLL circuit 5
Is the same for each part with the same reference numeral.

The operation of the DCK PLL circuit 7 will be described below. The CPU 6 has a comparison segment value, a load segment signal (ldseg) and an enable load (enl).
Oad) is set in the register 73. This enable load (enload) is asserted (logical value 1
Then, the following operations are performed. The segment number counted by the segment counter 52 and the register 73
The comparison segment values stored in are compared and the load sector signal (ldsct) is asserted when the two match.

In this case, when the segment initial signal (initseg) is asserted, the load signal (ld) is asserted and the sector number stored in the register 73 is set in the sector counter 60. With this configuration, when the disc recording / reproducing apparatus 1 accesses a predetermined zone of the magneto-optical disc 10, a rotation initial signal (initrev) that is asserted only once every one revolution of the magneto-optical disc 10 is generated. It is possible to record / reproduce data on / from the magneto-optical disk 10 without waiting.

In addition to the above, the optical disk device of the present invention is
For example, various configurations such as setting the rotation speed of the magneto-optical disk 10 to 3600 rpm are possible.

[0095]

As described above, according to the optical disk device of the present invention, the control device of the disk recording / reproducing device is the DCK.
It is possible to generate clock signals having different frequencies required for recording / reproduction of the MCAV type magneto-optical disk only by setting the count value in the PLL circuit for use. Further, since the DCK PLL circuit counts the sectors, segments, and bits of the magneto-optical disk accessed by the disk recording / reproducing apparatus, the control circuit of the disk recording / reproducing apparatus does not need to manage them. Therefore, it is possible to reduce the addition of the control circuit of the disc recording / reproducing apparatus, which simplifies the development of software for operating the disc recording / reproducing apparatus.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a disc recording / reproducing apparatus of the present invention.

FIG. 2 is a diagram showing a configuration of a DCK PLL circuit of the present invention.

FIG. 3 is a diagram illustrating a relationship between a radial position of a magneto-optical disk and a track length.

FIG. 4 is a diagram illustrating zone division of a magneto-optical disk.

FIG. 5 is a diagram showing a segment structure of a magneto-optical disk and a servo area structure of each segment.

FIG. 6 is a diagram showing a relationship between a waveform of a signal obtained from a servo area and a clock.

FIG. 7 is a timing chart showing timings of a write gate signal (WGate) and a laser control signal.

FIG. 8 shows a dataen signal and a data clock signal (DC
8 is a timing chart showing the timing of (K) and the like.

FIG. 9 is a timing chart showing timings of a write data reference signal, a read data reference signal, and the like.

FIG. 10 is a timing chart showing timings of a segment end signal and a count value of a sector counter.

FIG. 11 is a DCK PLL circuit 7 according to a second embodiment.
It is a figure which shows the structure of.

FIG. 12 is a diagram showing a configuration of a conventional PLL circuit used in an optical disc device for reproducing data recorded on an optical disc by a sample servo CAV (constant angular velocity) method.

[Explanation of symbols]

 1, 7 ... Disk recording / reproducing apparatus 5 ... DCK PLL circuit 51, 58, 59 ... Bit counter 52 ... Segment counter 53, 54 ... Timing generation circuit 55 ... Phase comparison circuit 56 ... LPF 57 ... Voltage controlled oscillation circuit 60 ... Sector counter 61-63, 70 ... Logic circuit 72 ... Comparison circuit 73 ... Register 6 ... CPU 10 ... Optical Magnetic disk 11 ... Magnetic head 12 ... Pickup unit 13-15 ... Playback amplifier 16 ... Focus servo circuit 17 ... Disk recording / playback device 18, 29 ... Switch 19 ... Analog signal Processing circuit 20 ... A / D conversion circuit 21 ... Tracking error circuit 22 ... Drive amplifier 23 ... Address reproduction circuit 24 ... Pattern detection circuit 25 ... Phase error detection circuit 26 ... Demodulation circuit 27 ... LPF 28 ... Voltage controlled oscillation circuit 30 ... Pulse generation circuit 31 ... Gate circuit 32 ... Laser drive circuit 33 ... Timing generation circuit 34 ... Command latch circuit 35 ... Modulation circuit 36 ... Magnetic head drive circuit

Claims (4)

[Claims] 1. Synchronizing by a sample servo system,
For MCAV type discs in which data is recorded at different data speeds for each predetermined range of the recording area, timing of data recording or reproduction is managed for each range by using a servo clock common to each range. , Recording and reproducing data by performing sector management of the data for each range and management of the data in bit units in synchronization with the servo clock and using a data clock corresponding to the data speed, or An optical disk device comprising: a data management means for performing either one and a compensation means for compensating a delay required for recording or reproducing data on the disk in the data management means by using the data clock for each of the ranges. 2. The compensator, when recording data, prepares the servo clock earlier by a certain period from the time when the data is written on the disk, and prepares the prepared data by the data clock. The servo clock is supplied to the data management means earlier by the period corresponding to each range, and the delay from the preparation of the data to the writing to the disk is combined with the delay required for the recording processing in the data management means to obtain the servo clock. The optical disk device according to claim 1, wherein the optical disk device has a fixed period. 3. The compensating means, when reproducing the data, gives the data reproduced by the data managing means a delay of a period corresponding to each range of the data clock,
A delay from the time when the data is read from the disk to the time when the data is output from the compensating means is output as a fixed cycle of the servo clock together with the delay required for the reproduction processing in the data managing means. The optical disk device according to claim 1 or 2, which is characterized in that. 4. The data management means has a PLL circuit for generating a data clock, and the PLL circuit is inputted with servo clock frequency dividing means for frequency-dividing the servo clock at a predetermined frequency division ratio. A voltage controlled oscillator for generating the data clock having a frequency corresponding to a voltage signal, a data clock divider for dividing the data clock with a different division ratio for each range, and the servo clock divider And a phase comparing means for comparing the phases of these clocks divided by the data clock dividing means, converting to the voltage signal corresponding to the phase difference, and inputting to the voltage controlled oscillator circuit. The optical disk device according to any one of claims 1 to 3, characterized in that: