JP4001934B2 - Disk unit - Google Patents

Description

[0001]
[Industrial application fields]
  The present inventionRegion (zone) divided in the radial directionThe present invention relates to an optical disc apparatus such as a sample servo type magneto-optical disc in which data is recorded at different frequencies.
[0002]
[Prior art]
  In an apparatus for recording data using an optical disk or a magneto-optical disk, a PLL (phase synchronization) circuit that generates a clock for writing data to or reading data from a disk is disclosed in, for example, The one disclosed in Japanese Patent No. 156774 is known.
  FIG. 12 is a diagram showing a configuration of a conventional PLL circuit 8 used in an optical disc apparatus for reproducing data recorded on an optical disc by a sample servo CAV (constant angular velocity) method.
[0003]
  In FIG. 12, an A / D conversion circuit 81 converts an analog RF signal read from an optical disk into a digital signal.
  The servo pattern detection unit 82 detects a servo pattern recorded on the optical disc.
  The counter circuit 83 is initialized when the magneto-optical disk device detects a servo pattern, counts the clock signal (C-CLK) output from the VCO 85, and inputs the count result to the decoder 84.
[0004]
  The decoder 84 generates a sample pulse corresponding to the count result of the counter circuit 83, and samplesholdInput to circuit 88.
  sampleholdThe circuit 88 detects specific data in the output data string of the A / D conversion circuit 81 based on the sample pulse.Hold andInput to the arithmetic unit 89.
  The computing unit 89 computes the RF signal and detects phase error data and tracking error.
[0005]
  The D / A conversion circuit 87 converts the PLL error signal detected by the calculation unit 89 into an analog signal.
  The phase compensation circuit 86 performs phase compensation on the output signal of the D / A conversion circuit 87.
  Voltage controlled oscillator (VCO)An oscillation circuit 85 is controlled by the output signal voltage of the phase compensation circuit 86, and generates a C-CLK signal.
[0006]
  Hereinafter, the operation of the PLL circuit 8 will be described.
  optical diskFrom the data (pit) recorded inThe reproduced RF signal is converted into a digital signal by the A / D conversion circuit 81, and the servo pattern detector 82 and the sample are converted.holdInput to the circuit 88.
  The servo pattern detection unit 82 detects a servo pattern such as “1000100” from the output signal of the A / D conversion circuit 81 and inputs it to the counter circuit 83.
[0007]
  When the output waveform of the servo pattern detector 82 is a logical value 1, the counter circuit 83 is set to a predetermined value.
  The counter circuit 83 counts the C-CLK signal output from the VCO 85 and inputs it to the decoder 84. The decoder 84 generates a sample pulse at a predetermined count value.
  This sample pulse is the wobbling pit of the optical disc.(Wobble pit)FromDetectedSample generated at the timing when the RF signal is converted by the A / D conversion circuit 81holdInput to the circuit 88.
[0008]
  sampleholdThe circuit 88 holds an output signal of the A / D conversion circuit 81 at the time when the sample pulse is inputted, that is, a digital RF signal corresponding to a plurality of positions of the clock pit and wobbling pit (Hold orLatch).
  Calculation unit 89 is a sampleholdBased on the RF signal latched by circuit 88, the phase error signal(PLL error signal)And a tracking error signal.
[0009]
  This PLL error signal is converted into an analog signal by the D / A conversion circuit 87, further phase-compensated by the phase compensation circuit 86, and input to the VCO 85.
  The VCO 85 generates a C-CLK signal having a frequency corresponding to the output signal of the phase compensation circuit 86.
[0010]
  With the above operation, a stable C-CLK signal can be obtained in synchronization with the RF signal corresponding to the clock pit.
  The C-CLK signal is used as a reference clock for each part in an optical disc apparatus using the PLL circuit 8.
[0011]
[Problems to be solved by the invention]
  The conventional sample servo CAV type disk storage medium described above has a track corresponding to the same center angle even though the outer track length corresponding to the same center angle of the disk is longer than the inner track length. The amount of data stored in is the same.
  Here, when data is recorded in the outer track, the data is stored by increasing the frequency of the clock for recording. On the other hand, when data is stored in the inner track, the frequency of the clock is decreased. There is a demand for recording almost the same data for the same track length both at the outer periphery and the inner periphery.
[0012]
  In response to this request, for example, the disk is used by dividing it into a plurality of regions (zones) in the radial direction,ThemA method of increasing the storage capacity of a disk by changing the frequency of a clock for recording data for each zone and recording almost the same amount of data for the same track length on the entire surface of the disk has been developed.
[0013]
  Such a recording method is called MCAV (Modified CAV) system or zone CAV system.
  In the MCAV system, optimization is performed for each zone in order to maximize the storage capacity of the disk.
  For this reason, the number of segments included in one sector and the amount of data stored in one segment are different.
[0014]
  A conventional PLL circuit corresponding to the CAV method generates a clock signal having substantially the same frequency on the entire disk surface, and synchronizes this clock signal with an RF signal corresponding to a clock pit formed on the disk. ing.
  Therefore, there is a problem in that it cannot be used as it is for recording and reproduction of an MCAV system disk that requires a clock with a different frequency for each zone of the disk.
[0015]
  It is possible to perform MCAV disk recording and reproduction using a frequency variable PLL circuit.
  However, as described above, since the number of segments included in one sector is different for each zone in the MCAV system disk, the number of bits included in one segment is obtained by table search or calculation, and each time the zone to be accessed changes. Therefore, it is necessary to make a setting corresponding to the zone in the PLL circuit.
[0016]
  In addition, since the correspondence relationship between the segment and sector and the bit count differs from zone to sector in each zone, it is necessary to perform recording and reproduction processing always taking this correspondence into consideration when recording and reproducing data.
  For this reason, the PLL described abovecircuitToParameters indicating the segment and sector, and the relationship between these and bit countWhen processing such as setting is performed by arithmetic processing in a control device of a disk device that performs general processing relating to data recording and reproduction, there is a problem that the load becomes large and eventually the performance of the disk device is reduced.
[0017]
  The present invention has been made in view of the above-mentioned problems of the prior art, and when recording and reproducing an MCAV disc,Divided in the radial directionProcessing amount related to setting to PLL circuit such as different number of segments per sector for each zone, and association of sector, segment, and bit countParameter settings, etc.An object of the present invention is to provide a PLL circuit capable of reducing the amount of processing and a disk device suitable for recording and reproduction of an MCAV system disk using the PLL circuit.
[0018]
[Means for Solving the Problems]
  According to the present invention, the timing of recording or reproducing data is controlled for each predetermined range using a servo clock common to the disk in which data is recorded at different frequencies for each predetermined range in the radial direction, A disk device having data management means for recording or reproducing data by managing different sectors and bits for each predetermined range using a data clock corresponding to each predetermined range;
  The data management means, for each of the predetermined ranges, based on a count value of a first counter indicating the order of sectors of the disk and a count value of a second counter indicating the order of bits in the sector, First generating means for generating a data clock reference signal, setting means for setting a division ratio corresponding to the predetermined range in the second counter, and a third counter indicating the order of the segments of the disk And a second generation means for generating a servo clock reference signal based on the count value of the fourth counter indicating the order of bits in the segment, and the reference signal of the data clock and the servo clock And a phase correction means for correcting a phase error with respect to the reference signal, and a data clock for generating the data clock based on the corrected phase error. Tsu comprising a click generating means, a
  When the second counter counts the data clock and asserts a carry signal, the first counter performs counting,4th counterCounts the servo clock and asserts a carry signal.Third counterIs provided that is configured to perform counting.
[0019]
  Preferably, the data management means includes compensation means for compensating for a delay time required for recording or reproduction on the disk using a data clock corresponding to each of the predetermined ranges.
[0020]
  AlsoPreferably, the compensation means sets the time required for the delay as a predetermined period of the servo clock, andDelay timeCompensate.
[0021]
  The disk device of the present invention manages the timing of data recording or reproduction for each predetermined range by using a servo clock common to the disks in which data is recorded at different frequencies for each predetermined range in the radial direction. And data management means for recording or reproducing data by managing different sectors and bits for each predetermined range using a data clock corresponding to each predetermined range.
  The data management means, for each of the predetermined ranges, based on a count value of a first counter indicating the order of sectors of the disk and a count value of a second counter indicating the order of bits in the sector, First generating means for generating a data clock reference signal, setting means for setting a division ratio corresponding to the predetermined range in the second counter, and a third counter indicating the order of the segments of the disk And a second generation means for generating a servo clock reference signal based on the count value of the fourth counter indicating the order of bits in the segment, and the reference signal of the data clock and the servo clock And a phase correction means for correcting a phase error with respect to the reference signal, and a data clock for generating the data clock based on the corrected phase error. Tsu includes a click generating means.
[0022]
  When the second counter indicating a count value indicating the order of bits in the sector counts the data clock and asserts a carry signal, the first counter counts a count value indicating the order of the sectors on the disk. I do.
  The first generating means for generating the data clock reference signal is based on the count value of the first counter indicating the order of the sectors of the disk and the count value of the second counter indicating the order of the bits in the sectors. The data clock reference signal is generated.
  Counting the count value indicating the order of the segments of the disk;4th counterCounts the count value indicating the order of bits in the segment when the servo clock is counted and the carry signal is asserted.Third counterDoes the counting.
  The second generating means for generating the servo clock reference signal is based on the count value of the third counter indicating the order of the segments of the disk and the measured value of the fourth counter indicating the order of the bits in the segments. To generate a servo clock reference signal.
  The phase correction unit corrects a phase error between the servo clock reference signal generated by the second generation unit and the servo clock reference signal generated by the first generation unit.
  The data clock generation unit generates the data clock based on the phase error corrected by the phase correction unit.
[0023]
  Preferably, a delay time required for recording or reproduction on the disk is compensated by using a data clock corresponding to each predetermined range.
[0024]
  Preferably, the time required for the delay is set as a predetermined period of the servo clock to compensate for the delay time.
[0025]
【Example】
  The first embodiment of the optical disk apparatus of the present invention will be described below.
  FIG. 1 is a diagram showing a configuration of a disc recording / reproducing apparatus 1 of the present invention.
  The disk recording / reproducing apparatus 1 is a magneto-optical device.(MO)The apparatus records data on the disk 10 and reproduces data recorded on the magneto-optical disk 10, and is particularly characterized by the DCK PLL circuit 5.
  Unless otherwise specified, each signal of the disk recording / reproducing apparatus 1 is positive logic.
[0026]
  In FIG. 1, a magneto-optical disk 10 is a recording medium used for the disk recording / reproducing apparatus 1, and data is recorded by a magneto-optical action, and the recorded data is read out.
  The magneto-optical disk 10 is rotated at, for example, 1800 rpm, and data is recorded and reproduced.
  The CPU 6 includes, for example, a general-purpose microprocessor or a digital signal processor (DSP) for signal processing and peripheral circuits such as a ROM and a RAM. The CPU 6 generally performs processing related to the entire disk recording / playback apparatus 1 and data recording / playback. Etc.
[0027]
  The magnetic head (MH) 11 converts the data recorded on the magneto-optical disk 10 into a magnetic signal and applies it to the recording position of the magneto-optical disk 10.
[0028]
  Data recording in the disk recording / reproducing apparatus 1 is performed by irradiating a magneto-optical disk 10 with a laser beam from a pickup unit (PU) 12 to apply heat to a position where data is recorded, and further using a magnetic head 11 to generate a magnetic field at the position. This is done by reversing the direction.
[0029]
  The pickup unit 12 includes a laser light emitting element (not shown) and a plurality of light receiving elements.Laser light emitting elementEach magneto-optical disk 10 is irradiated with a laser beam to receive each light receiving element.From the magneto-optical disk 10The reflected laser beam is converted into an electrical signal.
  A signal from each light receiving element is used for reproduction of data recorded on the magneto-optical disk 10, clock reproduction used for data recording, reproduction, and the like.
[0030]
  The reproduction amplifier 13 amplifies the focus servo signal from the magnetic head 11 and inputs it to the focus servo circuit (FoErr) 16.
  The reproduction amplifier 14 is a wobble from the magnetic head 11.Pit (wobbling pit)Embossed corresponding to etc.pitThe reproduction signal (PPRF) is amplified and input to the analog signal processing circuit (ASP) 19 through the switch 18.
  The reproduction amplifier 15 amplifies the MO reproduction signal used for reproducing the data stored in the magneto-optical disk 10 and inputs it to the analog signal processing circuit 19.
[0031]
  The focus servo circuit 16 processes the output signal of the reproduction amplifier 13 to detect a laser beam focus error, and moves the pickup unit 12 in a direction perpendicular to the surface of the magneto-optical disk 10 based on the focus error signal. A correction signal is generated, and focus control of the laser beam applied to the magneto-optical disk 10 through the drive amplifier 17 is performed.
[0032]
  The switch 18 is synchronized with a signal reproduced from the magneto-optical disk 10.Embossed pit playback signalPPRF and magneto-optical RF signal MORFEither one is selected and input to the circuits after the A / D conversion circuit 20.
  That is, the switch 18 selects the PPRF signal side when the pickup unit 12 reproduces the servo area signal on the track of the magneto-optical disk 10, and selects the MORF signal when the data area is selected. select.
[0033]
  The A / D converter circuit 20 synchronizes with the servo clock signal (SCK) or the data clock signal (DCK) selected by the switch 29 in the digital format. Convert to a signal.
  The tracking error circuit 21 is converted by the A / D conversion circuit 20Embossed pit playback signal PPRFA tracking error is detected based on the tracking error signal, a tracking correction signal for moving the pickup unit 12 in the radial direction with respect to the surface of the magneto-optical disk 10 is generated based on the tracking error signal, and laser beam irradiation is performed via the drive amplifier 22. Control for adjusting the position to the track center line of the magneto-optical disk 10 is performed.
[0034]
  An address reproducing circuit (Add) 23 reproduces the track number and sector number of the magneto-optical disk 10 being accessed by the magnetic head 11 and the pickup unit 12 and passes them to the CPU 6.
  The pattern detection circuit (Pat) 24 is shown in FIG.Pit playback signal (data) PRDetectPattern signal PATGenerated and described aboveServo clock (SCK)PLL circuit, that is, A / D conversion circuit 20,Phase errorDetection circuit (PE) 25, LPF 27, andVoltage controlled oscillatorThe loop by (VCO) 28 is controlled.
[0035]
  Phase error detection circuit (PE) 25 is embossedPit detection signalAnd servo clock signal (SCK)phaseDetect errors.
  LPF27It is called a low-pass filter or loop filter,The output signal of the phase error detection circuit 25 is filtered, a frequency component equal to or lower than a predetermined frequency is passed, and voltage control is performed.TypeInput to the oscillation circuit (VCO) 28.
[0036]
  The voltage controlled oscillation circuit 28 generates a servo clock signal (SCK) having a frequency corresponding to the output signal voltage of the LPF 27.
  The phase error detection circuit 25, the LPF 27, and the voltage controlled oscillation circuit 28 constitute a PLL circuit for generating a servo clock signal (SCK).
[0037]
  Data clock (DCK)The PLL circuit 5 generates a data clock signal (DCK) used for reading and writing data from the magneto-optical disk 10 and other timing signals used in the disk recording / reproducing apparatus 1.
  The configuration of the DCK PLL circuit 5 will be described later with reference to FIG.
[0038]
  The demodulation circuit (DEM) 26 isMagneto-optical (MO)Data recorded on the magneto-optical disk 10 is demodulated from the RF signal.
  The laser pulse generation circuit (PG) 30 generates a writing laser pulse signal for controlling the laser light emitting element of the pickup unit 12 at the time of data writing based on the data clock signal (DCK).
[0039]
  The timing generation circuit 33Data clock (DCK)A data control signal is generated based on the bit count (bitCNT) signal and the sector count (SctCNT) signal generated by the PLL circuit 5 for use, and is passed to the CPU 6.
  The command latch circuit (CMDL) 34 latches an instruction from the CPU 6.
  The pulse generation circuit (PG) 30 generates a laser pulse signal used for generating a laser control signal for controlling the laser light emitting element of the pickup unit 12 and inputs the laser pulse signal to the gate circuit 31.
[0040]
  The gate circuit (Gat) 31 includes a command held by the command latch circuit 34 and a read gate generated by the timing generation circuit (TG) 53 of the DCK PLL circuit 5 for the laser pulse signal from the pulse generation circuit 30. A logical operation is performed according to the signal and the write gate signal (WGate, RGate) to generate a laser control signal.
  There are three types of laser control signals: pulse generation, continuous light emission, and no light emission.
[0041]
  The laser drive circuit (LD) 32 drives the laser light emitting element of the pickup unit 12 based on the laser control signal generated by the gate circuit 31.
  Although not shown in FIG. 1, the laser drive circuit 32 generates a high-frequency signal used when reading out data stored in the magneto-optical disk 10 and a circuit for controlling the power supplied to the laser light emitting element. Further, a circuit for superimposing on the laser control signal is further provided, and power control supplied to the laser light emitting element and superposition of the high frequency signal are performed.
[0042]
  The modulation circuit (MOD) 35 modulates data to be recorded on the magneto-optical disk 10 and converts it into a recording signal in a format recordable on the magneto-optical disk 10.
  The magnetic head drive circuit (MD) 36 drives the magnetic head 11 based on the recording signal generated by the modulation circuit 35.
[0043]
  The configuration and operation of the DCK PLL circuit 5 will be described below.
  FIG. 2 is a diagram showing the configuration of the DCK PLL circuit 5 of the present invention.
  In FIG. 2, a first bit counter (bitCNT) 51 and a segment counter (SegCNT) 52 are counter circuits that count servo clock signals (SCK), and have a relationship between a lower counter and an upper counter, respectively. .That is, the first bit The counter 51 is a lower counter, and the segment counter 52 is an upper counter. The relationship between the lower counter and the upper counter will be described later in relation to the description of the operation of the DCK PLL circuit 5.
[0044]
  FirstThe bit counter 51 and the segment counter 52 are output from the pattern detection circuit 24.Pattern signal PATCounts when is asserted.
  Although not shown for simplification of illustration, each counter of the DCK PLL circuit 551, 52, 58, 59, 60The count value is configured to be read from the CPU 6.
[0045]
  The first timing generation circuit 53 includes a write gate signal (WGate), a read gate signal (RGate) signal (R / WGate), a servo control signal, an address control signal, and a reference signal for the servo clock signal (SCK). A timing signal for a servo clock signal (SCK) is generated.
  The second bit counter 58 is a counter circuit that counts the data clock signal (DCK), and the count value is changed for each zone by the CPU 6.
  The third bit counter 59 and the sector counter (SctCNT) 60 are counter circuits that count the data clock signal (DCK).ThirdThe bit counter 59 and the sector counter 60 are in a relationship of a lower counter and an upper counter, respectively.That is, the third bit counter 59 is a lower counter, and the sector counter 60 is an upper counter. The relationship between the lower counter and the upper counter will be described later in relation to the description of the operation of the DCK PLL circuit 5.
[0046]
  The second timing generation circuit 54SecondBased on the count value of the bit counter 58 and the W / RGate signal input from the timing generation circuit 53, the data clock signal (DCK)Reference signalVarious signals such as are generated.
  The phase comparison circuit 55 is a reference signal for the data clock signal (DCK) input from the timing generation circuits 53 and 54, respectively.WhenServo clock signal (SCK) reference signalWithThe phases are compared, and an error signal is input to the LPF 56.
[0047]
  The LPF 56 corrects the phase of the error signal output from the phase comparison circuit 55.
  The voltage controlled oscillation circuit (VCO) 57 generates a clock signal (data clock signal (DCK)) having a frequency corresponding to the voltage of the signal output from the LPF 56.
[0048]
  The logic circuits 61 to 63 are respectivelySecondA logical operation is performed on the data enable signal (dataen), segment initial signal (initseg), and rotation initial signal (initrev # 1) output from the timing generation circuit 54, and a reset signal (rst # 2) and an enable signal (en) are output. Generate.
  The logic of the logic circuits 61 to 63 is as shown in FIG.
[0049]
  The operation of the DCK PLL circuit 5 will be described below.
  The servo clock signal (SCK) generated by the PLL circuit for the servo clock signal (SCK) is supplied from the PLL circuit for DCK 5.FirstIt is counted by the bit counter 51 and the segment counter 52.
  Here, the servo clock signal (SCK) is the same as the data clock signal (DCK) in zone 0.FirstEach time the bit counter 51 counts the servo clock signal (SCK) 320 times, the bit counter 51 asserts the ripple carry (rc) signal and inputs it to the segment counter 52 as an enable signal (en).
[0050]
  The segment counter 52 counts the servo clock signal (SCK) only when the enable signal (en) is asserted.
  Therefore,FirstThe count value of the bit counter 51 represents a bit in the segment, and the count value of the segment counter 52 represents a segment.
[0051]
  The count value of the first bit counter 51 andThe count value of the segment counter 52 is input to the timing generation circuit 53.
  The timing generation circuit 53FirstBased on the count values of the bit counter 51 and the segment counter 52 and the servo clock signal (SCK), the R / WGate signal and the servo clock signal (SCK) are divided by eight.Servo clock (SCK)A reference signal or the like is generated.
[0052]
  SecondThe bit counter 58 is a data clock signal (DCK) according to the zone information set by the CPU 6.(8 + n) frequency division to generate a DCK reference signal.
  Here, n is a zone number (0 to 8) of the magneto-optical disk 10 accessed by the disk recording / reproducing apparatus 1.
[0053]
  SecondThe timing generation circuit 54 generates a rotation initial signal (initrev) generated once for each rotation of the magneto-optical disk 10 based on the W / RGate signal input from the timing generation circuit 53 and the data clock signal (DCK). # 1) A segment initial signal (initseg) indicating the servo area of the segment and a data enable signal (dataen) indicating the data area of each segment are generated.
[0054]
  These signals, andThirdThe ripple carry (rc) signal asserted every time the bit counter 59 counts the data clock signal (DCK) 5120 times is logically operated by the logic circuits 61 to 63, andThirdFrom the logic circuit 62, the count of the bit counter 59 is permitted (en).ThirdThe count of the bit counter 59 is reset (rst), a signal for enabling the count of the sector counter 60 (en), and a signal for resetting the sector counter 60 from the logic circuit 63 (rst # 2) are input.
[0055]
  These signals are inputThirdThe bit counter 59 receives the data clock signal (DCK) in the data area.ThirdWhen the ripple carry of the bit counter 59 itself is not asserted, it counts 5120 times.
  Here, in the magneto-optical disk 10 of the first embodiment, as described later, 5120-bit data is recorded in one sector.ThirdThe count value of the bit counter 59 represents the order of bits in the sector.
[0056]
  In addition, the sector counter 60 is used in the servo area of the magneto-optical disk 10.ThirdSince the counting is performed when the bit counter 59 asserts the ripple carry, the count value of the sector counter 60 represents the order of the sectors.
[0057]
  FirstTiming generation circuit 53Servo clock (SCK) reference signal output fromandSecondOutput from the timing generation circuit 54Data clock (DCK)The reference signal is phase-compared by the phase comparison circuit 55, and the phase comparison result(Phase error)Is input to the LPF 56.
  The voltage controlled oscillation circuit 57 generates and outputs a data clock signal (DCK) having a frequency corresponding to the output voltage of the LPF 56.
[0058]
  As mentioned above,Unlike the conventional PLL circuit, the present inventionData clock (DCK) of the first embodimentPLL circuit 5 from CPU 6SecondA data clock signal (DCK) in the zone can be generated only by setting a frequency division ratio corresponding to the zone in the bit counter 58.
  Furthermore, the CPU 651, 52, 58, 59, 60Since the relationship between different sectors, segments, and bits can be managed in each zone by reading the value of, the processing for managing these relationships, which was conventionally required, is unnecessary.
  Therefore, the processing load on the CPU 6 can be reduced.
  As mentioned aboveThirdThe timing of the ripple carry signal, the rotation initial signal (initrev), etc. of the bit counter 59 will be described later with reference to FIG.
[0059]
  Hereinafter, the MCAV system and the operation of the disk recording / reproducing apparatus 1 will be described with reference to the drawings.
  First, the MCAV system will be described.
  FIG. 3 is a diagram for explaining the relationship between the radial position of the magneto-optical disk and the track length.
  In FIG. 3, the outer peripheral track shown in FIG. 3A is at a position r in the radial direction from the center in the magneto-optical disk and corresponds to the central angle θ.
  The inner track shown in (B) is located at r / 2 in the radial direction from the center, and corresponds to the center angle θ.
[0060]
  A conventional CAV type magneto-optical disk is rotated at the same rotational speed when accessed at any location, and a recording / reproducing clock having the same frequency is used. A certain amount of data was recorded.
  That is, since the outer track and the inner track correspond to the same central angle, the outer track and the inner track are twice the length of the inner track. Record the amount of data.
[0061]
  On the other hand, as described below, the MCAV type magneto-optical disk is rotated at the same rotational speed when accessed at any location, and the magneto-optical disk is divided into a plurality of areas (zones). By changing the frequency of the data clock signal (DCK) for recording / reproducing data for each zone, substantially the same data is recorded on the entire surface of the magneto-optical disk for the same track length.
[0062]
  FIG. 4 is a diagram for explaining zone division of the magneto-optical disk 10.
  In FIG. 4, the magneto-optical disk 10 is divided into 9 zones 0 to 8 for the same length in the radial direction. Here, the radius of the inner circumference of zone 0 and the radius of the inner circumference of zone 8 are respectively r / 2, r.
[0063]
  Here, the magneto-optical disk 10 is rotated at a constant rotational speed when accessed at any location. In the zone 8, the data clock signal having a frequency 16/8 times that of the data clock signal (DCK) in the zone 0 is obtained. (DCK) is used to write and read data.
[0064]
  Further, in zone 8, there is a relationship that data is written and read using a data clock signal (DCK) having a frequency 16/8 times that of the data clock signal (DCK) in zone 0. To establish. That is, in a certain zone, data is written and read using a data clock signal (DCK) having a frequency proportional to the ratio of the radius of the inner circumference to the radius of the inner circumference of zone 0. .
[0065]
  This relationship will be described with reference to Table 1.
[Table 1]
  Table 1 shows the relationship between the data amount per segment for each zone (area) of the MCAV magneto-optical disk 10, the number of segments per sector, and the recording / reproducing frequency (fdck) for zone 0 in each zone. is there.
[0066]
  When data is read / written from / to the magneto-optical disk 10 by the sample servo system, the segments are provided corresponding to the central angle of the magneto-optical disk 10, so the data amount per segment of each zone and one sector There is a difference in the number of segments.
[0067]
  In the magneto-optical disk 10, user data is handled in units of 512 bytes. For example, user data includes 78 bytes of error correction code (ECC), extraction threshold value information, and reproduction clock phase correction information. Since 40 bytes are added, data of 640 bytes (5120 bits) per sector is recorded.
[0068]
  In the inner zone, the track length per segment is shortened even though the data amount per track length in the outer zone is the same, so the data amount per segment is reduced.
  Further, since the opposite relationship is established in the outer zone, the relationship shown in the column of data per segment in Table 1 is established.
  Here, the data amount corresponding to each zone is described as 320 = 40 × 8 in order to clearly show the correspondence with the recording frequency.
[0069]
  In addition, while it is necessary to record the same amount of data in one sector, the data amount per segment is smaller in the inner zone, so the number of segments per sector is larger in the sector in the inner zone. Become.
  Further, since the opposite relationship is established in the outer zone, the relationship shown in the column of the number of segments per sector in Table 1 is established.
  Further, since the recording (reproducing) frequency of each zone is proportional to the radius of the inner circumference of the zone as described above, the relationship shown in the column of recording frequency (fdck) in Table 1 is established.
[0070]
  FIG. 5 is a diagram showing the segment configuration of the magneto-optical disk 10 and the configuration of the servo area of each segment.
  FIG. 6 is a diagram showing the relationship between the waveform of the signal obtained from the servo area and the clock.
  5A shows the segment configuration of zone 0, FIG. 5B shows the segment configuration of zone 8, and FIG. 5C shows the configuration of pits in the servo area of each segment.
[0071]
  As shown in FIGS. 5A and 5B, each sector is composed of a header segment and a data segment, and each data segment includes a servo area in which signals used for tracking control, focus control, etc. are recorded, It consists of a data area where the data body is recorded.
[0072]
  Each servo area has a clock pit (CP) provided on the center of the track and a wobble pit (WP) provided at a position shifted from the center of the track, and the disc recording / reproducing apparatus 1 obtains from these pits. The clock is regenerated based on the received signal to generate a servo clock signal (SCK) and a data clock signal (DCK), and focus control and tracking control are performed.
[0073]
  These pits in the servo area are provided at the position shown in the figure with the first bit of the servo area as the first bit, and the reflected laser beam from the tracking area is converted into an electrical reproduction signal as shown in FIG. Converted.
  It should be noted that the relationship between each point indicated by a0 to a2, b1 to b2, and c0 to c2 and the servo clock signal (SCK) in this reproduced signal is as shown in the figure.
  Prior to the data body (DATA), 6-bit PR data is written in the data area, and PO data is placed after the data body.
[0074]
  Hereinafter, the operation of the disk recording / reproducing apparatus 1 will be described.
  FIG. 7 is a timing chart showing the timing of the W / RGate signal and the laser control signal.
  FIG. 8 is a timing chart showing the timing of the dataen signal and the data clock signal (DCK).
  7 and 8, the reference signal for write data is shown redundantly to clarify the timing relationship in both figures.
  FIG. 9 is a timing chart showing the timing of the write data reference signal, the read data reference signal, and the like.
[0075]
  The operation when the disk recording / reproducing apparatus 1 writes data to the magneto-optical disk 10 will be described with reference to FIGS.
  In FIG. 7, a read gate (RGate) signal for writing is asserted at the timing of reading a servo area signal.
  On the other hand, the write gate (WGate) signal is asserted at the timing of accessing the data area in synchronization with the WGate reference signal.
  Note that the WGate reference signal is a signal used in the timing generation circuit 53 and is not shown in FIGS.
[0076]
  The laser power control signal (LDP) signal isData clock (DCK)This signal is generated by the timing generation circuit 53 of the PLL circuit 5 for controlling the power supplied from the laser drive circuit 32 to the laser light emitting element of the pickup unit 12.
  When the LDP signal is asserted, the laser drive circuit 32 generates a laser control signal (LDD) for generating a pulse, increases the power supplied to the laser light emitting element to increase the intensity of the laser beam, and increases the intensity of the laser beam. The laser beam for writing to is output.
[0077]
  Accordingly, when the write gate signal (WGate) is asserted to the pickup unit 12, a pulsed LDD signal having high power is input, so that the laser light emitting element emits a pulsed laser beam having a high intensity. 10 irradiation.
  Data is written to the magneto-optical disk 10 by the magneto-optical action of the write laser beam and the write (MHD) signal applied from the magnetic head 11.
[0078]
  On the other hand, when the LDP signal is negated, the laser drive circuit 32 generates an LDD signal for continuous light emission, reduces the power supplied to the laser light emitting element to weaken the intensity of the laser beam, and supplies the magneto-optical disk 10. The laser beam for reading is output.
[0079]
  Therefore, when the readout gate signal (RGate) signal is asserted to the pickup unit 12, since the continuous LDD signal with low power is input, the laser light emitting element emits a continuous readout laser beam with low intensity. The pickup unit 12 can read out the synchronization signal for the servo area by irradiating the magneto-optical disk 10 and the reflected light.
  The disk recording / reproducing apparatus 1 synchronizes when writing data to the magneto-optical disk 10 based on the synchronization signal.
[0080]
  In FIG. 8, data setup is the time required for processing of input / output of write data, modulation of write data in the modulation circuit 35, and the length of this data setup depends on the data clock signal (DCK). The timing relationship with WGate is different for each zone.
  Therefore, for example, when a shift register is provided in the modulation circuit 35 and the gate circuit 31, the transmission of the LDD signal and the MHD signal shown in FIG. 7 is always delayed from the write data reference signal by the servo clock signal (SCK) for a certain period. To be done in.
[0081]
  For example, if the length of data setup is 8 cycles of the data clock signal (DCK), the data setup time is set to 8 cycles of the servo clock signal (SCK), so that the input of write data in all zones A time delay between the output and the output of the LDD signal and the MHD signal can be absorbed.
  That is, when this delay is a delay corresponding to k cycles of the data clock signal (DCK), the data setup time is set to be equal to k cycles of the data clock signal (DCK).
[0082]
  That is, in the zone 0, the period of the servo clock signal (SCK) is equal to the period of the data clock signal (DCK). In this example, if the data setup time for 8 periods of the servo clock signal (SCK) is provided, the data is stored. There is no lack.
  In other than zone 0, the cycle of the data clock signal (DCK) is shorter than the cycle of the servo clock signal (SCK), so that the data setup time for 8 cycles of the servo clock signal (SCK) is set as in the case of zone 0. If provided, data will not be lost.
[0083]
  Therefore, the write data reference signal is asserted at a timing earlier by eight cycles with the servo clock signal (SCK) than the DCK reference signal.
  Considering similarly the write data reference positions 1 and 2 shown in FIG. 9, the interval between the write data data reference position 1 and the data reference position 2 is equal to the time when WGate is asserted, that is, the length of the data area. Become.
[0084]
  Further, if the delay time between the write data reference signal and the write gate signal (WGate) is a servo clock signal (SCK) 8n (n is an integer), the servo clock is used when the data enable signal (dataen) is asserted and negated. Since the phase of the signal (SCK) and the data clock signal (DCK) coincide, the phase difference between the dataen signal and the servo clock signal (SCK) can be absorbed by performing processing synchronized with the data clock signal (DCK). .
  The data enable signal (dataen) at the time of writing shown in FIG. 8 is a signal generated as described above.
[0085]
  Hereinafter, the operation in the case of reading data from the magneto-optical disk 10 in the disk recording / reproducing apparatus 1 will be described.
  In the case of writing data to the magneto-optical disk 10, write data is prepared earlier by the time indicated in the data setup for the write gate signal (WGate), but the analog signal processing circuit 19, A / D, on the contrary, is read at the time of reading. It takes time for processing in the conversion circuit 20 and the demodulation circuit 26, and a delay occurs between the time when the signal is read from the magneto-optical disk 10 and the time when data is output.
[0086]
  Accordingly, when reading data, contrary to the case of writing data, a data enable signal (dataen) is generated with a data delay as shown in FIG.
  The length of this data delay is 8n cycles of the servo clock signal (SCK) in the first embodiment, similar to the data setup time at the time of writing.
[0087]
  FIG. 10 is a timing chart showing the timing of the segment end signal, the count value of the sector counter 60, and the like.
  In FIGS. 9 and 10, the timings of the servo area and the data area are shown redundantly to clarify the relationship between the timings in both figures.
  FIG.FIG. 5 is a diagram illustrating timings of signals generated by a timing generation circuit 54 of the DCK PLL circuit 5.
  In FIG. 10, a black portion indicates a range where data is not recorded.
[0088]
  The segment initial signal (initseg) is asserted at the position of the servo area of each segment, and the rotation initial signal (initrev) is asserted once per rotation of the magneto-optical disk 10.
  ThirdThe bit counter 59 and the sector counter 60 are reset when the rotation initial signal (initrev) is asserted and the segment initial signal (initseg) is asserted.
[0089]
  The ripple carry signal isThirdAsserted when the bit counter 59 counts DCK 5120 times, this signal is asserted, and the sector counter 60 is counted up when the segment initial signal (initseg) is asserted.
  here,ThirdThe count value of the bit counter 59 is shown, for example, in the case of the zone 7, and in this case, as shown in black in the figure, the data from the end of the sector to the data area of the next sector is not used for data storage. There is a case.
  This is because, in the MCAV system, the end of the sector, that is, the 5120th bit is not necessarily the end of the segment at the data clock (DCK).
[0090]
  The second embodiment of the present invention will be described below.
  Data clock (DCK) of the second embodimentPLL circuit 7 forData clock (DCK) of the first embodiment described aboveThe initialization method of the sector counter 60 of the PLL circuit 5 is changed.
  FIG. 11 is a diagram showing a configuration of the DCK PLL circuit 7 in the second embodiment.
  In FIG. 11, the logic circuit 70 performs an AND operation on the segment initial signal (initseg), the load sector signal (ldsct), and the enable load signal (enload), and generates a reset signal for the sector counter 60.
[0091]
  The comparison circuit (CMP) 72 compares the comparison segment values set in the segment counter 52 and the register 73, and asserts an enable load signal (enload) if they match.
  The register 73 holds a comparison segment value set by the CPU 6, a load segment signal (ldseg) that is a bit signal, and an enable load signal (enload).
  The other parts of the other DCK PLL circuit 7 are the same as the parts assigned the same reference numerals for the DCK PLL circuit 5.
[0092]
  The operation of the DCK PLL circuit 7 will be described below.
  The CPU 6 sets the comparison segment value, the load segment signal (ldseg), and the enable load (enload) in the register 73.
  When this enable load (enload) is asserted (logical value 1), the following operation is performed.
  The segment number counted by the segment counter 52 is compared with the comparison segment value stored in the register 73, and the load sector signal (ldsct) is asserted when they match.
[0093]
  In this case, when the segment initial signal (initseg) is asserted, the load signal (ld) is asserted, and the sector number stored in the register 73 is set in the sector counter 60.
  With this configuration, when the disk recording / reproducing apparatus 1 accesses a predetermined zone of the magneto-optical disk 10, a rotation initial signal (initrev) that is asserted only once every time the magneto-optical disk 10 makes one rotation. Data can be recorded and reproduced on the magneto-optical disk 10 without waiting.
[0094]
  Others mentioned above,The optical disk apparatus of the present invention can take various configurations, for example, the rotational speed of the magneto-optical disk 10 is 3600 rpm.
[0095]
【The invention's effect】
  As described above, according to the optical disc apparatus of the present invention, the control device of the disc recording / reproducing apparatus isData clock (DCK)It is possible to generate clock signals having different frequencies necessary for recording / reproduction of the MCAV type magneto-optical disk only by setting the count value in the PLL circuit for use.
  In addition, since the DCK PLL circuit counts the sectors, segments, and bits of the magneto-optical disk accessed by the disk recording / reproducing apparatus, the control circuit of the disk recording / reproducing apparatus does not need to manage them.
  Therefore, it is possible to reduce the addition of the control circuit of the disk recording / reproducing apparatus, and the development of software for operating the disk recording / reproducing apparatus is simplified.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a disc recording / reproducing apparatus of the present invention.
FIG. 2 of the present inventionOf the first embodimentIt is a figure which shows the structure of the PLL circuit for DCK.
FIG. 3 is a diagram for explaining a relationship between a radial position of a magneto-optical disk and a track length.
FIG. 4 is a diagram for explaining zone division of a magneto-optical disk.
FIG. 5 is a diagram showing a segment configuration of a magneto-optical disk and a configuration of a servo area of each segment.
FIG. 6 is a diagram illustrating a relationship between a waveform of a signal obtained from a servo area and a clock.
FIG. 7 is a timing chart showing timings of a write gate signal (WGate), a laser control signal, and the like.
FIG. 8 is a timing chart showing timings of a dataen signal, a data clock signal (DCK), and the like.
FIG. 9 is a timing chart showing timings of a write data reference signal, a read data reference signal, and the like.
FIG. 10 is a timing chart showing timings such as a segment end signal and a count value of a sector counter.
FIG. 11Of the present inventionPLL times for DCK in the second embodimentRoadIt is a figure which shows a structure.
FIG. 12 is a diagram showing a configuration of a conventional PLL circuit used in an optical disc apparatus that reproduces data recorded on an optical disc by a sample servo CAV (constant angular velocity) method.
[Explanation of symbols]
  1... Disc recording / playback devices
      5, 7... PLK circuit for DCK
            51, 58, 59 ...1st to 3rdBit counter
            52 ... Segment counter
            53, 54 ... Timing generation circuit
            55 ... Phase comparison circuit, 56 ... LPF
            57... Voltage controlled oscillation circuit
            60 ... Sector counter
            61-63, 70 ... logic circuit
            72: Comparison circuit, 73: Register
      6 ... CPU
      10: magneto-optical disk, 11: magnetic head
      12 ... Pickup unit, 13-15 ... Reproduction amplifier
      16: Focus servo circuit, 17 ... Disc recording / reproducing device
      18, 29 ... switch, 19 ... analog signal processing circuit
      20 ... A / D conversion circuit, 21 ... Tracking error circuit
      22 ... Drive amplifier, 23 ... Address reproduction circuit
      24 ... pattern detection circuit, 25 ... phase error detection circuit
      26... Demodulator circuit, 27... LPF, 28.
      30 ... Pulse generation circuit, 31 ... Gate circuit,
      32 ... Laser drive circuit, 33 ... Timing generation circuit,
      34 ... Command latch circuit, 35 ... Modulation circuit
      36 ... Magnetic head drive circuit

Claims (3)

Data recording or reproduction timing management is performed for each predetermined range using a servo clock common to disks in which data is recorded at different frequencies for each predetermined range in the radial direction, and for each predetermined range. A disk device having data management means for recording or reproducing data by managing different sectors and bits for each of the predetermined ranges using corresponding data clocks,
The data management means includes
Based on the count value of the first counter indicating the order of the sectors of the disk and the count value of the second counter indicating the order of the bits in the sector, the reference signal of the data clock is set for each predetermined range. First generating means for generating;
Setting means for setting a frequency division ratio corresponding to the predetermined range in the second counter;
Second generating means for generating a servo clock reference signal based on a count value of a third counter indicating the order of segments of the disk and a count value of a fourth counter indicating the order of bits in the segment When,
Phase correction means for correcting a phase error between the reference signal of the data clock and the reference signal of the servo clock;
Data clock generating means for generating the data clock based on the corrected phase error, and
When the second counter counts the data clock and asserts a carry signal, the first counter counts, and when the fourth counter counts the servo clock and asserts a carry signal, the first counter counts . 3 counters are configured to count,
Disk unit. The data management means includes compensation means for compensating for a delay time required for recording or reproduction on the disc using a data clock corresponding to each of the predetermined ranges.
The disk device according to claim 1. The compensation means compensates the delay time by setting the time required for the delay as a predetermined period of the servo clock.
The disk device according to claim 2.

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