JPH063378B2 - Encoder output interpolation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention, when detecting a position or a rotation angle by an incremental encoder, digitalizes a quantization error of the detected information by electronic circuit processing. Type encoder output interpolation circuit.

A rotary encoder, a linear encoder, or the like is used to detect the position and speed of a motor or an object driven by the motor.

For example, a rotary encoder generates A-phase and B-phase sine wave signals having a phase difference of π / 2 depending on the rotation of the motor, and the frequency thereof is proportional to the rotation speed of the motor. Then, a position (displacement) signal and a velocity signal are detected from these A-phase and B-phase sine wave signals, for example, as shown in FIG.

In FIG. 8, M is a motor, RE is a rotary encoder, PG is a pulse generator that generates a pulse when a two-phase sine wave signal of A phase and B phase crosses zero volt, as shown in FIG. PD is a phase detector that gives the addition signal AD to the up / down counter UDC when the A-phase signal is advancing, and the subtraction signal SB when it is delayed. UDC is an up / down counter and is used for the pulse generator PG. The one that counts up or down the generated pulse, DA is the digital-analog converter, FVC is the pulse generator P
It is an FV converter that outputs a voltage according to the pulse frequency generated by G and generates a speed signal.

For example, if the motor M is rotating in the clockwise direction and gradually decelerates and the direction of rotation is reversed at time t ₀ , the rotary encoder RE first outputs A as shown in FIGS.
Two sine wave signals are generated in which the phase signal leads the B phase signal by π / 2. The phase detector PD detects this and
The addition signal AD is output to the down counter UDC. At this time, the pulse generator PG generates an up pulse UPP as shown in FIG. 11 every time the A-phase and B-phase sine wave signals cross zero volts, and inputs them to the up-down counter UDC and the FV converter FVC. To do.

Up / down counter UDC is up pulse UPP
Is counted up every time is input, this count value is DA converted by the DA converter, and becomes the position signal PS.

Therefore, as shown in FIG. 9, until the time t ₀ , the position signal P
S steps stepwise, and the velocity signal VS decays stepwise. After the time t _0, the rotation direction of the motor M is reversed, so
The A-phase signal lags the B-phase signal, this time the phase detector PD generates the subtraction signal SB, and the pulse generator PG outputs the first signal.
As shown in FIG. 1, a down pulse DNP is generated and the counter value of the up / down counter UDC is subtracted.
Therefore, as shown in FIG. 9, after time t ₀ , the position signal PS decreases stepwise and the speed signal VS increases stepwise in the negative direction.

According to the method shown in FIG. 8, the position signals PS,
It was not possible to obtain a position signal or a velocity signal in which both velocity signals VS are stepwise and smoothly change. By the way, even in the flat portion of the position signal PS and the speed signal VS in FIG. 9, the motor is actually rotating and the speed is also changing. That is, such a method has a drawback in that an instantaneous accurate position and velocity signal cannot be obtained.

[Conventional technology]

In order to improve the above-mentioned drawbacks, the applicant of the present invention has disclosed in JP-A-55-55.
As shown in Japanese Patent No. 76905, a method as shown in FIG. 10 has been proposed.

In FIG. 10, the phase A signal and B of the rotary encoder RE are shown.
The phase signal is transmitted to the pulse generator PG and the phase detector PD to output the up pulse UPP or the down pulse DNP, and the up / down counter UDC outputs the addition signal AD or the subtraction signal from the phase detector PD. It is the same as in FIG. 8 that addition or subtraction is performed by SB and this is analogized by the digital / analog converter DA.

However, in FIG. 10, the A-phase signal and the B-phase signal are transmitted to the slicer SL, the adder AAD, and the subtractor ASB. Slicer SL slices these signals at a certain level,
The square wave signals P and Q shown in FIG. 11 are converted, and the adder AAD and the subtractor ASB add or subtract these signals to obtain the (A + B) signal, (AB )
Output a signal. These (A + B) signal and (AB) signal are transmitted to the multiplexer MPX ₁ . By the way, the rectangular wave signals P and Q are input to the exclusive OR circuit EOR and the exclusive OR (PQ) is calculated. When the exclusive OR circuit EOR is "1", the multiplexer MPX ₁ is
The (A + B) signal is output in synchronism with the output pulse of the pulse generation circuit PG, and when it is "0", the (AB) signal is output. The output of this multiplexer MPX ₁ is D by the attenuator ATN.
It is attenuated to the voltage value of one step of the A converter DA. This becomes one input signal of the multiplexer MPX _{2, and} the other input signal of this multiplexer MPX ₂ is the attenuator ATN output from the inverter IN.
It becomes the inversion signal of. Therefore, the multiplexer MPX ₂
The output INPS of is shown by the dotted line in the signal shown as INPS in FIG. 11, and this is transmitted to the interpolator INP. By the way, the interpolator INP has the digital
The analog signal PS of the count value of the up / down counter UDC output from the analog converter DA (11th
(Indicated as step signals in the figure) are transmitted. Therefore, in this interpolator INP, the stepped analog signal PS and the multiplexer MPX ₂
Of the position signal PSS in which the discontinuity of the step signal PS is removed by adding the output INPS of
Is obtained.

When speed detection control is performed using this position signal PSS, for example, as shown in FIG. 12, adder / subtractors AD _{1 to} AD _{3 are used.}
And integrators INTG ₁ , INTG ₂ , amplifiers AP ₁ , AP ₂
And the like, and a signal I _i proportional to the motor drive current i is transmitted to the adder / subtractor AD ₁ and the position signal P
The SS is transmitted to the adder / subtractor AD ₃ . For example, when a DC motor is used as a drive motor, the motor armature current i
Is proportional to the angular acceleration, this current i is
The speed signal VSS is integrated by G ₁ and the speed signal VSS is further integrated by the integrator INTG ₂ to obtain the position signal PSS ′, which is compared with the smooth position signal PSS and the adder / subtractor AD ₃ . The speed signal VSS can be obtained by controlling so that this difference becomes zero.

[Problems to be solved by the invention]

Thus, by feeding back the position information obtained by the circuit of FIG. 10 and configuring the servo system, the limit cycle due to the quantization error can be prevented, and some effects are obtained. However, this circuit has many drawbacks in that it is difficult to reduce the size and cost of the device because there are many parts that perform analog signal processing.

In particular, it is necessary to digitize the servo system control device when using a microcomputer. Therefore, as shown in FIG. 13, the multiplexer MPX ₂
The output of is converted into a digital signal by the AD converter A / D,
It is necessary to interpolate this as a signal of the lower digit with respect to the upper digit which is counted and output from the up / down counter UDC, resulting in a complicated circuit configuration as shown in FIG. 13, which also reduces the size of the device and lowers the price. There is a problem that it is difficult to make it.

[Means for solving problems]

In order to solve the above problems, the encoder output interpolation circuit of the present invention includes an encoder that generates two-phase sinusoidal signals having a phase difference of π / 2 with each other according to movement or rotation of an object, In an object position detecting device equipped with a counting means for performing addition counting or subtraction counting according to the movement or rotation direction of an object during one cycle of each sine wave signal, interpolation smaller than the position information detectable by the counting means Storage means for outputting position information for use and analog / digital conversion means for converting each of the two-phase sinusoidal signals into digital quantities are provided, and when accessing the storage means based on these digital quantities, storage addresses are matrixed. And the row and column numbers are selected according to the information obtained by converting the two-phase sinusoidal signals into digital quantities. Means for outputting the interpolation position information from the storage means in accordance with these digital amounts, and based on this, the position information detected by the counting means is interpolated, and during one cycle of the sinusoidal signal. When the number of times counted by the counting means is n and the number of bits of the interpolation position information written in the storage means is m, a virtual circle in which the centers of the matrix overlap each other is taken into consideration. The plane angle of 360 ° at the center of
Introducing n × 2 ^m virtual sectors divided into 2 × 2 ^m equal parts, and assigning 2 ^m kinds of interpolation information to each of the n × 2 ^m sectors, and storing each of the matrices overlapping each sector. It is characterized in that the value of the interpolation information is stored in the address.

[Action]

In the present invention, the two-phase outputs of the encoder are A / D converted into digital amounts, and then these signals are stored in the ROM (Re
Since the interpolation data can be obtained based on the correspondence table written in advance in ROM by deriving it as the address input of (Ad Only Memory), the means for generating the interpolation data can be put together in an extremely compact form, and the encoder The interpolated data can be continuously generated without being affected by the fluctuations in the amplitude, offset, and phase difference of the two-phase sinusoidal signal, and accurate control can be performed.

〔Example〕

An embodiment of the present invention will be described with reference to FIGS. 1 to 7.

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is an explanatory view of a ROM state, FIG. 3 is an explanatory view of problems when the ROM of FIG. 2 is used, and FIG. R used in the examples
It is a block diagram of OM.

In the figure, 1 is a motor, and the motor M in FIG. 8 and FIG.
2 is an incremental rotary encoder that generates a sine wave A-phase signal and a B-phase signal having a phase difference of π / 2, and is of a motor shaft connected to the rotation shaft of the motor 1. A sensor configured to detect a rotation angle and corresponding to the rotary encoder RE, 3 is an analog-digital (A / D) conversion circuit for converting the sine-wave A-phase signal into a digital signal A'as described later,
Reference numeral 4 is an A / D conversion circuit for converting the B-phase signal of the sine wave into a digital signal B'as will be described later, 5 is a ROM in which data as shown in FIG. 2 is written, and 6 is a phase discrimination circuit. It is to determine which one of the A-phase signal and the B-phase signal is advancing, and corresponds to the pulse generator PG in FIGS. 8 and 10, and will be described in detail later. When the signal advances, the count-up signal up is "1". Conversely, when the B phase advances, the count-down signal dN is "1".
Becomes Reference numeral 7 is an up / down counter, which raises / lowers a pulse by the count-up signal up or count-down signal dN output from the phase discrimination circuit 6.
The counter U for counting is shown in FIGS. 8 and 10.
It corresponds to DC.

The A / D conversion circuit 3 outputs the A-phase signal as a digital signal in 16 steps from 0 to F, and its negative maximum value "-
Digital signal A'where 8 "is 0 and the maximum positive value is F
Is output. Similarly, the A / D conversion circuit 4 outputs the B-phase signal as a digital signal in 16 steps from 0 to F, and sets the negative maximum value "-8" to 0, and the maximum positive value. A digital signal B'having a value of F is output.

The ROM 5 holds data for interpolating the output of the up / down counter 7, and is shown in FIG. 2 (a).
The correspondence table shown in FIG. 2B is written based on the calculation rule shown in FIG. 2. In this example, 4-bit interpolation data corresponds to 256 addresses. Here, 1 in (A + B + 1) in the operation rule of FIG. 2 (a) is an addition to target the values in the table of FIG. 2 (b), and may be 0. It can be ignored as the number of bits is increased.

The phase discriminator 6 discriminates which of the A-phase signal and the B-phase signal is in the advanced phase based on the signals P and Q output from the ROM 5, and from the ROM 5 when A ≧ 0, P = “ 1 ", P =" 0 "when A <0, Q =" 1 "when B≥0, and Q =" 0 "when B <0. Therefore, in ROM 5, FIG.
P tables 5-2 and Q as shown in FIGS. 2 (c) and 2 (d), respectively, created by the same address as the ROM 5-1 in which the correspondence table to be the interpolation data shown in FIG. 2 (b) is written.
A table 5-3 is provided to output P and Q values in accordance with the A and B conditions. Instead of these FIG. 2 (c) and (d), the interpolation data of FIG. 2 (b) can be output as 6 bits, and 2 bits of them can be assigned to P and Q.

The phase discriminator 6 outputs the count-up signal up or the count-down signal dN as shown in the following Table 1 according to the A-phase signal and the B-phase signal input in this way. Then, these signals cause the up / down counter 7 to
The counting operation is performed in synchronization with the interpolation data INPS output from the ROM 5.

Here, the configuration of the phase discriminator 6 will be briefly described with reference to FIG. This phase discriminator includes four flip-flops FF1 to FF4, two inverters IN1 to IN2 and four AND circuits a1 to a4 as shown in FIG. 14 (a).
A rectangular signal output section, an up pulse output section composed of four AND circuits a5 to a8 and an OR circuit OR1 as shown in (b), and four AND circuits shown in (c). DN composed of the circuits a9 to a12 and the OR circuit OR2
It is composed of a pulse output unit and the like. The four flip-flops FF1 to FF4 shown in FIG.
Performs an input / output operation as shown in FIG. Here, J and K are input terminals, Q is an output terminal, and CL is a clock terminal. As shown in FIG. 14 (a), when signals P and Q are input, they are output from the inverters IN1 and IN2, and P output from AND circuits a1 to a4.
U is shown in (b) and (c) of the rising and falling signals of Q respectively.
Each AND circuit a5 of p pulse output section and dN pulse output section
By inputting a8 and a9 to a12 in the illustrated state, the up pulse and the dN pulse are obtained from the OR circuits OR1 and OR2, respectively. The relationship between the signals P and Q and their up pulse and dN pulse is as shown in FIGS. 14 (d) and 14 (e).

Next, the operation of FIG. 1 when the ROM 5 shown in FIG. 2 is used will be described.

When the motor 1 rotates, the output signal of the rotary encoder 2 is a sine wave signal of several hundred to several thousand cycles per one rotation of the motor shaft, which is a two-phase signal having a phase difference of 90 °. It is outputting. Now these signals When expressed by, ω is proportional to the rotation speed of the motor 1.
Here, the decoding ± is + in the forward rotation and − in the reverse rotation.

Next, these A-phase signal and B-phase signal are converted into digital quantities in the range including -V to + V by A / D conversion circuits 3 and 4, and these are designated as A'and B '. Assuming that the A / D conversion circuits 3 and 4 are 4-bit A / D conversion circuits, when -V, (0000) _{change 2} , + V
In this case, it is possible to correspond to 16 levels of digital quantity as in (1111) ₂ . Then, the data of these 4-bit digital signals A'and B'is put together into 8-bit data, which is led to the address selection input of the ROM 5. In this case, the ROM 5 is capable of address selection of 2 ⁸ = 256 ways. As described above, the correspondence table as shown in FIG. 2B is written in the ROM 5, and in this example, 4-bit interpolation data corresponds to 256 addresses.

As a result, at a certain moment, only one of 256 addresses of the ROM 5 is selected corresponding to the rotation angle of the motor 1, and only one value of the interpolation data corresponding to this is selected. As shown above, the A-phase signal and the B-phase signal are In the case of, in the ROM 5-1 of the interpolated value of FIG. 2 (b), on the circular locus of the shaded portion, the address of the ROM 5-1 is turned counterclockwise for forward rotation and clockwise for reverse rotation. Will be selected. Therefore, for example, in the case of forward rotation,
Starting from A '= (F) ₁₆ and B' = (0) ₁₆ , the interpolation data is 1,2,3,4,5,6,7,8,9, A ..
A sawtooth waveform of 4 periods is obtained during the rotation. In the case of reverse rotation, a sawtooth waveform with an inclination opposite to 1, F, E, D, C, B, A ... Is obtained. In this way, interpolation data similar to the interpolation signal output INPS of the multiplexer MPX ₂ shown in FIG. 10 can be obtained as a digital value. By adding this to the lower order of the data counted by the up / down counter 7, the quantization error of the detection data of the rotation angle of the motor 1 can be further reduced by 1/2 ⁴ compared with the case of only the up / down counter 7. It can be reduced by 1/16.

In the above example, for simplicity of explanation, the outputs of the A / D conversion circuits 3 and 4 are 4 bits, and the output of the ROM 5-1 is 4 bits.
Although the case of bits has been described, it goes without saying that these can be expanded to 5 bits, 6 bits, and so on. Thus, the number of output bits of the A / D conversion circuits 3 and 4 and the ROM 5-1
The output bit number of can be changed freely, for example, A / D
The number of bits of the conversion circuits 3 and 4 can be set to 7 bits, and the number of output bits of the ROM 5-1 can be set to 6 bits. In this case, 1/4 scaling may be performed according to the calculation rule of FIG. In addition, the interpolated data in Fig. 2 (b) did not have a zero value, and there was a step of one step like ... D, E, F, 1, 2, 3 ..., but this is shown in Fig. 2 ( If the 16 × 16 table in b) is expanded outward by one turn to 18 × 18, a value of zero can be inserted, so that more complete interpolation is possible.

The up / down counter 7 is not limited to the one controlled by the above-mentioned method, and may be any counter capable of counting in synchronization with the interpolation data.

Also, in FIG. 2 (b), for simplicity of explanation, a case where the A-phase signal and the B-phase signal swing positive and negative like ± V around 0 (V) is explained, but of course 0 (V) It is also possible not to center around, in which case, for example, A / D conversion rotation 3, 4
It is sufficient to simply shift the conversion range of the input analog signal of.

By doing so, the structure shown in FIG. 10 can be simplified. However, in this case, the ROMs shown in FIGS. 10 and 2 have the problems as shown in FIG. 3, respectively. The present invention improves on this.

FIG. 3 is a diagram for explaining the problems, FIG. 4 is a diagram for explaining the ROM in the first embodiment of the present invention, FIG. 5 is a diagram for explaining the ROM address selection locus, and FIG. 6 is a reference value for the two-phase output of the rotary encoder. FIG. 7 is an explanatory view of the ROM address selection locus in the case of variation from FIG.

By the way, in the apparatus shown in FIG. 10, when the two-phase output of the rotary encoder RE, that is, the amplitude, offset, phase difference, etc. of the A-phase signal, the B-phase signal, fluctuates from the reference values, as shown by the curve S ₂ , Unlike the curve S ₁ when there is no fluctuation,
Discontinuity is likely to occur at the joint portion S ₀ of the interpolation data shown in FIG. 3 (a). Therefore, when the two-phase output, that is, the A-phase signal and the B-phase signal greatly fluctuates, positioning is performed only at the joint and the central portion of the joint where continuity is maintained.

For example, even if an automatic gain adjustment (AGC) is performed to make the amplitude of the two-phase output of the rotary encoder RE constant,
The output of the rotary encoder RE changes from DC to several tens of KHz, and it is difficult to separate the effects of other offset fluctuations and phase difference fluctuations, and even if it could be compared, it would be a large scale.

Even if the ROM 5-1 shown in FIG. 2 (b) is used, the same problem exists when the amplitude of the A-phase signal or the B-phase signal is small. For example, in the ROM 5-1 of FIG. 2 (b), when moving from the first quadrant to the second quadrant, for example, B
When the A / D conversion value B'of the phase signal is the maximum E, the A / D of the A phase signal
When the conversion value A ′ is 8, the interpolation data becomes E → 2, and as shown in FIG. 3 (b), a large step exists at the joint portion S ₀ . Therefore, even if it is attempted to stop at this joint portion S ₀ , as shown in FIG. 3 (c), a vibration state reciprocating between E and 2 occurs, and it is very difficult to stop at this portion. It was

Therefore, an object of the present invention is to improve the ROM shown in FIG. 2 (b) so that even if the amplitude, offset, and phase difference of the encoder two-phase output are slightly changed, this change is compensated. In this form, seamless interpolation data can be generated.

The feature of the present invention is that, as shown in FIG. 4, the ROM 5'is divided into a plurality of continuous areas, and in this section, the same interpolation data is written continuously with the adjacent areas. . In the example of FIG. 4, the A / D for accessing the ROM 5 '
The output of the conversion circuit is a 6-bit digital output and R
3-bit interpolation data is written in OM5 '.

Now, in the case of outputting 6-bit data respectively as the A / D conversion circuits 3 and 4 in FIG. 1 and accessing the ROM 5 ′ shown in FIG. 4 with a total of 12-bit data to obtain 3-bit interpolation data explain.

Therefore, when the motor is rotated, the rotary encoder also rotates and outputs the two-phase signals A and B. The A-phase signal and the B-phase signal are converted into 6-bit digital signals A'and B'by A / D converters 3 and 4, respectively, with respect to the analog quantity range completely including -V to + V. ) ₂ ~ (11111
1) As in ₂ , it is possible to correspond to a digital quantity of 64 steps. These 6-bit digital signals A ',
The data of B'are collected together as 12-bit data and led to the address selection input of the ROM 5'shown in FIG. The ROM 5'in this case is capable of address selection in 2 ¹² = 4096 ways.

As shown in FIG. 4, the values 0 to 7 are written in this ROM 5'as 3-bit interpolation data, and the same value is written in the range of the triangle extending radially from the origin. Is shown.

As shown in the example of FIG. 4, when the interpolated data is 3 bits, the same interpolated data is written in an area equally divided into 11.25 ° each obtained by dividing 360 ° by 2 ³ × 4 = 32. When the information amount of the interpolation data requires n bits, it may be divided into 2 ⁿ × 4.
Actually, the ROM 5'shown in FIG. 4 is a matrix, and the area occupied by one address is a minute square, whereas the boundary of the interpolation data value is a diagonal line, but the interpolation of the address at that boundary is performed. The data value should be rounded up to the one with the larger area.

For example, in order to create the interpolation data while calculating the correspondence table while the servo is operating, for example, with a microcomputer, it requires some complicated calculation, and it cannot be realized in real time.
Even if it can be done, valuable calculation time will be used for a long time, so if you create a correspondence table in advance and write it in ROM (may be RAM) as shown in FIG. 4, the operating speed of this ROM will increase. Real-time continuous interpolation is possible.

Thus, at a certain moment, only one of the 4096 addresses of the ROM is selected corresponding to the rotation angle of the motor, and only one value of the interpolation data corresponding to this is selected.

Here, as mentioned above, In the case of, the address of the ROM 5'is selected on the circular locus shown in FIG. 5 in the counterclockwise direction for the forward rotation and in the clockwise direction for the reverse rotation. Therefore, for example, in the case of normal rotation, if you start from the right end of the circle, the interpolation data will be 0,1,2,3,4,5,6,7,0,1,2. A sawtooth waveform of 4 cycles is obtained during one round of the trajectory, and in the case of reverse rotation, the gradient is 0,7,6,5,4,3,2,1,0,7,6 ... A sawtooth waveform having Up this
By adding to the lower part of the data counted by the down counter 7, the quantization error of the motor rotation angle detection data is further reduced to 1/2 ³ = 1/8 compared with the case of only the up down counter 7. Can be made smaller.

Next, other reasons and effects of using the ROM 5'shown in FIG. 4 will be described.

In the above explanation so far, the two-phase output of the encoder Although it has been expressed in a simple form such as B = V sin ωt,
The actual encoder two-phase output is As described above, it is necessary to allow some variation in the offset component, the vibration component, and the phase difference component of the signal. This is because the encoder is a precision component using a fine slit pattern, and a slight deviation in the mechanical positional relationship of several μm to several tens of μm gives fluctuations to these. This is because if you wish, almost all encoders will be defective. FIG. 6 shows changes in the circular locus of FIG. 5 in the case of such fluctuations. FIG. 6 (a) shows the case where the amplitude fluctuates, the same (b) shows the case where the offset fluctuates, and the same (c)
Indicates the case where the phase difference varies.

If there are such amplitude fluctuations, offset fluctuations, and phase difference fluctuations, in the system shown in FIG. 10, a jump occurs at the joint portion S ₀ as shown in FIG. This is the second
Even when the ROM 5-1 shown in FIG. 2B is used, when the amplitude becomes small, the data passes through the reference locus of the shaded portion in FIG. C, D, E, 2,3
... or a path like A, B, C, D, 2,3,4,5 ..., E → 2 (see Fig. 3), or D
→ You can see that it jumps as shown in 2 (although the jump amount is smaller than when the interpolation circuit is not used).

Analysis of the reason why such a jump phenomenon occurs when the encoder two-phase output fluctuates from the reference value is shown in Fig. 2 (b).
The line connecting the points where the interpolation data values are the same in the ROM 5-1 rises to the right in the first and third quadrants and falls to the right in the second and fourth quadrants, as shown in FIG. 7 (a). The pattern is. Therefore, as is clear from FIG. 2 (b), there are many jumping portions of the adjacent values of the boundary portion of each quadrant.

On the other hand, in the ROM 5'of the present invention, FIG.
As shown in (b), the boundary lines where the values of the interpolation data are equal are lined up in the radial direction with the origin as the center, and the adjacent values of these boundary lines are continuous values. a) to (c)
As shown in FIG. 3, even if there are amplitude fluctuations, offset fluctuations, and phase difference fluctuations in the encoder two-phase output, the jump as shown in FIG. 3 does not occur.

As described above, according to the present invention, even if there is some variation in the two-phase output that is the encoder detection signal, correct continuous interpolation is performed, so that accurate control can be performed.

In the present invention, the output of the A / D conversion circuit is 6 bits,
Although an example in which the output of the ROM is 3 bits has been described, the present invention is not limited to this, of course, and these can be changed as appropriate, and the larger the number of bits, the smaller the quantization error position ( Or, the rotation angle) data is obtained. Further, in FIG. 4, for simplicity of explanation, the A-phase signal,
The case where the B-phase signal swings positive and negative like ± V (V) around 0 (V) has been explained, but it is of course possible that the phase B signal does not center around 0 (V). In that case, for example, A / D It is sufficient to simply shift the conversion range of the input analog signal of the conversion circuit.

In addition, the interpolation data shown in the ROM shows the case where the up / down counter counts the two-phase sine wave signal output from the encoder four times in one cycle. However, when it counts twice or once in one cycle. But it is possible, and in that case RO
If the number of bits of M output interpolation data is 3 bits, it is 4 bits, 5 bits, etc., 4 sets of conversion table values 0 to 7 are 2 sets of 0 to (F) ₁₆ and 0 to (1F) ₁₆ Even if one set is used, it is in line with the gist of the present invention, and the same effect can be obtained.

Then, in the above description, the case where the interpolation data is written in the ROM has been described, but the RAM can of course be used.

In the present invention, as shown in FIG. 13, as in the case where the servo system control device is configured by a micro computer,
When it is sufficient to reduce the quantization error to the required value without having to obtain the position information as a complete continuous quantity, such as when the interpolation output is A / D converted and digitized, the fact that Even if a limit cycle occurs, if the quantization error is reduced, the amplitude of the limit cycle becomes smaller accordingly and it may be ignored, which is very effective.

〔The invention's effect〕

According to the present invention, when the position (or rotation angle) information used for digital control by a micro computer or the like is output as a digital amount, the interpolation data of the counter output can be obtained with an extremely simple configuration.

In addition, the quantization error of the position (or rotation angle) information can be set to an arbitrary value without being affected by a slight change in the amplitude, offset, or phase difference of the two-phase sinusoidal signal that is the detection output of the incremental encoder. It is possible to quickly generate the interpolated data that is extremely small.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention, FIG. 2 is an explanatory diagram of a ROM, FIG. 3 is an explanatory diagram of problems, and FIG. 4 is an explanatory diagram of a ROM in the first embodiment of the present invention. 6 is an explanatory view of the ROM address selection locus, FIG. 6 is an explanatory view of the ROM address selection locus when the two-phase output of the rotary encoder fluctuates from the reference value, and FIG. 7 is an explanatory view of the data arrangement state where the interpolation data values are the same. , FIG. 8 is a method for detecting the position and speed by a conventional incremental encoder, and FIG.
The characteristics shown in FIG. 10, FIG. 10 shows the conventional position and velocity detection method in which the drawbacks shown in FIG. 8 have been improved, FIG. 11 shows the operation characteristic chart of FIG. 10, and FIG. 12 shows the position signal obtained from FIG. The position control and speed detection method is used, FIG. 13 shows the position signal digitizing method of FIG. 10, and FIG. 14 shows the configuration and operation explanatory diagram of the phase discriminator. In the figure, 1 is a motor, 2 is a rotary encoder, 3 and 4 are analog / digital conversion circuits, 5 is a ROM, 6 is a phase discriminator, and 7 is an up / down counter.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toru Kamata 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa FUJITSU LIMITED (56) References JP 50-26975 (JP, A) JP 55-76905 (JP, A) JP 54-19773 (JP, A) JP 59-202008 (JP, A) Actual opening 55-127214 (JP, U) Actual opening 59-14516 (JP, U) Special Japanese Patent Publication No. 1-19044 (JP, B2) Japanese Patent Publication No. 4-524 (JP, B2) JP 61-110005 (JP, A)

Claims (1)

[Claims] 1. π / 2 relative to each other according to movement or rotation of an object
An object for generating a two-phase sinusoidal signal having a phase difference of 2 and a counting means for performing addition counting or subtraction counting according to the moving or rotating direction of the object during one cycle of each of the sinusoidal signals In the position detecting device, the storage means for outputting interpolation position information smaller than the position information that can be detected by the counting means, and the analog / digital conversion means for converting each of the two-phase sinusoidal signals into a digital amount are provided. Information obtained by arranging storage addresses in a matrix when accessing the storage means based on these digital quantities and converting the values of the row numbers and column numbers into digital quantities of the two-phase sinusoidal signals. Means for selecting the interpolation position information is output from the storage means in accordance with these digital amounts, and based on this, the interpolation position information is output. The position information detected by the number means is interpolated, and the number of times the counting means counts during one cycle of the sinusoidal signal is n, and the number of bits of the interpolation position information written in the storage means is m. when a, the planar angle 360 ° by introducing n × 2 ^m equally divided n × 2 ^m pieces of virtual sector in the center of the circle consider a hypothetical circle centered comrades overlaps the center of the matrix , That n × 2
Assign the interpolation information for each 2 ^m as the ^m-number of the sector, the encoder output interpolating circuit and to store the value of the interpolation information in the storage addresses of the matrix which overlaps the respective sector.