JPH06337776A - Multiplier - Google Patents

Abstract

PURPOSE:To provide the multiplier which performs high-precision arithmetic. CONSTITUTION:This multiplier has a pulse generating means 1 which generates a pulse signal, a 1st frequency divider 4 and a 2nd frequency divider 5 which divides the frequency of the pulse signal to two slightly different frequencies, a 1st pulse width converting means 2 and a 2nd pulse width converting means 3 which displace output pulse signal widths from those frequency dividers 4 and 5 according to the level of a multiplied input signal, and logical arithmetic means 6, 7, 8, and 9 which performs logical arithmetic between pulse signals outputted from both the pulse width converting means 2 and 3 to obtain an output signal proportional to the product of the two multiplied input signal levels. Consequently, the frequency need not finely be adjusted and there is no influence of ambient temperature.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplier for obtaining a digital output signal proportional to a product of input signal levels, and more particularly to improvement of multiplication accuracy.

[0002]

2. Description of the Related Art As a multiplier of this type, for example, the one disclosed in Japanese Patent Laid-Open No. 1-81083 is known. As shown in FIG. 4, this multiplier is configured to obtain a pulse signal having a frequency proportional to the product of the voltage values of the two input signals. In the figure, input terminals 11,
The multiplied input signals given to 12 are inputted to the "-" terminals of the comparators OP1 and OP2 in the pulse width modulators 13 and 14, respectively. Since a triangular wave is input to the other "+" terminal, a rectangular wave having a width of a triangular wave sliced at the input signal level of the "-" terminal, that is, a pulse width proportional to each multiplied input signal level A pulse signal is output. Generally, it is necessary to select the pulse frequencies of the pulse width modulator 13 and the pulse width modulator 14 so that they are asynchronous. Since the output pulse signals of the comparators OP1 and OP2 are obtained by the EXOR logical operation circuit 15 as the term of the product of the pulse widths of the respective pulse signals,
The AND logic operation circuit 16 is used to perform a logical product with the output pulse of the pulse oscillator 17 to convert the pulse width into the number of pulses. Since the output pulse width of the EXOR logical operation circuit 15 includes a fixed amount, an output terminal 20 for determining the difference from the number of pulses output from the 1/2 frequency divider 18 is provided.

[0003]

Since it is necessary to select the pulse frequencies of the pulse width modulator 13 and the pulse width modulator 14 so as to be asynchronous, it is necessary to set both frequencies to be slightly shifted. However, in the above-described conventional multiplier, since the two pulse width modulators independently include the CR oscillator, it is difficult to keep the difference in oscillation frequency stable.

The present invention has been made in view of the above problems, and an object thereof is to provide a multiplier capable of stabilizing a frequency difference by adding a simple circuit and performing a highly accurate operation. And

[0005]

In order to achieve the above object, the present invention comprises pulse generating means for generating a pulse signal,
The pulse signal output from this pulse generator is 1 / S
(S is a natural number), a first frequency divider, a second frequency divider that divides the pulse signal into 1 / (S + s) (s is a natural number such that s <S), and the first frequency divider. The first pulse width conversion means for displacing the output pulse signal width from the frequency divider according to the first multiplied input signal level, and the output pulse signal width from the second frequency divider to the second A second pulse width conversion means for displacing in accordance with the multiplied input signal level, and a logical operation of the pulse signal output from the first pulse width conversion means and the second pulse width conversion means The gist of the present invention is to provide a logical operation means for obtaining an output signal proportional to the product of the first multiplied input signal level and the second multiplied input signal level. Further, it is a gist that a timing means for outputting a signal for resetting the first frequency divider and the second frequency divider when a predetermined time has elapsed is provided.

[0006]

The present invention, by taking such means,
By dividing the pulse signals output from the common pulse generating means, the frequency difference between the divided pulse signals becomes stable, so that highly accurate multiplication can be performed.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, 11 and 12 are input terminals for a multiplied input signal, 1 is pulse generating means, 2 and 3
Is a first pulse width conversion means and a second pulse width conversion means, and 4 and 5 are a first frequency divider and a second frequency divider for dividing the pulse output from the pulse generation means 1, respectively. OP1 and OP5 are comparators for outputting a pulse having a pulse width proportional to the multiplied input signal level, and 6 is an E
XOR logic operation circuit, 7 AND logic operation circuit, 8 E
A pulse oscillator that oscillates a pulse for digitizing the pulse width of the pulse output from the XOR logic operation circuit 6, and 9 is a 1/2 frequency divider that divides this pulse into 1/2.

Next, the operation of the apparatus configured as described above will be described with reference to FIG. Input terminal 1 now
The frequency of the input signal to be multiplied input from 1 and 12 is
The case where the frequency is 0 Hz will be described. Since the frequency of the pulse for pulse width conversion needs to be sufficiently higher than the frequency of the input signal to be multiplied, the pulse frequency of the first pulse width conversion means 2 is set to 5000 Hz, for example. On the other hand, in order to improve the accuracy of multiplication, it is desirable that the frequency difference between the output pulse of the first pulse width conversion means 2 and the output pulse of the second pulse width conversion means 3 is small. The pulse frequency of the width converting means 3 is 5005 Hz
And For that purpose, the output pulse frequency of the pulse generating means 11 is set to 5005 kHz, the frequency division ratio of the first frequency divider 4 is set to 1/1001, and the frequency division ratio of the second frequency divider 5 is set to 1/10.
Set to 00. By using a digital circuit for the frequency divider, the frequency division ratio can be accurately set in units of at least 1 Hz. Therefore, the frequency difference between the output pulses of the first frequency divider 4 and the second frequency divider 5 can be calculated. It is possible to reliably set and maintain the desired value. The configuration of the first pulse width conversion means 2 and the second pulse width conversion means 3 is different only in the frequency difference due to the difference in the division ratio of the first frequency divider 4 and the second frequency divider 5. ,
Since the operation is the same, the operation of the first pulse width conversion means 2 will be described. The rectangular wave output pulse from the first frequency divider 4 is an operational amplifier OP2, a resistor R1, a capacitor C1.
Is integrated by the integrator and converted into a triangular wave. The inverting amplifier including the operational amplifier OP3 and the resistors R2 and R3 shifts the amplitude center of the triangular wave to the ground potential. Operational amplifier OP4,
The fluctuation of the amplitude center extracted by the integrator by the resistor R4 and the capacitor C2 is fed back through the resistor R5, and the level of the triangular wave is maintained stable.

Since the triangular wave input to the "+" terminal of the comparator OP1 is sliced by the multiplied input signal level input to the "-" terminal, a rectangular wave having a pulse width proportional to the multiplied input signal level is sliced. A wave pulse signal is obtained. The comparator is adjusted so that the duty ratio of the comparator output pulse becomes 1 when the multiplied input signal level is 0 potential, and when the multiplied input signal level is + potential, the duty ratio is larger than 1 and the multiplied input The duty ratio is set to be smaller than 1 when the signal level is −potential.

Next, the operation of the logical operation means composed of the EXOR logical operation circuit 6, the AND logical operation circuit 7, the pulse oscillator 8 and the 1/2 frequency divider 9 will be described. Since the output signal of the first pulse width conversion means 2 is binarized, the proposition that it is at a high level is now A, and similarly the output signal of the second pulse width conversion means 3 is at a high level. Let us call the proposition B. When the output of the EXOR logical operation circuit 6 whose inputs are A and B is expressed by a logical symbol

[0011]

[Equation 1] Becomes As shown in FIG. 2A, when one cycle of the output pulse signal of the first frequency divider 4 is 2t _a , the first pulse width conversion means 2 has a pulse width T according to the input signal level to be multiplied. _It is converted into a pulse signal of _a (= t _a + τ _a ). Here, τ _a is a value proportional to the multiplied input signal level of the input terminal 11. On the other hand, as shown in FIG. _2B , when one cycle of the output pulse signal of the second frequency divider 5 is 2t _b ,
The second pulse width conversion means 3 converts into a pulse signal having a pulse width T _b (= t _b + τ _b ) according to the multiplied input signal level. Here, τ _b is a value proportional to the multiplied input signal level of the input terminal 12. Here, the pulse period 2t _a and the pulse period 2t _b are set to very close values that are not equal to each other. Assuming that the number of pulses output from the pulse oscillator 8 per unit time is F (see FIG. 2C),
Since the number of pulses P output from the AND logic operation circuit 7 is a value obtained by multiplying the ratio of the period in which the output of the EXOR logic operation circuit 6 is true to the entire period,

[0012]

[Equation 2] 1/2 of the number of pulses F per unit time of the first term pulse oscillator 8 a constant, the second term t _a, t _b is the known because a constant two multiplicand input signal level product Represents a proportional number of pulses.

Therefore, as shown in FIG.
By subtracting P _T from the number of output pulses (1/2) F of the frequency divider 9, P = (1/2) F−P _T = (τ _a · τ _b ) F / 2t _a · t _b (3) Is obtained, the number of pulses proportional to the product of two multiplied input signal levels can be obtained.

Therefore, according to the configuration of the above embodiment, the frequency of the pulse supplied to the two pulse width converting means 2 and 3 can be accurately set and maintained by the frequency divider, so that the frequency is accurate. The multiplication result can be obtained.

FIG. 3 shows another embodiment of the present invention, in which a timing circuit 10 is added to reset the first frequency divider 4 and the second frequency divider 5 at a predetermined timing. There is. When the frequency divider is composed of an analog circuit, the frequency difference between the output pulses of both frequency dividers may not be an integer value. However, according to the present embodiment, the first frequency divider 4 and Since the second frequency divider 5 is reset, the synchronization shift can be prevented.

Further, the above circuit can be constructed by using a D-A converter, and the same effect as that of the embodiment of FIG. 1 can be obtained. Further, miniaturization can be achieved by forming an LSI with a switched capacitor circuit or the like.

[0017]

As described above, according to the present invention, since two pulses whose pulse widths have been modulated are uniformly mixed over a long period of time, it is possible to obtain a highly accurate multiplication result. In addition, since it uses digital frequency division,
It is possible to realize a multiplier that does not require fine adjustment of the frequency and is not affected by the ambient temperature.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration in an embodiment of the present invention.

FIG. 2 is a timing chart of the embodiment of FIG.

FIG. 3 is a block diagram showing the configuration of another embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 pulse generation means 2 1st pulse width conversion means 3 2nd pulse width conversion means 4 1st frequency divider 5 2nd frequency divider 6 EXOR logic operation circuit 7 AND logic operation circuit 8 pulse oscillator 9 1 / 2 frequency divider 10 Timing circuit

Claims (2)

[Claims] 1. A pulse generator for generating a pulse signal and a pulse signal output from the pulse generator
/ S (S is a natural number) and a second frequency divider that divides the pulse signal into 1 / (S + s) (s is a natural number such that s <S), and The first pulse width conversion means for displacing the output pulse signal width from the first frequency divider according to the first multiplied input signal level, and the output pulse signal width from the second frequency divider are Second pulse width conversion means for displacing according to the level of the input signal to be multiplied, and logical operation of the pulse signals output from the first pulse width conversion means and the second pulse width conversion means. And a logical operation means for obtaining an output signal proportional to the product of the first multiplied input signal level and the second multiplied input signal level. 2. The multiplier according to claim 1, further comprising timing means for outputting a signal for resetting the first frequency divider and the second frequency divider after a lapse of a predetermined time.