JPH06337742A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To prevent the reliability of the system from decreasing without interrupting the operation of a processor disconnected from a system bus, to prevent malfunction due to hot-line insertion and extraction, and to improve the maintainability of the system. CONSTITUTION:The multiprocessor system, equipped with plural processors P1-P8 and the system bus 1 which connects those processors P1-P8. is equipped with registers R1-R8 corresponding to the processors P1-P8, a register rewriting means which resets bits of the registers R1-R8 corresponding to an optional processor when an instruction for disconnecting the optional processor from the system bus 1 is inputted, and a means which places the output signal from the optional processor to the system bus 1 in a high-impedance signal after confirming the end of the process of the optional processor once the register rewriting means resets the bits of the registers corresponding to the optional processor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a plurality of processors,
Among the multiprocessor system including the system bus connecting the plurality of processors, in particular, the system reliability is prevented from being lowered without interrupting the operation of the processor disconnected from the system bus, and the malfunction due to the hot-swap is also performed. The present invention relates to a multiprocessor system that prevents the occurrence of the above and improves the maintainability of the system.

[0002]

2. Description of the Related Art Generally, a multiprocessor system is
By connecting a plurality of arithmetic processors and a system control unit by a system bus and sharing a plurality of jobs to perform parallel processing, processing efficiency is improved and system reliability is improved. An external switch provided on an arbitrary processor by an operator when disconnecting an arbitrary one of the plurality of arithmetic processors connected to the system bus from the system bus other than a failure, for example, for version upgrade. Is switched off. When the external switch is turned off, the arbitrary processor becomes detachable from the system bus, and the operator removes the arbitrary processor from the system bus. Further, when the external switch is turned off, the arbitrary processor forcibly interrupts the operation of the task being executed.

[0003]

However, when disconnecting an arbitrary arithmetic processor from the system bus, the operation of the task in the arbitrary arithmetic processor is forcibly interrupted by switching the external switch to the off state. The processing until the interruption is wasted, and there is a possibility that the reliability of the system may be deteriorated particularly when important processing is being executed.

Further, if the external switch is switched to the OFF state during the hot-plugging operation of the board of the arbitrary arithmetic processor, there is a possibility that the arbitrary arithmetic processor malfunctions, and the maintainability of the system is improved. There was a problem of lowering.

The present invention has been made in view of such conventional problems, and an object thereof is to prevent the system reliability from being lowered without interrupting the operation of the processor disconnected from the system bus. It is an object of the present invention to provide a multiprocessor system that prevents malfunctions caused by hot-plugging and unplugging and improves system maintainability.

[0006]

To achieve the above object, the present invention provides a multiprocessor system comprising a plurality of processors and a system bus connecting the plurality of processors, the system bus being connected to the system bus. A register having a bit corresponding to the plurality of processors, and a register rewriting unit that resets a bit corresponding to the arbitrary processor of the register when an instruction to disconnect any processor of the plurality from the system bus is input. When the register rewriting unit resets the bit of the register corresponding to the arbitrary processor, after confirming the end of the processing of the arbitrary processor, the output signal from the arbitrary processor to the system bus is set to high impedance. The gist is to have means

[0007]

According to the above construction, when an instruction for disconnecting any one of the plurality of processors from the system bus is input, the register rewriting means causes the register having the bit corresponding to the plurality of processors connected to the system bus. Reset the bit corresponding to any of the processors. After resetting, the output signal from the arbitrary processor to the system bus is set to high impedance after confirming the completion of the processing of the arbitrary processor, so that the reliability of the system can be improved without interrupting the operation of the processor disconnected from the system bus. It is possible to prevent deterioration of sex.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a system configuration diagram according to an embodiment of a multiprocessor system of the present invention.

In the above multiprocessor system, the system bus 1 has a plurality of arithmetic processors P1, arithmetic processors P2 ... Arithmetic processors P8, and a system controller 3.
Are connected to each other to share a plurality of jobs and perform parallel processing to improve processing efficiency and improve system reliability.

The arithmetic processor P1, the arithmetic processor P2 ... The arithmetic processor P8 are provided with registers R1, R2 and R8 which indicate the mounting states of the arithmetic processors connected to the system bus 1, respectively. The system bus 1 includes an address line and a data line, and transmits data, instructions and the like in the arithmetic processor P1 ... Arithmetic processor P8 and the system control unit 3. The system control unit (SCU) 3 includes a memory 5 shared by the arithmetic processors P1 and the like, and controls the arithmetic processors P1, arithmetic processors P2, ... Arithmetic processors P8 and controls the entire system.

The control of the arithmetic processor P8 connected to the system bus 1 will be described with reference to the block diagram of FIG. The arithmetic processor P8 connected to the system bus 1 is provided with an instruction decoding unit 7, a driver 9 and a register rewriting unit 11 to perform processing such as data arithmetic and control for disconnection from the system bus 1. When the command transmitted from the system control unit 3 via the system bus 1 is input, the instruction decoding unit 7 decodes the command and controls the register rewriting unit 11 and the like. The driver 9 controls input / output transmission of commands, data, etc. to the system bus 1. The register rewriting unit 9 controls rewriting of bits included in the register R8 described later.

The arithmetic processor P8 also includes a task processing detector 13, an exclusion processor 15, and a register R8. The task processing detection unit 13 detects whether a task in the arithmetic processor P8 is operating and detects the instruction decoding unit 7
To notify. When the instruction decoding unit 7 determines that the arithmetic processor P8 can be disconnected from the system bus 1, the exclusion processing unit 15 receives a control signal from the instruction decoding unit 7 and sets the output signal to the system bus 1 to high impedance. .

Now, the register R8 will be described with reference to FIG. The register R8 indicates a mounting state in which the arithmetic processor is connected to the system bus 1, and is 0
When the arithmetic processor P1 corresponds to the bit, the arithmetic processor P2 to the first bit corresponds to the arithmetic processor P8 to the seventh bit, and each arithmetic processor is connected to the system bus 1, the bit is separated to "1". If it is "0"
Is set to. Although the control of the arithmetic processor P8 and the like have been described, the other arithmetic processors may be the arithmetic processor P8.
The same control and the like.

Next, the operation of this embodiment will be described with reference to FIG.
An explanation will be given using the flowchart of (b).

First, the case where the arithmetic processor P8, which is connected to the system bus 1 when the system is activated, is disconnected from the system bus 1 by the self processor will be described with reference to the flowchart of FIG. 4 (a).

The instruction decoding unit 7 of the arithmetic processor P8
When an instruction is input from the system control unit 3 via the system bus 1, the register rewriting unit 11 decodes the instruction and disconnects the processor from the system bus 1 if the instruction is input.
(Step 100). By the notification, the register rewriting unit 11 rewrites the flag of the 7th bit of the register R8 from "1" to "0" (step 110). When the flag is rewritten, the instruction decoding unit 7 notifies the system control unit 3 via the system bus 1 that the own processor has been disconnected (step 120). After the notification, the instruction decoding unit 7 outputs a control signal to the exclusion processing unit 15, and the exclusion processing unit 15 sets the output signal to high impedance (step 130).

Next, when disconnecting from other processors, for example, from the arithmetic processors P1 to P
A case where 8 is disconnected and controlled will be described with reference to the flowchart of FIG.

When an instruction to disconnect the arithmetic processor P8 from the system bus 1 is transmitted from the arithmetic processor P1 to the system controller 3, the system controller 3 interrupts the arithmetic processor P8. After the interrupt, the instruction decoding unit 7 of the arithmetic processor P8 decodes the instruction when the instruction is input via the system bus 1 and the register rewriting unit 11 if the instruction is to disconnect the processor from the system bus 1.
(Step 140). By the notification, the register rewriting unit 11 rewrites the flag of the 7th bit of the register R8 from "1" to "0" (step 150). When the flag of the 7th bit of the register R8 is rewritten, the instruction decoding unit 7 notifies the system control unit 3 via the system bus 1 that the own processor is disconnected (step 160). After the notification, the instruction decoding unit 7 makes the task processing detection unit 1
When notified to 3, the task processing detection unit 13 detects whether the operation of the task in the arithmetic processor P8 is completed. When the operation of the task is completed by the detection, the process proceeds to step 180, and when the operation is not completed, the task is put into the waiting state (step 170). When the process proceeds to step 180, when the instruction decoding unit 7 outputs the control signal to the exclusion processing unit 15, the exclusion processing unit 15 sets the output signal to the system bus 1 to high impedance. At the same time, the originating arithmetic processor P8 notifies the arithmetic processor 1 which issued the instruction that the processor itself has been disconnected from the system bus 1 (step 180).

As a result, the arithmetic processor 8 can be disconnected from the system bus 1 and can be removed from the system bus 1 by the operator.

After the operation of the task in the arithmetic processor disconnected from the system bus 1 is finished, the exclusion processing for changing the output signal to the high impedance is performed. Therefore, the task is disconnected from the system bus 1 without interrupting the operation as in the conventional case. System reliability can be prevented from degrading, and malfunction due to hot-plugging can be prevented in advance to improve system maintainability.

Although this embodiment has been described from the arithmetic processor P1 to the arithmetic processor P8, it can be applied to the case where the arithmetic processor P8 is disconnected by an instruction from another arithmetic processor.

Further, in the present embodiment, when a predetermined error occurs for each system, it is possible to easily set the disconnection processing of the arithmetic processor in which the error has occurred, and the RAS (reliability of the system). , Availability, maintainability) can be improved.

[0024]

As described above, according to the present invention, when an instruction for disconnecting any one of a plurality of processors from the system bus is input, the bit corresponding to the any processor in the register is reset so that the arbitrary processor is reset. When the completion of the processing of the processor is confirmed, the output signal from the arbitrary processor to the system bus is set to high impedance, so that the deterioration of the system reliability is prevented without interrupting the operation of the processor disconnected from the system bus. It is possible to prevent malfunction due to hot-plugging and unplugging and improve the maintainability of the system.

[Brief description of drawings]

FIG. 1 is a system configuration diagram according to an embodiment of a multiprocessor system of the present invention.

FIG. 2 is a block diagram of FIG. 2 showing control of an arithmetic processor.

FIG. 3 is a diagram showing a register.

FIG. 4 is a flowchart showing the operation of the present invention.

[Explanation of symbols]

 1 System Bus 3 System Control Unit 7 Instruction Decoding Unit 11 Register Rewriting Unit 13 Task Processing Detection Unit 15 Exclusion Processing Unit P1 to P7 Operation Processors R1 to R7 Registers

Claims (1)

[Claims] 1. A multiprocessor system comprising a plurality of processors and a system bus connecting the plurality of processors, wherein a register having a bit corresponding to the plurality of processors connected to the system bus, A register rewriting unit that resets a bit corresponding to the arbitrary processor of the register when an instruction to disconnect an arbitrary processor from the system bus is input, and a register rewriting unit that registers the bit corresponding to the arbitrary processor by the register rewriting unit. A multiprocessor system comprising: a means for setting an output signal from the arbitrary processor to the system bus to high impedance after confirming completion of processing of the arbitrary processor when the bit is reset.