JPH06334702A - Line changeover circuit - Google Patents

Abstract

PURPOSE:To prevent collision of data by providing a protection circuit in which plural data communication lines are not simultaneously selected for the system. CONSTITUTION:The line changeover circuit is provided with a data communication line selection instruction section 1 instructing selection of a data communication line 5 to which an external communication line is connected, a selection command detection section 2 discriminating whether or not the data communication line selection command section 1 makes an instruction of selection of plural data communication lines 5 to provide an output of a detection signal representing the result, a selection instruction detecting section 2 judging whether or not the data communication line selection instruction section 1 selects and instructs plural data communication line 5, and outputting the detection signal showing the result a protection section 3 providing an output of a selection signal 7 to select the data communication line 5 when detection signal representing the command of the selection of only one data communication line 5 is received and not providing an output of the selection signal 7 when the detection signal representing the command of the selection of plural data communication lines simultaneously, and a selection section 4 connecting the data communication line 5 selected by the selection signal 7 to the external communication line 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a line switching circuit,
In particular, the present invention relates to a line switching circuit that performs communication by connecting only one data communication line to an external communication line during a certain period of a plurality of data communication lines.

[0002]

2. Description of the Related Art Multiplexes for accommodating a plurality of terminal devices (DTEs) such as workstations and personal computers, rearranging communication data randomly generated from each terminal device and sending it to an external communication line such as a high speed digital line. In a communication control device such as a communication device, only one data communication line is selected from the data communication lines to which a plurality of terminal devices are connected and connected to an external communication line during a certain period. Communication is performed by sequentially switching the data communication lines to be connected.

FIG. 6 shows a block diagram of a conventional line switching circuit. The line switching circuit 61 mainly includes an MPU (microprocessor unit) 62, a data selection register 63, a communication controller 64, and a selection D-flip-flop (D).
-FF) D1, D2, ... Dn and interface connectors I1, I2 ,.
Composed of and.

The MPU 62 includes a CPU, a RAM, a ROM,
This is a so-called 1-chip type microcomputer including a timer, an I / O controller, etc., and is the main body that executes the line switching function. The data selection register 63 outputs a selection signal for selecting one of the plurality of data communication lines.

Select D-Flip Flop (D-FF) D
1, D2, ... Dn are connected to each data communication line,
Only when the selection signal is input, a data communication gate that outputs data on the corresponding data communication line is operated. The selection signal is input to the enable terminal of the selection D-FF and used as the enable signal of the selection D-FF.

The communication controller 64 adds a control bit and a parity bit so that the data that has passed through the selected D-FF can be sent to the external communication line 65 and assembles it into a frame structure. Further, as shown in FIG. 6, the terminal devices DTE1, 2, ... N such as workstations and personal computers are connected to the data communication lines L1, L.
2, ... Ln are connected to the interface connectors I1, I2, ... In respectively.

In this example, the data communication line is selected as follows. First, the MPU 62 selects the D-FF D1, D2, ... D for the data selection register 63.
Data indicating which of n should be selected is written. For example, when data indicating that the selection D-FF D1 should be selected is written, the data selection register 63
Sends a selection signal only to the selection D-FF D1.

Selection D-FF D1 to which selection signal is input
Becomes an enabled state, passes the data on the data communication line L1, and outputs the data to the communication controller 64. on the other hand,
The other selection D-FF to which the selection signal is not input is in the disabled state and does not pass data.

As described above, conventionally, one of the plurality of data communication lines is selected by enabling only one of the selected D-FFs on the plurality of data communication lines. I was communicating by connecting to an external communication line.

[0010]

However, in the above-mentioned line switching circuit, when a plurality of data communication lines are simultaneously selected due to some malfunction such as software defect, the selected plurality of data communication lines are connected. Data may collide with the output part of the selected D-FF and cause circuit destruction.

The present invention has been made in consideration of the above circumstances, and prevents a data collision by providing a protection circuit for preventing a plurality of data communication lines from being selected at the same time. However, it is an object of the present invention to provide a line switching circuit that can prevent circuit destruction.

[0012]

FIG. 1 shows a block diagram of the basic construction of the present invention. In the figure, the present invention relates to a circuit switching circuit for connecting a plurality of data communication lines 5 and an external communication line 6 to one external data communication line 6 by sequentially selecting only one arbitrary data communication line 5. , A data communication line selection instructing unit 1 for selecting and instructing the data communication line 5 to be connected to the external communication line 6, and whether or not the data communication line selection instructing unit 1 has instructed selection of a plurality of data communication lines 5. A selection instruction detection unit 2 that makes a determination and outputs a detection signal indicating the result, and a data communication line selection instruction unit 1
When the detection signal from the selection instruction detecting unit 2 indicating that the selection instruction of only one data communication line 5 is input, the selection signal 7 for selecting the data communication line 5 is output. A protection unit that does not output the selection signal 7 when a detection signal from the selection instruction detection unit 2 indicating that the data communication line selection instruction unit 1 is instructing selection of a plurality of data communication lines 5 at the same time is input. The present invention provides a line switching circuit including: 3 and a selection unit 4 for connecting one data communication line 5 selected by a selection signal 7 output from the protection unit 3 to an external communication line 6.

Further, the protection unit 3 receives the detection signal from the selection instruction detecting unit 2 indicating that the data communication line selection instructing unit 1 is simultaneously instructing the selection of a plurality of data communication lines. Alternatively, only the selection signal 7 for selecting the data communication line having the highest priority among the data communication lines instructed to be selected may be output in accordance with the predetermined priority given to the data communication line.

[0014]

[Function] The data communication line selection instructing unit 1 is the external communication line 6
The selection instruction of the data communication line 5 to be connected to is output to the selection instruction detection unit 2. The selection instruction detection unit 2 is configured so that the input selection instruction of the data communication line is a plurality of data communication lines 5.
It is determined whether or not the selection instruction is given.

When the selection instruction detecting unit 2 determines that the data communication line selection instructing unit 1 gives an instruction to select only one data communication line 5, the selection instruction detecting unit 2 determines that only one data is available. A detection signal indicating that the instruction to select the communication line 5 is issued is output to the protection unit 3.

When the selection instruction detecting unit 2 determines that the data communication line selection instructing unit 1 is simultaneously instructing the selection of the plurality of data communication lines 5, the selection instruction detecting unit 2 simultaneously operates the plurality of data. A detection signal indicating that the instruction to select the communication line 5 is issued is output to the protection unit 3.

When the detection signal indicating that the instruction to select only one data communication line is input, the protection unit 3 outputs the selection signal 7 for selecting the data communication line 5 to the selection unit. Output to 4.

The protection unit 3 does not output the selection signal 7 when a detection signal indicating that a plurality of data communication lines are selected is instructed at the same time. The selection unit 4 connects one data communication line 5 selected by the input selection signal 7 to the external communication line 6.

Further, in the structure according to the second aspect, the protection unit 3 is connected to the data communication line 5 when a detection signal indicating that a plurality of data communication lines are selected is simultaneously instructed. Only the selection signal 7 for selecting the data communication line having the highest priority among the data communication lines 5 selected and instructed according to the given predetermined priority is output.

Therefore, when a plurality of data communication lines are instructed to be selected at the same time, the protection unit 3 does not output the selection signal for selecting the data communication lines, or the protection unit 3 outputs two selection signals at the same time.
Since no more than one data is output, it is possible to prevent data collision and prevent circuit destruction.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the embodiments shown in the drawings. The present invention is not limited to this. FIG. 2 shows a block diagram of the configuration of the first embodiment of the present invention.

A line switching circuit 21 constitutes an MPU 22 and a data selection register 23 which form a data communication line selection instruction section, NAND elements N1 to N4 which form a selection instruction detection section 2, and a protection section 3. OR element OR1
It is composed of an OR4, a communication controller 24 and D-flip-flops D1 to D4 that form the selection unit 4, and interface connectors I1 to I4 that connect data communication lines.

Here, the MPU 22 and the data selection register 2
3 and the communication controller 24 perform the same operation as shown in the related art. Reference numeral 25 is an external communication line. DTE1 to DTE4 are terminal devices such as workstations or personal computers, and are connected to the interface connectors I1 to I4 of the line switching circuit 21 via the data communication lines L1 to L4, respectively.

The NAND elements N1 and N2 are elements that output the result of the NAND logical operation on the input signal. The OR elements OR1 to OR4 are OR with respect to the input signal.
Is an element that outputs the result of the logical operation of.

In this example, the D-flip-flops D1 to D4 pass only the data on one data communication line out of the data transmitted on the four data communication lines and transmit the data to the communication controller 24. This is the part that performs the operation. The D-flip-flop has an enable terminal (E
This is an element that outputs the input data as it is when there is an'L 'level input in N).

Next, an operation example in which one data communication line is selected from the four data communication lines will be described with reference to FIG. First, the MPU 22 sets a numerical value corresponding to the data communication line to be selected in the data selection register 23 according to the program stored in the internal ROM, and gives a selection instruction. The data selection register 23 sends a selection instruction signal to the signal line corresponding to the data communication line according to the set numerical value.

For example, in order to select the data communication line L1 from the MPU 22, the numerical value 1 is the data selection register 2
Suppose that it is set to 3. When the numerical value 1 is set, the data selection register 23 outputs an'L 'level signal on the signal line R1 corresponding to the data communication line L1. This'L 'level signal is a signal indicating that selection is instructed. At this time, the other signal lines R2, R3 and R
An'H 'level signal indicating that selection is not instructed is output to 4.

As described above, when only the signal line R1 is at the “L” level and the signal lines R2, R3, and R4 are at the “H” level, only the signal line EN1 is set by the NAND and OR elements. L'level selection signal is output,
An'H 'level selection signal is output to the other signal lines EN2, EN3 and EN4.

Therefore, of the D-flip-flops of the selection section, only D1 is enabled and the data on the data communication line L1 is passed and input to the communication controller 24.

Next, the operation when a plurality of data communication lines are simultaneously selected will be described. When the data communication lines L1 and L2 are instructed to be selected at the same time due to a programming error of the MPU 22 or a malfunction of the data selection register, an'L 'level signal is output on the signal lines R1 and R2. . The signal lines R3 and R4 are at the “H” level.

At this time, it is detected that a line other than the data communication line to be selected is selected in the NAND elements N1 to N4, and the outputs of the NAND elements N1 to N4 are all at the "H" level.

The OR elements OR1 and O of the protection unit 3 are
Data communication lines L1 and L selected and designated by R2
The'L 'level signals on R1 and R2 corresponding to 2 are masked, and the signal lines EN1 to EN4 become'H' level,
All the D-FFs D1 to D4 are disabled and no data communication line is selected. That is, the setting for instructing selection of multiple data communication lines is invalidated,
All four data communication lines are in a state of not being connected to the communication controller 24.

FIG. 3 shows an example of a logical correspondence diagram of signals on the line switching circuit in the first embodiment. In the figure, the level of the signal when only the data communication line L1 is instructed to be selected is shown. When only the signal line R1 is at the'L 'level as the output of the data selection register, the enable terminal ( EN) signal line EN1 that is an input to
Only the level is'L '. That is, only the D-FF D1 is enabled.

The symbols and indicate the signal levels when the data communication line L1 is instructed to be selected and at the same time any one of the other L2, L3 or L4 is instructed to be selected. In all cases, the signal lines EN1 to EN4 are all at the “H” level, and all the D-FFs are disabled.

As can be seen from the logical correspondence diagrams of ~, when only one data communication line is instructed to be selected, only the corresponding one of the signal lines EN1 to EN4 becomes the "L" level. Note that, in FIG. 3, L / H may be either “L” level or “H” level.

As described above, only when only one data communication line is selected and instructed, only the D-FF corresponding to that data communication line is enabled, and the data of the data communication line is changed to the communication controller 24. Will be input to, and it is possible to prevent data collision.

FIG. 4 is a block diagram showing the configuration of the second embodiment of the present invention. In the first embodiment, when a plurality of data communication lines are selected and instructed at the same time, control is performed so that data on any data communication line is not transmitted, but in this embodiment, the data communication line has priority over the circuit configuration. When a plurality of data communication lines are selected and instructed at the same time in order, only the data on the data communication line with the highest priority is controlled to be transmitted to the communication controller.

2 is different from FIG. 2 in the configuration of the selection instruction detecting section 2 and the protecting section 3 and the connection relationship of the signal lines. The signal line R1 is the enable terminal (E of the D-flip-flop D1 of the direct selection unit).
N), the data on the data communication line L1 is always input to the communication controller 24 when the data communication line L1 is selected and instructed.

The selection instruction detecting section 2 includes a NOT element N11 which receives the signal line R1, an NAND element N12 which receives the signal lines R1 and R2, and signal lines R1, R2 and R3.
And a NAND element N13 which receives as input.

The protection section 3 includes a signal line R2 and a NOT element N.
OR element OR11 which receives the output of 11 and signal line R
3 and the output of the NAND element N12 as an input, an OR element OR12, and the signal line R4 and the output of the NAND element N13 as an input. With the circuit configuration as described above, the priority of the data communication line to be selected is the highest in the data communication line L1 and L2.
It is set so that it becomes lower in the order of L3 and L4.

FIG. 5 shows a logical correspondence diagram of signals on the line switching circuit in the second embodiment. In the figure, indicates the signal level when the data communication line L1 is instructed to be selected, and the other data communication lines L2 and L3 are shown.
Regardless of the selection instruction state of L4 and L4, only the D-flip-flop D1 corresponding to the data communication line L1 is enabled, and only the data on the data communication line L1 is input to the communication controller 24.

That is, at this time, the signal line R1 is "L".
Since it is at the level, the NOT element N11 and the NAND element N1 are irrespective of the states of the signal lines R2, R3, and R4.
The outputs of 2 and N13 become "H" level, and the OR element O
Input to R11, OR12, and OR13. Therefore, all the outputs of each OR element become'H 'level, and D
-The enable terminals of the flip-flops D2, D3 and D4 are at the "H" level and are in the disabled state.

In the case where the data communication line L1 is not instructed to be selected, the data communication line L2 is instructed to be selected. At this time, since the signal line R1 is at the “H” level and the signal line R2 is at the “L” level, OR
Only the signal line EN2 that is the output of the element OR11 becomes the “L” level, and the other signal lines EN1, EN3 and EN4 become the “H” level. Therefore, only the D-flip-flop D2 is enabled and the data communication line L2
Only the above data is input to the communication controller 24.

Indicates that the data communication line L3 is instructed to be selected and has a higher priority than L3.
And L2 are not instructed to be selected, and the data communication line L4 is irrespective of the selection instruction of the data communication line L4.
3 is selected.

In the case where only the data communication line L4 is instructed to be selected, the data communication line L4 is selected only when the other high priority data communication lines L1, L2 and L3 are not instructed to be selected. To be done.

With the above circuit configuration, even if a plurality of data communication lines are selected and instructed at the same time, the data communication line having the highest priority among the plurality of data communication lines instructed to be selected can be handled. Only the D-FF is enabled and the data of the data communication line is input to the communication controller 24, so that the data collision can be prevented.

[0047]

According to the present invention, by providing a protection circuit that prevents a plurality of data communication lines from being selected at the same time, data collision can be prevented and circuit destruction can be prevented in advance. it can.

[Brief description of drawings]

FIG. 1 is a block diagram showing a basic configuration of the present invention.

FIG. 2 is a configuration block diagram of a first embodiment of the present invention.

FIG. 3 is a logic correspondence diagram of signals in the first embodiment of the present invention.

FIG. 4 is a configuration block diagram of a second embodiment of the present invention.

FIG. 5 is a logic correspondence diagram of signals in the second embodiment of the present invention.

FIG. 6 is a block diagram showing a basic configuration in a conventional example.

[Explanation of symbols]

 1 data communication line selection instruction unit 2 selection instruction detection unit 3 protection unit 4 selection unit 5 data communication line 6 external communication line 7 selection signal 21 line switching circuit 22 MPU 23 data selection register 24 communication controller 25 external communication line DTE1 to 4 terminals Device L1 to L4 data communication line I1 to I4 interface connector N1 to N4 NAND element OR1 to OR4 OR element D1 to D4 D-flip flop (D-FF) R1 to R4 selection instruction signal line EN1 to EN4 selection signal line

Claims (2)

[Claims] 1. When connecting a plurality of data communication lines (5) and an external communication line (6), only one arbitrary data communication line (5) is sequentially selected and connected to the external communication line (6). Data communication line (5) that should be connected to external communication line (6) in the line switching circuit
The data communication line selection instructing section (1) for selecting and instructing whether or not the data communication line selection instructing section (1) has instructed selection of a plurality of data communication lines (5), and shows the result. Selection instruction detection unit (2) that outputs a detection signal
And a detection signal from the selection instruction detection unit (2) indicating that the data communication line selection instruction unit (1) is instructing selection of only one data communication line (5), Selection signal (7) for selecting the data communication line (5)
Is output and a detection signal from the selection instruction detection unit (2) indicating that the data communication line selection instruction unit (1) is simultaneously instructing selection of a plurality of data communication lines (5) is input. Is a protection unit (3) that does not output the selection signal (7) and one data communication line (5) selected by the selection signal (7) output from the protection unit (3) to the external communication line (6). A line switching circuit having a connecting section (4) to be connected. 2. When connecting a plurality of data communication lines (5) and an external communication line (6), only one arbitrary data communication line (5) is sequentially selected and connected to the external communication line (6). Data communication line (5) that should be connected to external communication line (6) in the line switching circuit
The data communication line selection instructing section (1) for selecting and instructing whether or not the data communication line selection instructing section (1) has instructed selection of a plurality of data communication lines (5), and shows the result. Selection instruction detection unit (2) that outputs a detection signal
And a detection signal from the selection instruction detection unit (2) indicating that the data communication line selection instruction unit (1) is instructing selection of only one data communication line (5), Selection signal (7) for selecting the data communication line (5)
Is output and a detection signal from the selection instruction detection unit (2) indicating that the data communication line selection instruction unit (1) is simultaneously instructing selection of a plurality of data communication lines (5) is input. Is the data communication line (5) selected and instructed in accordance with the predetermined priority given to the data communication line (5).
The protection unit (3) that outputs only the selection signal (7) that selects the data communication line (5) that has the highest priority among them, and the selection signal (7) that is output from the protection unit (3). A line switching circuit having a selection unit (4) for connecting one data communication line (5) to an external communication line (6).