JPH06334485A - Three-stage switch device - Google Patents

Three-stage switch device

Info

Publication number
JPH06334485A
JPH06334485A JP13923493A JP13923493A JPH06334485A JP H06334485 A JPH06334485 A JP H06334485A JP 13923493 A JP13923493 A JP 13923493A JP 13923493 A JP13923493 A JP 13923493A JP H06334485 A JPH06334485 A JP H06334485A
Authority
JP
Japan
Prior art keywords
switch
input
output
switches
primary
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13923493A
Other languages
Japanese (ja)
Other versions
JP2737600B2 (en
Inventor
Yoshimi Hirata
芳美 平田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP5139234A priority Critical patent/JP2737600B2/en
Publication of JPH06334485A publication Critical patent/JPH06334485A/en
Application granted granted Critical
Publication of JP2737600B2 publication Critical patent/JP2737600B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)

Abstract

PURPOSE:To avoid production of blocking even when a fault takes place in a secondary switch and it is relieved by providing 2n sets of secondary switches and using one secondary switch in a redundant way. CONSTITUTION:A matrix circuit 4 consists of primary switches 1-1-1-(N/n) having inputs (n) and outputs (2n), secondary switches 2-1-2-2n having N/n inputs and outputs N/n and a ternary switch having inputs 2n and outputs (n) and the primary, secondary and terminal switches are in close connection. When a secondary switch (j) is faulty with connection of the primary switch (i), the secondary switch (j) and the ternary switch (k), a control section 5 uses the primary switch (i) to make broadcast to the input (a). In this case, a contact b1 of the secondary switch is closed, a contact b2 of the secondary switch 2n is closed and the connection of the contact a3 of the ternary switch (k) is open and the contact b3 is closed. Thus, a fault of the secondary switch (j) is relieved. Then the control section 5 uses the secondary switch 2-2n only when the relief of the secondary switch is required.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はクロスコネクト装置など
に使用される3段スイッチ装置に係り、特に2次スイッ
チの障害救済のための3段スイッチ装置に関するもので
ある。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a three-stage switch device used in a cross-connect device or the like, and more particularly to a three-stage switch device for relieving a failure of a secondary switch.

【0002】[0002]

【従来の技術】従来の3段スイッチ装置は、図2に示す
ようにマトリクス回路14が入力n,出力2n−1
(n:整数)の1次スイッチ1−1〜1−(N/n)の
N/n個(N:整数)と入力N/n,出力N/nの2次
スイッチ2−1〜2−2n−1の2n−1個および入力
2n−1,出力N/nの3次スイッチ3−1〜3−(N
/n)のN/n個からなるクロス(clos)構成され
ており、このマトリクス回路14を制御する制御部15
から構成されている。そして、制御部15では3段スイ
ッチ構成に伴うブロッキングを防止するために、1次ス
イッチでのブロードキャスト(分岐)接続は一切行わな
い制御を行っていた。
2. Description of the Related Art In a conventional three-stage switch device, a matrix circuit 14 has an input n and an output 2n-1 as shown in FIG.
(N: integer) primary switches 1-1 to 1- (N / n) N / n (N: integer) and input N / n, output N / n secondary switches 2-1 to 2- 2n-1 of 2n-1 and 3n switches 3-1 to 3- (N of input 2n-1 and output N / n)
/ N) N / n crosses are configured, and the control unit 15 controls the matrix circuit 14.
It consists of Then, in order to prevent blocking due to the three-stage switch configuration, the control unit 15 performs control such that broadcast (branch) connection at the primary switch is not performed at all.

【0003】[0003]

【発明が解決しようとする課題】この従来の3段スイッ
チ装置では、2次スイッチで障害が発生した場合に他の
2次スイッチに空きがあれば障害となった接続(パス)
の救済が可能であるが、他の2次スイッチを使用してし
まうとブロッキングが発生する可能性が出てくるという
問題があった。本発明はかかる問題を解決するためにな
されたもので、3段スイッチ回路の2次スイッチ障害救
済時にブロッキングが発生せず、切戻し時の瞬断時間を
短くする3段スイッチ装置を得ることを目的とする。
In this conventional three-stage switch device, when a failure occurs in the secondary switch, if there is a vacancy in the other secondary switch, the connection (path) in which the failure occurs
However, there is a problem in that blocking may occur if another secondary switch is used. The present invention has been made to solve such a problem, and it is an object of the present invention to provide a three-stage switch device in which blocking does not occur at the time of relieving a secondary switch failure of a three-stage switch circuit and the instantaneous interruption time at the time of switchback is shortened. To aim.

【0004】[0004]

【課題を解決するための手段】本発明の3段スイッチ装
置は、入力N,出力N(N:整数)のマトリクス回路お
よびこの入力N,出力Nのマトリクス回路の接続制御,
障害検出を行う制御部から構成され、上記入力N,出力
Nのマトリクス回路は入力n,出力2n(n:整数)の
1次スイッチN/n個と入力N/n,出力N/nの2次
スイッチ2n個および入力2n,出力nの3次スイッチ
N/n個からなるクロス構成のマトリクス回路であり、
上記制御部に上記1次スイッチで分岐接続を行わせる機
能を持つようにしたものである。
A three-stage switch device according to the present invention comprises a matrix circuit of input N and output N (N: integer) and connection control of the matrix circuit of input N and output N,
The matrix circuit having the input N and the output N comprises a primary switch N / n having an input n and an output 2n (n: an integer) and two input N / n and an output N / n. It is a matrix circuit of a cross configuration composed of 2n next switches and N / n third switches of input 2n and output n,
The control unit has a function of making a branch connection with the primary switch.

【0005】[0005]

【作用】本発明においては、2次スイッチを2n個持つ
ことにより、1個の2次スイッチを冗長的に使用する。
In the present invention, one secondary switch is redundantly used by having 2n secondary switches.

【0006】[0006]

【実施例】つぎに本発明について図面を参照して説明す
る。図1は本発明による3段スイッチ装置の一実施例を
示す系統図である。この図1において、1−1〜1−
(N/n)は入力n,出力2nのN/n個の1次スイッ
チ、2−1〜2−2nは入力N/n,出力N/nの2n
個の2次スイッチ、3−1〜3−(N/n)は入力2
n,出力nのN/n個の3次スイッチである。4はこれ
ら入力n,出力2nの1次スイッチ1−1〜1−(N/
n)と入力N/n,出力N/nの2次スイッチ2−1〜
2−2nおよび入力2n,出力nの3次スイッチ3−1
〜3−(N/n)からなるクロス(clos)構成のマ
トリクス回路(入力N,出力Nのマトリクス回路)であ
る。
The present invention will be described below with reference to the drawings. FIG. 1 is a system diagram showing an embodiment of a three-stage switch device according to the present invention. In FIG. 1, 1-1 to 1-
(N / n) is N / n primary switches having an input n and an output 2n, and 2-1 to 2-2n is an input N / n and an output N / n 2n.
Input of 2 secondary switches, 3-1 to 3- (N / n)
N / n third-order switches with output n. Reference numeral 4 designates primary switches 1-1 to 1- (N /
n) and input N / n, output N / n secondary switches 2-1 to 2-1.
2-2n and input 2n, output n tertiary switch 3-1
It is a matrix circuit (matrix circuit of input N, output N) having a cross structure composed of 3 to 3- (N / n).

【0007】そして、このマトリクス回路4は入力n,
出力2nの1次スイッチ1−1〜1−(N/n)と入力
N/n,出力N/nの2次スイッチ2−1〜2−2nと
入力2n,出力nの3次スイッチ3−1〜3−(N/
n)から構成され、1次スイッチ,2次スイッチ,3次
スイッチはclos接続されている。5はこの入力N,
出力Nのマトリクス回路4の接続制御,障害検出を行う
制御部で、この制御部5に1次スイッチでブロードキャ
スト(分岐)接続を行わせる機能を持たせている。
The matrix circuit 4 has inputs n,
Output 2n primary switches 1-1 to 1- (N / n) and input N / n, output N / n secondary switches 2-1 to 2-2n and input 2n, output n tertiary switch 3- 1-3- (N /
n), the primary switch, the secondary switch, and the tertiary switch are cross-connected. 5 is this input N,
In the control unit that controls the connection of the output N matrix circuit 4 and detects a failure, the control unit 5 is provided with a function of making a broadcast (branch) connection by a primary switch.

【0008】つぎにこの図1に示す実施例の動作を説明
する。まず、図1に示す入力aと出力bの接続が1次ス
イッチi,2次スイッチj,3次スイッチkを介して接
続されているときに2次スイッチjで障害が発生する
と、制御部5は1次スイッチiで入力aに対するブロー
ドキャストを行い、b1の接続,2次スイッチ2nでb2
の接続、3次スイッチkでa3 の接続を開放しb3
接続を行うことにより、2次スイッチjの障害を救済す
る。つぎに、制御部5は2次スイッチ2−2nを2次ス
イッチの障害救済が必要な場合のみ使用する。
Next, the operation of the embodiment shown in FIG. 1 will be described. First, when a failure occurs in the secondary switch j when the connection between the input a and the output b shown in FIG. 1 is connected via the primary switch i, the secondary switch j, and the tertiary switch k, the control unit 5 perform broadcast to the input a the primary switch i, the connection b 1, b 2 a secondary switch 2n
Connection, and the connection of a 3 is released by the tertiary switch k and the connection of b 3 is performed, thereby relieving the failure of the secondary switch j. Next, the control unit 5 uses the secondary switch 2-2n only when it is necessary to repair the failure of the secondary switch.

【0009】[0009]

【発明の効果】以上説明したように本発明の3段スイッ
チ装置は、2次スイッチを2n個持つことにより、1個
の2次スイッチを冗長的に使用するようにしたので、2
次スイッチに障害が発生し、その救済を行ってもブロッ
キングが発生することはないという効果を有する。ま
た、図1において、2次スイッチjの障害が復旧した場
合には3次スイッチkでb3 の接続をa3 に変更するこ
とで、元の接続に戻すことができるため、短時間の瞬断
で元の接続に戻すことができる効果がある。
As described above, since the three-stage switch device of the present invention has 2n secondary switches, one secondary switch is used redundantly.
This has an effect that the failure does not occur in the next switch even if the failure occurs in the next switch. Further, in FIG. 1, when the failure of the secondary switch j is recovered, the connection of b 3 can be changed to a 3 by the tertiary switch k to restore the original connection. There is an effect that it can return to the original connection by disconnecting.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明による3段スイッチ装置の一実施例を示
す系統図である。
FIG. 1 is a system diagram showing an embodiment of a three-stage switch device according to the present invention.

【図2】従来の3段スイッチ装置の一例を示す系統図で
ある。
FIG. 2 is a system diagram showing an example of a conventional three-stage switch device.

【符号の説明】[Explanation of symbols]

1−1〜1−(N/n) 1次スイッチ 2−1〜2−2n 2次スイッチ 3−1〜3−(N/n) 3次スイッチ 4 マトリクス回路 5 制御部 1-1 to 1- (N / n) primary switch 2-1 to 2-2n secondary switch 3-1 to 3- (N / n) tertiary switch 4 matrix circuit 5 control unit

─────────────────────────────────────────────────────
─────────────────────────────────────────────────── ───

【手続補正書】[Procedure amendment]

【提出日】平成6年4月22日[Submission date] April 22, 1994

【手続補正1】[Procedure Amendment 1]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】特許請求の範囲[Name of item to be amended] Claims

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【特許請求の範囲】[Claims]

【手続補正2】[Procedure Amendment 2]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】0004[Correction target item name] 0004

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【0004】[0004]

【課題を解決するための手段】本発明の3段スイッチ装
置は、入力N,出力N(N:整数)のマトリクス回路お
よびこの入力N,出力Nのマトリクス回路の接続制御,
障害検出を行う制御部から構成され、上記入力N,出力
Nのマトリクス回路は入力n,出力2n(n:整数)の
1次スイッチN/n個と入力N/n,出力N/nの2次
スイッチ2n個および入力2n,出力nの3次スイッチ
N/n個からなるクロス構成のマトリクス回路であり、
上記制御部に上記1次スイッチで分岐接続を行わせる機
能を持つようにしたものである。また、制御部は、2次
スイッチのいずれかで障害が発生したとき、2次スイッ
チの所定の1つを使用して、障害が発生した2次スイッ
チの回路をこの所定の2次スイッチの回路に切り替える
ようにしたものである
A three-stage switch device according to the present invention comprises a matrix circuit of input N and output N (N: integer) and connection control of the matrix circuit of input N and output N,
The matrix circuit having the input N and the output N comprises a primary switch N / n having an input n and an output 2n (n: an integer) and two input N / n and an output N / n. It is a matrix circuit of a cross configuration composed of 2n next switches and N / n third switches of input 2n and output n,
The control unit has a function of making a branch connection with the primary switch. In addition, the control unit
If one of the switches fails, the secondary switch
Use the desired one of the
Switch the circuit of H to the circuit of this predetermined secondary switch
It was done like this .

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 入力N,出力N(N:整数)のマトリク
ス回路およびこの入力N,出力Nのマトリクス回路の接
続制御,障害検出を行う制御部から構成され、前記入力
N,出力Nのマトリクス回路は入力n,出力2n(n:
整数)の1次スイッチN/n個と入力N/n,出力N/
nの2次スイッチ2n個および入力2n,出力nの3次
スイッチN/n個からなるクロス構成のマトリクス回路
であり、前記制御部に前記1次スイッチで分岐接続を行
わせる機能を持つようにしたことを特徴とする3段スイ
ッチ装置。
1. A matrix of an input N and an output N (N: integer) and a matrix of the input N and the output N matrix circuit, and a controller for performing connection control and fault detection. The circuit has n inputs and 2n outputs (n:
(Integer) primary switch N / n, input N / n, output N / n
A matrix circuit having a cross structure composed of 2n secondary switches of n and 3n switches N / n of input 2n and output n, and has a function of causing the control unit to perform branch connection with the primary switch. A three-stage switch device characterized in that
JP5139234A 1993-05-19 1993-05-19 Three-stage switch device Expired - Lifetime JP2737600B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5139234A JP2737600B2 (en) 1993-05-19 1993-05-19 Three-stage switch device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5139234A JP2737600B2 (en) 1993-05-19 1993-05-19 Three-stage switch device

Publications (2)

Publication Number Publication Date
JPH06334485A true JPH06334485A (en) 1994-12-02
JP2737600B2 JP2737600B2 (en) 1998-04-08

Family

ID=15240605

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5139234A Expired - Lifetime JP2737600B2 (en) 1993-05-19 1993-05-19 Three-stage switch device

Country Status (1)

Country Link
JP (1) JP2737600B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003009194A (en) * 2001-06-25 2003-01-10 Kddi Corp Optical crossconnect system and its controller and controlling method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5595490A (en) * 1979-01-12 1980-07-19 Nec Corp System switching system for exchange
JPH0296495A (en) * 1988-10-03 1990-04-09 Nec Corp Three-stage switch extending method
JPH03274819A (en) * 1990-03-23 1991-12-05 Nec Corp In-equipment signal route switching method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5595490A (en) * 1979-01-12 1980-07-19 Nec Corp System switching system for exchange
JPH0296495A (en) * 1988-10-03 1990-04-09 Nec Corp Three-stage switch extending method
JPH03274819A (en) * 1990-03-23 1991-12-05 Nec Corp In-equipment signal route switching method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003009194A (en) * 2001-06-25 2003-01-10 Kddi Corp Optical crossconnect system and its controller and controlling method

Also Published As

Publication number Publication date
JP2737600B2 (en) 1998-04-08

Similar Documents

Publication Publication Date Title
Armstrong A general method of applying error correction to synchronous digital systems
JP2849819B2 (en) switch
JP2745566B2 (en) How to extend a three-stage switch
JPH06334485A (en) Three-stage switch device
JP4182621B2 (en) Control signal input circuit
JPS61269493A (en) Multistage link connection network
JPH04160949A (en) Switching unit
JPH07321629A (en) Semiconductor equipment
JP2643578B2 (en) Self-diagnosis circuit
JP2730522B2 (en) Unit switching device and unit switching method
JP2583002B2 (en) Dual system time-division channel collation monitoring device
JPS6343558Y2 (en)
JPH036741A (en) Data output device for duplex system
JPH0685714A (en) Line switching method
JPH05300261A (en) Redundant configuration system in voice storage module
JPS60259026A (en) Automatic switching method in n:1 active spare equipment
JPH04137923A (en) Line switching circuit
JPS58154050A (en) Logical function module
JPH04267623A (en) Non-blocking type 3-stage switch
JPH0748716B2 (en) Hitless line switching circuit
JPH1013308A (en) N:1 redundant configuration system
JPH05108103A (en) Multiplexing controller
JPH0496802A (en) I/o unit device
JPH02213248A (en) Redundant constitution system
JPH02155403A (en) Automatic train controller