JPH06334311A - Manufacture of circuit body - Google Patents

Abstract

PURPOSE:To provide a manufacturing method of a circuit body wherein a large current circuit and a small current circuit which are different in thickness can be effectively formed. CONSTITUTION:Excepting a large current forming part, plating resist is stuck on a conducting layer formed on the surface of a board 1. High speed electrolytic plating layer is laminated on the large current circuit forming part on the conducting layer. First etching resist 7 is stuck on the high speed electrolytic plating layer. The plating resist is peeled by etching, and the conducting layer is exposed. Second etching resist is stuck on a small current circuit forming part on the conducting layer. Excepting the part position on which the second etching resist and the first etching resist are stuck, the conducting layer is peeled by etching, and a large current circuit 10 and a small current circuit 11 which are different in film thickness are formed. Elctrolytic solder plating may be used as the etching resist.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a circuit body in which a large current circuit and a small current circuit having different thicknesses are formed on a circuit board.

[0002]

2. Description of the Related Art FIGS.
This figure shows a conventional method of manufacturing a circuit body described in Japanese Patent Publication No. 88. In this manufacturing method, the copper foil layer previously formed on the surface of the insulating substrate 15 is removed by etching except for the circuit portions 16 and 17 as shown in FIG. 11, and the small current circuit 17 for signals is left as it is. A shield plate 18 is attached to the large current circuit 16, an epoxy insulating resin 19 is filled on the insulating substrate 15 as shown in FIG. 12, and the small current circuit 17 is buried in the insulating resin 19 and then the shield plate 18 is formed. And the electroless plating 20 is applied on the large current circuit 16 to remove the large current circuit 1.
6 is made a thick film, and finally the insulating resin 19 is removed to remove a thin film small current circuit 17 and a thick film large current circuit 1 as shown in FIG.
The circuit body 21 having 6'is completed.

However, in the above-mentioned conventional manufacturing method, the shield plate 18 having a shape matching the large-current circuit pattern of the various circuit bodies 21 must be prepared one by one, and the shield plate 18 is required.
However, there is a problem that it takes a long time to thicken the large-current circuit 16 because the electroless plating 20 has a low deposition rate of about 0.1 μm / min because of its poor versatility. there were.

[0004]

SUMMARY OF THE INVENTION In view of the above points, the present invention is a circuit body capable of efficiently forming a thick film large current circuit and a thin film small current circuit without using a shielding plate. It aims at providing the manufacturing method of.

[0005]

In order to achieve the above-mentioned object, the present invention is to deposit a plating resist on a conductive layer formed on the surface of a substrate except for a portion where a large current circuit is to be formed. High-speed electrolytic plating is laminated on the large current circuit planned part,
A first etching resist is deposited on the high-speed electrolytic plating, the plating resist is removed by etching to expose the conductive layer, and a second etching resist is deposited on a small current circuit planned portion on the conductive layer. , A circuit body in which a large current circuit and a small current circuit having different film thicknesses are formed by exfoliating the conductive layer by etching except for a portion adhered to the second etching resist and the first etching resist. The manufacturing method is basically used.

[0006]

Function: A plating resist is deposited on the conductive layer to form a large current circuit portion in a groove pattern. Then, high-speed electrolytic plating is performed in the groove to pattern the large current circuit. The first etching resist deposited on the rapid electrolytic plating protects the rapid electrolytic plating during etching of the plating resist. Then, by etching the conductive layer, a thin film small current circuit is formed in the pattern shape of the second etching resist on the conductive layer, and the conductive layer under the high-speed electrolytic plating is left to form a thick film large current circuit. It

[0007]

1 to 10 show an embodiment of a method of manufacturing a circuit body according to the present invention. In this manufacturing method, first, as shown in FIG. 1, a copper foil (35 to 70 μm) 2 as a conductive layer is attached to the surface of an insulating substrate 1 made of glass epoxy resin or the like, and as shown in FIG. A plating resist layer 4 such as a UV-curable resist agent is deposited on the copper foil 2 except for the planned portion 3 by printing. The large current circuit portion 3 is patterned in the plating resist layer 4 in a groove shape.

Next, as shown in FIG. 3, high-speed electrolytic plating 5 is applied to the large-current circuit planned portion 3, that is, the exposed portion of the copper foil, and laminated. As shown in FIG. 9, the high-speed electrolytic plating 5 has an electrode 6 formed on the substrate 1 in advance, and 10 to 80 A / a is provided between the cathode and the anode.
It energizes at a current density of dm ² and deposits a metal conductor (Cu) at a high speed of about 10 μm / min.

As shown in FIG. 4, solder plating 7 as a first etching resist is applied on the electrolytic plating 5. The solder plating 7 can deposit a thickness of 2 to 3 μm in a few seconds by electrolytic plating. Then, as shown in FIG. 5, the plating resist layer 4 is etched and stripped using an alkaline solution or the like. The electrolytic plating 5 is not affected by the etching due to the solder plating 7.

Further, as shown in FIG. 6, a second etching resist 9 is formed on the exposed portion of the copper foil 2 for a small current circuit for a signal circuit or the like by printing or the like. As the second etching resist 9, the same solder plating as that of the first etching resist 7 may be used. It is preferable that the solder is attached by electrolytic plating rather than printing the etching resists 7 and 9 because the process is easier and printing is not uneven.

Then, as shown in FIG. 7, the copper foil 2 is peeled off by etching except the portions where the etching resists (solder plating) 7 and 9 are adhered. As a result, the thick film large current circuit 10 and the thin film small current circuit 11 are formed on the insulating substrate 1. Finally, as shown in FIG. 8, the etching resist 9 is removed, and an insulating coating (not shown) such as a UV curable resist is applied to the surfaces of the circuits 10 and 11 by spraying or the like, and the above-mentioned electrode portion 6'is cut off so that the electrode 6'is removed. A circuit body 12 having two types of circuits 10 and 11 having different film thicknesses is obtained.

[0012]

As described above, according to the present invention, a high-current circuit can be formed on a conductive layer such as a copper foil by high-speed electrolytic plating. Therefore, the manufacturing time is significantly longer than that of conventional electroless plating. Shortened. Moreover, since a shielding plate having poor versatility is not required, the production efficiency of different types of circuit bodies is improved. Further, after patterning the large current circuit, the conductive layer is peeled off by etching to leave the small current circuit remaining, so that the degree of freedom in circuit design is expanded.

[Brief description of drawings]

FIG. 1 is a vertical cross-sectional view showing a state in which a copper foil is attached to an insulating substrate in the method for manufacturing a circuit body of the present invention.

FIG. 2 is a vertical cross-sectional view showing a state in which a plating resist is deposited on a copper foil except for a large current circuit planned portion.

FIG. 3 is a vertical cross-sectional view showing a state in which electrolytic plating is also plated on a large current circuit planned portion.

FIG. 4 is a vertical cross-sectional view showing a state in which an etching resist is similarly deposited on the electrolytic plating.

FIG. 5 is a vertical cross-sectional view showing a state in which the plating resist is also peeled off.

FIG. 6 is a vertical cross-sectional view showing a state in which an etching resist is deposited on a portion of the copper foil on which a small current circuit is to be formed.

FIG. 7 is a longitudinal sectional view showing a state in which a large current circuit and a small current circuit are similarly formed by peeling off the copper foil.

FIG. 8 is a vertical cross-sectional view showing a state in which the etching resist on the circuit is peeled off.

FIG. 9 is a plan view showing a state in which an electrode for electrolytic plating forming the large current circuit is formed.

FIG. 10 is a perspective view showing a completed circuit body.

FIG. 11 is an exploded perspective view showing a state in which a shielding plate is attached on a circuit in a conventional manufacturing method.

FIG. 12 is an exploded perspective view showing a state in which an insulating resin is filled on the substrate and the shielding plate is removed, similarly.

FIG. 13 is a perspective view showing a state in which a large current circuit is made thick by electroless plating.

[Explanation of symbols]

 1 Insulation substrate 2 Copper foil 3 Large current circuit planned part 4 Plating resist 5 High speed electrolytic plating 7,9 Etching resist 8 Small current circuit planned part 10 Large current circuit 11 Small current circuit

Claims (2)

[Claims] 1. A plating resist is deposited on a conductive layer formed on a surface of a substrate except for a large current circuit planned portion, and high speed electrolytic plating is laminated on the large current circuit planned portion on the conductive layer,
A first etching resist is deposited on the high-speed electrolytic plating, the plating resist is removed by etching to expose the conductive layer, and a second etching resist is deposited on a small current circuit planned portion on the conductive layer. , The conductive layer is removed by etching except for a portion adhered to the second etching resist and the first etching resist to form a large current circuit and a small current circuit having different film thicknesses. And a method for manufacturing a circuit body. 2. The method for manufacturing a circuit body according to claim 1, wherein electrolytic solder plating is used as the etching resist.