JPH06332846A - Bus repeater - Google Patents

Abstract

PURPOSE:To provide a bus repeater for shortening the time of data transfer over two buses by simple constitution. CONSTITUTION:This bus repeater 11 is provided with a bus access register 21 for storing information for indicating the presence/absence of access between the buses and a bus arbiter 18 for arbitrating a request signal to the bus and also requesting utilization to the bus different from the bus managed by itself when a signal for requesting the utilization of the bus is inputted in a state where the contents of the bus access register indicate the access between the buses.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus relay device,
For example, the present invention relates to a bus relay device that connects buses each having a device that can be a bus master to enable data transfer between two buses.

[0002]

2. Description of the Related Art A bus relay device is a device for connecting buses each having a bus master, and a device which enables a bus master of a bus to access a device on a bus different from the bus to which the bus master is connected. Is. Conventionally, in such a case, after acquiring the bus on the master side, the address information for the device on another bus is output to the bus on the master side, and a request for using the other bus is issued according to the address information. .

FIG. 7 shows a circuit configuration of a bus relay device in this case. The bus relay device 11 includes two external buses 1
Address decoder 15 and bus arbiter 16 for bus 12, address decoder 17 and bus arbiter 18 for bus 13, and address / data buffer 19 which is a buffer for address and data of two buses and this address A buffer control circuit 20 that controls the data buffer 19 is used. A bus master 25 and a bus slave 26 are connected to the external bus 12,
A bus master 27 and a bus slave 28 are connected to the bus 13. Originally, a device that has obtained permission to use the bus becomes the bus master, but here, it is called a bus master even when the device has not obtained use permission.

FIG. 8 shows the operation timing when the bus master 27 makes a data request to the bus slave 26 connected to a bus different from its own bus and receives the data in this bus relay device. In the figure, the bus 12 is described as a system bus, and the bus 13 is described as an I / O bus.

First, the bus master 27 operates as the bus arbiter 1.
By issuing the bus use request signal 103 to the bus 8, the use request of the bus 13 is issued. Bus use request signal 10
When the bus 13 is not busy, the bus arbiter 18, which has received 3, outputs the bus use permission signal 104 to the bus master 27 (i). The bus master 27 receiving the bus use permission signal 104 outputs address information corresponding to the bus slave 26 connected on the bus 12 (ii). The output address information is decoded by the address decoder 17, and it is recognized that the slave is connected to the bus 12. As a result, the address decoder 17 issues a request to use the system bus 12 to the bus arbiter 16 that manages the bus 12 (iii). The bus arbiter 16 that has received the usage request confirms the usage status of the system bus, and if the bus is not busy, issues a bus usage permission (i.
v). The buffer control circuit 20 controls the address / data buffer according to the bus use permission signal and supplies the address onto the bus 12 (v). On the bus 12, the bus slave 26 supplies data according to the address supplied on the bus, and this data is received by the bus master 27 on the I / O bus 13 via the address / data buffer 19 (vi). After this, the bus use permission signal given to the bus master 27 is canceled and the data read operation is terminated (vi
i).

In this bus relay device 11, since permission to use each bus is sequentially requested as shown in the figure, it takes time to acquire both buses when transferring data between the two buses. There was a problem that it took time. As a device for solving this problem, Japanese Patent Publication No.
Japanese Patent Publication No. 365 has proposed a bus relay device described below.

FIG. 9 shows a circuit configuration of this device. Circuits and units corresponding to the configuration of the bus relay device shown in FIG. 7 are denoted by the same reference numerals, and description of common parts will be omitted. In this bus relay device, new bus request signal lines 105 and 107 are provided between the bus master and the two bus arbiters, and bus use permission signals 106 and 108 for responding thereto.
And are added. That is, this bus relay device
The circuit configuration of the bus master itself is different from the conventional one, and it is premised on the use of a bus master capable of outputting a plurality of bus request signals. When the above-mentioned bus master 27 accesses the bus slave 26 via the bus relay device 11, the bus master 27 uses the bus use request signal 108 to issue a bus use request to the bus arbiter 16 and the bus arbiter 18 at the same time. ing. Therefore, the problem that it takes time to acquire both buses as described above is solved.

[0008]

In the bus relay device described in the latter half of the conventional example, the problem that it takes a long time to acquire a bus has been solved, but in order to realize it, the bus master must have as many buses as there are buses. Since the use request signal and the use permission signal are connected, there is a problem in that an existing bus master that supports only one set of bus use request signal and bus use permission signal cannot be used.

Therefore, an object of the present invention is to provide a bus relay device which can shorten the access time across two buses with a simple device configuration using an existing bus master.

[0010]

According to a first aspect of the present invention, there is provided a bus relay means for relaying access between a system bus to which a processor is connected and a predetermined bus different from the system bus, and whether or not the bus relay means is used. The inter-bus access information storage means for storing inter-bus access information indicating that the contents can be rewritten from the processor, and the contents of the inter-bus access information storage means when a bus use request is issued from a device on a predetermined bus. Bus access information discriminating means for discriminating whether or not the information indicates that the bus relay means is used, and when the inter-bus access information discriminating means discriminates not to perform inter-bus access, the predetermined bus Arbitrates the usage request to the device and grants the device the right to use the bus, and when it determines that inter-bus access is to be performed, gives the device the right to use the specified bus Together and a bus arbitration means to acquire the right to use issues a use request to the system bus.

That is, according to the first aspect of the invention, the inter-bus access information storage means for indicating whether or not the access is between two buses, and the information stored in the access information storage means,
Bus arbitration means for issuing a request to use the bus on the accessed side is provided. In this system, since there is only one processor, writing of information in the inter-bus access information storage means is performed by the processor connected to the bus on the accessed side. As a result, the object of shortening the access time across two buses can be achieved with a simple device configuration using the existing bus master and bus arbiter.

According to a second aspect of the present invention, there is provided bus relay means for relaying access from one bus to the other bus between the two buses, and whether the bus relay means is provided corresponding to each bus. Inter-bus access information storage means that stores inter-bus access information indicating whether or not the contents can be rewritten from the corresponding bus, and supports the bus when a bus use request is issued from a device on one bus The inter-bus access determination means for determining whether the content of the inter-bus access information storage means is information indicating that the bus relay means is used, and the inter-bus access determination means determines that the inter-bus access is not performed. When it does, it arbitrates the usage request for the predetermined bus and gives the right to use the bus to the device,
When it is determined that the bus access is to be performed, the device is provided with a bus arbitration means for giving the device a right to use the bus and issuing a use request to the other bus to obtain the right to use the bus.

That is, according to the second aspect of the present invention, inter-bus access information storage means for indicating whether or not the access is between two buses is provided, and the access side of the access side is provided according to the information stored in the inter-bus access information storage means. Bus arbitration means for issuing bus use requests is provided. The inter-bus access information storage means can be written from the bus requesting inter-bus access. As a result, the object of shortening the access time across two buses can be achieved with a simple device configuration using the existing bus master and bus arbiter.

According to a third aspect of the present invention, bus relay means for relaying access from one bus to the other bus between two buses and bus relay means provided corresponding to each bus are used. Inter-bus access information storage means for storing inter-bus access information indicating whether or not, access frequency measuring means for respectively measuring access frequency from one bus to the other bus, and a measurement result of this access frequency measuring means is predetermined. When the value is larger than the value of, the information indicating the inter-bus access using the bus relay means is written in the inter-bus access information storage means corresponding to one bus, and in other cases, the information indicating the non-inter-bus access is written. Inter-bus access information rewriting means for writing and the inter-bus access corresponding to that bus when a bus use request is issued from a device on one bus Inter-bus access determination means for determining whether or not the content of the information storage means is information indicating that the bus relay means is used, and when the inter-bus access determination means determines that inter-bus access is not performed, the predetermined Arbitrates the use request for the bus, gives the device the right to use the bus, and when it determines that inter-bus access is to be performed, gives the device the right to use the bus and issues a use request to the other bus Bus arbitration means for acquiring the right of use.

That is, according to the third aspect of the invention, inter-bus access information storage means for indicating whether or not the access is between two buses is provided, and the access side is stored according to the information stored therein. Bus arbitration means for issuing bus use requests is provided. The writing of information to the inter-bus access information storage means is performed by measuring the frequency of inter-bus access. As a result, the object of shortening the access time across two buses can be achieved with a simple device configuration using the existing bus master and bus arbiter.

[0016]

EXAMPLES The present invention will be described in detail below with reference to examples.

FIG. 1 shows a circuit configuration of a bus relay apparatus according to an embodiment of the present invention. This bus relay device 11
Is used by being connected to two external buses. Here, a bus relay device is used in a system in which one is a system bus 12 to which a processor is connected and the other is an I / O bus 13. In the bus relay device, an address decoder 15 and a bus arbiter 16 for the system bus 12,
Address decoder 17 and bus arbiter 18 for I / O bus 13, address / data buffer 19 which is a buffer for address and data of two buses, and buffer control circuit 20 and bus access register 21 for controlling this address / data buffer 19 Composed of. The system bus 12 includes a processor 29 that is a master of the system bus.
Is connected to the storage device 30 that is a bus slave,
A bus master 27 and a bus slave 28 are connected to the O-bus 13. The processor 29 uses the bus master 27
Holds the information designating the operation contents for the interrupt signal from the bus master. The details will be described later, but the bus master is activated based on this information for the interrupt signal.

The bus access register 21 stores information as to whether or not the master on the I / O bus 13 accesses the slave on the system bus 12. here,
A 1-bit value is used as this information, and this value is "
The value "1" indicates that the access from the bus master 27 to the storage device 30, which is a slave on the system bus, is performed in the data transfer mode which is a feature of this bus relay device. The data between the buses in the case of "0" Are exchanged using an address decoder as in the conventional case.

The operation of the bus relay device of this embodiment will be described below. Here, it is assumed that the bus master 27 on the I / O bus accesses the storage device 30 on the system bus.
This operation includes interrupts to the processor, acquisition of two buses, and data transfer operations. First, the interrupt operation for the processor will be described.

FIG. 2 shows a flow of operation of the processor when the bus master 27 interrupts the processor 29. The bus master 27 uses the interrupt signal line 121 to interrupt the processor 29 (step S10).
1). The interrupt signal line is also used in the conventional system. The processor 29
When an interrupt is issued, the operation being performed at that time is interrupted, the device that issued the interrupt request is identified (step S102), and if the interrupt is from the bus master 27 (step S103; Y). ) Is
"1" is written in the bus access register 21 (step S104), and then information including the address and the number of words in the storage device 30 is given to the bus master 27 (step S104).
105) and activate the bus master 27 (step S
106). It should be noted that this series of operations is performed according to the information managed by the processor 29. If the interrupt request is a request from another bus master (step S103; N), the process according to the device that made the request is performed (step S107).

The step S102 is shown. The interrupt request identification operation may include as many interrupt request lines as there are bus masters, and so-called polling is performed to confirm the device requesting the interrupt by receiving the OR signal of the interrupt request signals from each bus master. It may be executed. Information is transferred to the bus master 27 in step S105 by requesting the bus arbiter 18 to use the I / O bus 13 via the address decoder 15.

The bus master 27 thus activated by the processor 29 performs the actual data transfer by the following operation.

In FIG. 3, the content of the access register is "1".
Shows the flow of the data transfer operation. First, the activated bus master 27 outputs a bus use request signal 103 requesting use of the I / O bus 13 (step S201), and the bus arbiter 18 receiving this signal
Check the contents of the bus access register 21 and confirm that
If it is "1", the use permission of the I / O bus 13 is given to the bus master 27 using the bus use permission signal line 104 (step S202), and the bus use request signal 111 requesting the use of the system bus 12 is sent to the bus arbiter 1
6 (step S203). As a result, the request for use of the system bus is issued at a faster stage than the request for use of the bus via the address decoder. The bus arbiter 16 confirms the usage status of the system bus 12, and outputs the usage permission signal 112 of the system bus 12 when the usage is possible, and the bus arbiter 18 receives the usage permission of the system bus (step S204). . When the use permission of the system bus 12 is obtained, the buffer control circuit 20 controls the address / data buffer 19 to supply the address to the system bus 12 (step S205). The storage device 30 supplies the data corresponding to this address on the bus (step S206), and the bus master 27 receives this (step S207), and ends the transfer of one data. This operation is repeated as many times as necessary (step S208; N), and when the transfer of the necessary data is completed (step S208; Y), the bus master 27 interrupts the processor (step S2).
09), and notifies the processor 29 of the end of the data transfer operation. The processor rewrites the contents of the bus access register to "0" in response to this interrupt (step S21).
0) End a series of operations.

FIG. 4 shows the timing of the operation described above. Here, the timing until the transfer of one data is completed, that is, step S201 to step S2
The timing up to 07 is shown. In this bus relay device, since it is possible to determine that the access is between buses by reading the contents of the bus address register, it is not necessary to decode the address, and before the address is supplied onto the bus, A usage request for the I / O bus can be issued as shown in a). For this reason, it is not necessary to wait for the address to be supplied on the bus unlike the conventional bus relay apparatus using the address decoder, so that the time until the data transfer is completed is shortened.

The timing itself is almost the same as that of the device in which the bus master makes a bus request to two arbiters at the same time as shown in the conventional example, and the similar access speed can be obtained with a simple structure.

In this bus relay device, the data transfer operation is described as being started by an interrupt from the bus master on the I / O bus, but this operation may be started by an instruction from the processor. Is natural.

First Modification

FIG. 5 shows an outline of the circuit configuration of the bus relay device in the first modification. This bus relay device has two bus access registers 22 and 23, and each bus access register is wired so that its contents can be referred to by a bus arbiter that manages a bus to which the bus access register is connected. . This bus relay device is connected to two buses on which a bus master having processor class processing capability is mounted.

For example, when the bus master 27 accesses the storage device 30 on a different bus, the bus master 27 receives the bus use permission from the bus arbiter 18,
Write “1” in the bus access register 23. When a bus use request is received, the bus arbiter 18 always refers to the contents of the bus access register 23,
When it is "1", in addition to performing arbitration for the bus requested to be used, a use request signal 112 for the bus 12 is output to the bus arbiter 16. In this bus relay device, the bus to which the address register is connected and its The bus connected to the bus arbiter that refers to the contents is the same bus,
Other operations are the same as those shown in the embodiment. Therefore, the timing of data transfer becomes the same as that shown in FIG. 4, and the data transfer can be performed in a shorter time than the data transfer using the address decoder. For access from the bus 12 to the bus 13, the bus arbiter 16 refers to the contents of the bus access register 22, and the bus use request signal 1
This is done by requesting the use of the bus 13 using 14. In this bus relay device, if data transfer between buses is performed by using a bus access register, it is not necessary to provide an address recorder.

Second modification

In the bus relay device in the embodiment and the first modification, the device on the bus writes the address. However, the frequency of access between the buses is detected, and the operation of the bus arbiter is thereby detected. The device can also be configured to direct.

FIG. 6 shows an outline of the circuit configuration of the bus relay device of the second modification. In the figure, description of the circuits already described is omitted. This device is provided with inter-bus access monitoring circuits 35 and 36 for monitoring the signal line from the address decoder to the bus arbiter. The inter-bus access monitoring circuits 35 and 36 monitor the signal line from the address decoder to the bus arbiter and count the number of accesses within a predetermined time. When the count value is larger than a predetermined value, the bus access existing inside the circuit Write "1" to the register.
In this device, when the access between buses using the address decoder continues, the inter-bus access monitoring circuit determines to the bus arbiter that the inter-bus access is being performed, and notifies the bus arbiter of that fact. Is output, the two bus request signals are almost simultaneously output during the subsequent inter-bus access, and the data transfer speed is increased.

It is also easy to rewrite the contents of the bus access register by using a changeover switch such as a dip switch instead of using a device such as a processor. In this case, when accessing between buses, the user switches the switch to change the operation mode of the bus relay device to a state capable of high-speed transfer.

[0034]

As described in detail above, according to the invention of claim 1, a bus master other than the bus master to which the bus master is connected is simply added to the existing bus master without changing the existing bus master. Since it becomes possible to quickly make a bus use request to another bus when accessing, it is possible to shorten the time as a whole access. This bus relay device is particularly effective when only devices that can perform only simple operations are connected to the I / O bus.

According to the second aspect of the present invention, when the bus master accesses a bus other than the one to which the bus master is connected by simply adding a simple circuit without changing the existing bus master, another bus master Since it becomes possible to quickly request the bus to be used, the total access time can be shortened.

According to the third aspect of the present invention, when the bus master accesses a bus other than the one to which the bus master is connected, it does not change the existing bus master and only adds a simple circuit. Since it becomes possible to quickly request the bus to be used, the total access time can be shortened. Further, since the switching of the operation mode is performed by the bus relay device detecting the access status between the buses, it is necessary to write the information about the inter-bus access such as the bus access register before the bus master starts the data transfer. There is also the advantage of not having.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration of a bus relay device according to an embodiment of the present invention.

FIG. 2 is a flow chart showing a flow of an operation of writing information indicating performing inter-bus access into a bus access register of a bus relay device according to an embodiment.

FIG. 3 is a flowchart showing a flow when a bus master on the I / O bus accesses a bus slave on the system bus via the bus relay device of the embodiment.

FIG. 4 is a timing chart showing the timing of each signal when a bus master on the I / O bus accesses a bus slave on the system bus via the bus relay device of the embodiment.

FIG. 5 is a block diagram showing a circuit configuration of a bus relay device according to a first modified example of the present invention.

FIG. 6 is a block diagram showing a circuit configuration of a bus relay device according to a second modified example of the present invention.

FIG. 7 is a block diagram showing a circuit configuration of a conventional bus relay device.

FIG. 8 is a timing chart showing timings of respective signals when a bus master on an I / O bus accesses a bus slave on a system bus via a conventional bus relay device.

FIG. 9 is a block diagram showing a circuit configuration of a bus relay device that simultaneously outputs a bus use request signal to the two buses described in the conventional example.

[Explanation of symbols]

11 ... Bus relay device, 12 ... System bus, 13 ... I /
O-bus, 15, 17 ... Address decoder, 16, 18 ...
Bus arbiter, 19 ... Address data buffer, 20 ...
Buffer control circuit, 21, 22, 23 ... Bus access register, 25, 27 ... Bus master, 26, 28 ... Bus slave, 29 ... Processor, 30 ... Storage device, 35, 3
6 ... Bus access monitoring circuit, 101, 103, 10
5, 107, 111, 113 ... Bus use request signal line, 1
02, 104, 106, 108, 112, 114 ... Bus use permission signal line, 121 ... Interrupt signal line

Claims (3)

[Claims] 1. A bus relay means for relaying access between a system bus to which a processor is connected and a predetermined bus different from the system bus, and inter-bus access information indicating whether or not to use the bus relay means are stored from a processor. An inter-bus access information storage means capable of rewriting the contents, and a content of the inter-bus access information storage means using the bus relay means when a bus use request is issued from a device on the predetermined bus. The inter-bus access information discriminating means for discriminating whether or not it is information, and when the inter-bus access information discriminating means discriminates not to perform the inter-bus access, the use request for the predetermined bus is arbitrated and the device When a bus access right is given to the device and it is determined that access between buses is to be made, the device is given the right to use the specified bus and used for the system bus. A bus relay device comprising a bus arbitration means for issuing a request and acquiring the right to use the request. 2. A bus relay means for relaying access from one bus to the other bus between two buses, and a bus provided corresponding to each bus and indicating whether or not the bus relay means is used. Inter-bus access information storage means for storing inter-bus access information and rewriting the contents from the corresponding bus, and the inter-bus access corresponding to the bus when a bus use request is issued from a device on one bus An inter-bus access determining means for determining whether or not the content of the information storing means is information indicating that the bus relaying means is used, and when the inter-bus access determining means determines that the inter-bus access is not performed, When a request for use of a predetermined bus is arbitrated and the right to use the bus is given to the device, and when it is determined that inter-bus access is performed, the right to use the bus is given to the device. A bus relay apparatus comprising a bus arbitration means for issuing a usage request to the other bus and acquiring the usage right. 3. Bus relay means for relaying access from one bus to another bus between two buses, and a bus provided corresponding to each bus and indicating whether or not the bus relay means is used Inter-bus access information storage means for storing inter-bus access information, access frequency measuring means for measuring access frequency from one bus to the other bus respectively, and when the measurement result of the access frequency measuring means is larger than a predetermined value Into the inter-bus access information storage means corresponding to the one bus, information indicating the inter-bus access using the bus relay means is written, and in other cases, information indicating non-inter-bus access is written Inter-bus access information rewriting means and the inter-bus access information corresponding to the bus when a bus use request is issued from a device on one bus. Inter-bus access determination means for determining whether or not the content of the storage means is information indicating that the bus relay means is to be used, and when the inter-bus access determination means determines not to perform inter-bus access, the predetermined Arbitrates the usage request for the bus to give the right to use the bus to the device, and when it is determined that inter-bus access is to be performed, the right to use the bus is given to the device and the usage request is issued to the other bus A bus relay device, comprising: a bus arbitration unit that acquires a usage right.