JP2001282707A - Device and method for controlling bus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a device and method for controlling bus, which perform processing of retry in a short time, can prevent the transaction processing of useless retry, and further, are inexpensive. SOLUTION: This device is provided with a common bus 10 for transferring data between master devices A, C and E and target devices B and D and a busy signal line busy for connecting the master devices and the target devices and when the target device can not quickly respond to the request of data transfer from the master device, a busy signal to be sent to the busy signal line is asserted. In response to the assert of the busy signal from the buster signal line, the master device releases the common bus by interrupting data transfer with the target device and in response to the deassert of the busy signal from the busy signal line, the data transfer is restarted from the time point of interruption.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus control device and a bus control method suitable for an information processing device having a plurality of master devices and a plurality of target devices connected to a common bus. Related to improving technology.

[0002]

2. Description of the Related Art Conventionally, there has been known an information processing apparatus comprising a plurality of master devices (hereinafter simply referred to as "master") connected to a common bus and a plurality of target devices (hereinafter simply referred to as "target"). I have. In such an information processing apparatus, several methods are employed to avoid contention for data transfer on a common bus. Hereinafter, a non-split information processing apparatus using weights and a split information processing apparatus using retries will be described as typical examples.

FIG. 11 shows a configuration of an information processing apparatus employing a non-split system. In this information processing device, contention for data transfer occurring on the common bus is avoided by using weights. The information processing apparatus includes a master A, a master C, a target B, a target D, and an arbiter 20 connected to a common bus 10.

The operation of the information processing apparatus will be described with reference to a timing chart shown in FIG. This timing chart shows a read operation in which the master A reads data from the target B. The master A first sends a bus use request to the arbiter 20 using a signal line (not shown). The arbiter 20 uses the common bus 10
Is available, a bus use permission is returned using a signal line (not shown). Master A, having received the bus use permission, sends an access request to target B and, as shown in FIG. 12 (A), enables its bus driver (not shown) to enable common bus 1.
Send the address of target B to 0.

[0005] The target B, which has received the access request from the master A, starts a process corresponding to the access request if it can respond to the access request. However, when the target B receives the read access request, there are many cases where the data is not yet prepared in the buffer memory inside the target B. Therefore, the target B
Cannot immediately respond to the read access request.

In such a case, the target B asserts a wait signal to the master A as shown in FIG. As a result, as shown in a period T2 in FIG. 12A, the master A enters the wait state while occupying the common bus 10. When the target B has the data in the buffer memory therein, the target B deasserts the wait signal as shown in FIG. 12B and the bus driver (shown in FIG. 12C) as shown in FIG. No) to send data to the common bus 10. The master A takes in the data on the common bus 10, and the transaction ends.

In the information processing apparatus of the non-split type configured as described above, the master A occupies the common bus during the wait period T2, even though no data transfer is performed. As a result, the use efficiency of the common bus is poor, and the performance of the entire information processing apparatus is reduced.

FIG. 13 shows the configuration of an information processing apparatus employing the split system. In this information processing apparatus, contention for data transfer occurring on the common bus is avoided by using a retry. The information processing apparatus includes a master A, a master C, a target B, a target D, and an arbiter 20 connected to a common bus 10.

The operation of the information processing apparatus will be described with reference to a timing chart shown in FIG. This timing chart shows a write operation in which the master A writes data to the target B. Master A
As shown in FIG. 4 (B), first, a req signal indicating a bus use request is sent to the arbiter 20. Arbiter 20
FIG. 14 shows that the common bus 10 can be used.
As shown in (C), a gnt signal indicating permission to use the bus is returned to the master A. The master A, which has received the gnt signal, sends a read access request to the target B and, as shown in FIG. 14A, enables the bus driver (not shown) to connect to the common bus 10. Send the address of target B.

If the target B receiving the access request from the master A cannot immediately respond to the access request, the target B sends a retry signal indicating a retry request to the master A and the arbiter 20 as shown in FIG. Return to. Master A that has received this return signal
Starts a timer (not shown) and starts measuring a retry time. Further, the master A is in the period T in FIG.
As shown in FIG. 2, the bus driver (not shown) is disabled, the transaction is temporarily terminated, and the common bus 10 is released. Further, the arbiter 20 receiving the retry signal cancels the gnt signal.

Therefore, after the common bus 10 is released,
Master C can initiate a transaction with target D. In this case, the master C is the arbiter 2
The arbiter 20 sends a req signal to the master C and sends a gnt signal to the master C if the common bus 10 is in a usable state. Master C receiving this gnt signal
Sends a write access request to the target D, for example, and enables the bus driver to send the address of the target D to the common bus 10 as shown in FIG. The target D, which has received the access request from the master C, does not return a return signal if it can immediately respond to the access request. As a result, the master C sends data to the common bus 10 following the address, as shown in FIG.
The target D receives the data on the common bus 10, and the transaction ends.

When the retry time has elapsed, the master A sends a req signal to the arbiter 20 again, as shown in FIG. The arbiter 20 returns a gnt signal to the master A when the common bus 10 is available. The master A that has received the gnt signal sends an access request to the target B again, and
As shown in FIG. 4A, the bus driver is enabled and the address of the target B is transmitted to the common bus 10.

The target B that has received the access request
Is ready to respond to the access request,
As shown in FIG. 14 (A), the return signal is
Do not return to. Thereby, the master A sends data to the common bus following the address. The target B receives the data on the common bus 10, and the transaction ends.

In the split-type information processing apparatus configured as described above, after the retry time has elapsed, the master A transmits arbitration such as transmission of a req signal and reception of a gnt signal and transmission of an address (FIG. 1).
(Shaded area 4) must be performed again, and the time required for these steps reduces the use efficiency of the common bus.
In addition, since the retry time is generally fixed, the timing at which the master A performs the retry operation does not coincide with the timing at which the target B enters the ready state, and a useless retry transaction may be performed.

As a technique for solving such a problem, for example, a "common bus control system" is disclosed in Japanese Patent Application Laid-Open No. Sho 60-77254. In this common bus control method, data transfer is performed between a first module and a second module connected to the common bus using the common bus. In this case, the first module acquires the right to use the common bus, issues a data transfer request to the second module via the common bus, and the second module detects a data transfer request addressed to itself. If the data transfer cannot be performed immediately at the point of time, the second module activates the first signal provided to the first module, notifies the first module of the activation, and grants the right to use the bus. The first signal line is deactivated and notified to the first module when data transfer is ready, and the first module obtains the right to use the bus again by the notification and transmits the data. I do.

This common bus control method is used between a first module and a second module connected to a common bus, using the common bus to switch from the first module to the second module.
Data is transferred to the module. In this case, the first module acquires the right to use the common bus, issues a data transfer request to the second module via the common bus, and the second module detects a data transfer request addressed to itself. If the data transfer completion cannot be immediately notified to the first module when the data is received, the second signal provided to the first module is activated from the second module to activate the second module. To the first module to release the right to use the bus. After that, when it becomes possible to notify the completion of data transfer, the second signal line is deactivated and notified to the first module. With the notification, the first module acknowledges the completion of the data transfer.

Japanese Patent Application Laid-Open No. 10-262070 discloses a "data processing system". In the data processing system, a plurality of devices transmit and receive packets to and from each other using a common bus, each device outputs a use request signal of a common bus having a predetermined priority prior to packet transmission, and a bus arbiter There is provided control means for arbitrating the common bus use request signal and determining a device to use the common bus according to the priority and giving permission. Each device has means for outputting a request signal for use of the common bus and outputting information indicating its transfer partner, and the bus arbiter has means for receiving the information. When the command packet buffer is busy and cannot receive a new command packet, it is configured to have a bus arbiter or a means for transmitting information such as the status to all devices. With this configuration, efficient bus control can be performed when a packet format command and data are transferred using the common bus.

[0018]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
The “common bus control method” disclosed in Japanese Patent Publication No. 254 corresponds to the split method described above. When this common bus control method is used, the right to use the common bus is released during one data transfer, so that the occupation time of the common bus is reduced. However, when the master performs a retry, it is still necessary to perform the arbitration work again, and the problem that the time required for the arbitration work reduces the use efficiency of the common bus has not been solved.

A "data processing system" disclosed in Japanese Patent Application Laid-Open No. 10-262070 also corresponds to the above-described split system. In this data processing system, the busy state of each target is notified to the arbiter or each master. Therefore, each master, by referring to the signal from the arbiter or the signal from the target, suppresses the issuance of a retry transfer request if the target is busy.

According to this data processing system, the problem of the split method described above is solved, but information indicating a transfer partner and information indicating an unreceivable state are transmitted and received between each master and each target. Therefore, there is a problem that wiring and hardware are required for this, and the device becomes complicated and expensive.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem. The present invention is capable of performing retry processing in a short time and preventing unnecessary transaction processing of retry from being performed. It is an object to provide a device and a bus control method.

[0022]

According to a first aspect of the present invention, there is provided a bus control apparatus, comprising: a common bus for performing data transfer between a master device and a target device; A control unit for providing a busy signal line connecting the master device and the target device, wherein the target device asserts a busy signal to be transmitted to the busy signal line when the target device cannot immediately respond to a data transfer request from the master device. Wherein the master device interrupts data transfer to and from the target device in response to the busy signal from the busy signal line being asserted to release the common bus, and the busy signal line And a controller for restarting the data transfer from the point of interruption in response to the deassertion of the busy signal from.

A bus control method according to a second aspect of the present invention is a bus control method for performing data transfer between a master device and a target device using a common bus for the same purpose as described above. The target device asserts a busy signal when it cannot immediately respond to a data transfer request from the master device, and the master device responds to the target device in response to the busy signal being asserted. The data transfer is interrupted to release the common bus, and the master device is configured to resume the data transfer from the interrupted point in response to the de-assertion of the busy signal.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to FIGS.
A case will be described as an example where the present invention is applied to an information processing apparatus in which two masters and two targets are connected to a common bus. In the following, in order to simplify the description, illustration and description other than those necessary for understanding the present invention are omitted.

[Embodiment 1] (1-1) Schematic description of information processing apparatus: In an information processing apparatus to which a bus control apparatus according to Embodiment 1 of the present invention is applied, data between a master and a target is used. In the transfer,
When the master suspends the operation by receiving the busy signal from the target and releases the common bus, the busy
After the signal is released, the master whose operation has been suspended always operates.

FIG. 1 is a block diagram showing a configuration of an information processing apparatus to which the bus control device according to the first embodiment of the present invention is applied. This information processing device includes a master A, a master C, a master E, a target B, a target D, a common bus 10, a control bus 11, and an arbiter 20. The master A, the master C, the master E, the target B, and the target D are interconnected by a common bus 10.

The masters A, C and E (hereinafter collectively referred to simply as “master” unless otherwise required) are:
It comprises a CPU, a DMA and the like. Also, target B
And D (hereinafter, simply referred to as “target” unless otherwise required) are constituted by a memory controller, a disk controller, a display controller, and the like. Although not shown, external devices such as a memory device (DRAM, page ROM, etc.), a disk device, a serial I / O device, etc. are connected to each target.

The common bus 10 is a bidirectional bus for transmitting and receiving addresses and data in a time-division manner, and has a bus width of n bits. This common bus 10 is used for the master to send address and data to the target and for the target to send data to the master. In this information processing apparatus, a command bus is provided for the master to send a command specifying the operation of the target to the target. However, since the command bus is not directly related to the features of the present invention, illustration and description are omitted.

The control bus 11 is used for transmitting and receiving control signals between the master and the target. The control signal includes a busy signal, a cycleA signal, c
A cycleC signal, a cycleE signal, and a ready signal are included. The busy signal is used to notify each master and the arbiter 20 that each target is busy, that is, cannot respond immediately to an access request from the master.

The cycle A signal, the cycle C signal, and the cycle E signal correspond to the master A, the master C, and the master E.
Are used to inform the targets B and D and the arbiter 20 that they are in operation, respectively. rea
The dy signal is used to notify masters A, C and E that targets B and D have sent data to common bus 10 and are ready to receive data. In the following, the cycle A signal, c
The cycle signal and the cycle E signal are collectively referred to simply as the cycle signal unless it is necessary to particularly distinguish them.

The masters A, C and E are connected to the common bus 10
, And a reqA signal, a reqC signal, and a reqE signal (hereinafter, simply referred to as “req signals” unless otherwise required) to the arbiter 20. Further, the masters A, C, and E transmit the gntA signal, the gntC signal, and the gntE signal (hereinafter referred to as “gnt signal unless otherwise necessary”) which permit the use of the common bus 10 and are transmitted from the arbiter 20. ) Are sent to the target B or D, respectively. Targets B and D are
Various processes are performed in response to an access request from the master. The detailed configuration and operation of this target will be described later.

The arbiter 20 arbitrates the right to use the common bus 10. That is, the arbiter 20 receives r
When an eq signal is received, a gnt signal is sent to a master with a higher priority. Only the master that has received the gnt signal can use the common bus 10 to send and receive data to and from the target.

The general operation of the information processing apparatus configured as described above will be described. When accessing the target, the master first sends a req signal to the arbiter 20. Then, when the gnt signal is sent from the arbiter 20, the access request is sent to the target. When the target that has received the access request cannot respond to the access request immediately, it asserts the busy signal.

The arbiter 20 constantly monitors the busy signal, and releases the common bus 10 to another master when the target waits by the busy signal. When the busy signal is deasserted by the target, the transaction of the master to which the wait has been started is started without arbitration being performed again.

By the above operation, it is possible to improve the use efficiency of the common bus in the information processing device which requires a long time for sending and arbitration of the address.

(1-2) Detailed Description of Master: Next, the detailed configuration of the master will be described with reference to the block diagram shown in FIG. The master is roughly composed of a bus interface block 30 and a device control block 31. Bus interface block 30
Controls transmission and reception of signals between the master and the common bus 10. The device control block 31 includes a CPU,
It is composed of DMA and the like.

The bus interface block 30, and a state machine 32, output control block 33 and the bus control block 34 ₁ ~34 _n.

The state machine 32 controls the entire bus interface block 30. That is, the state machine 32 performs req based on the busy signal, ready signal, and gnt signal from the control bus 11 and the data transfer request from the device control block 31.
A signal, a cycle signal, and a SIG1 signal are generated. r
The eq signal is supplied to the arbiter 20, and the cycle signal is supplied to the target and the arbiter 20 via the control bus 11. The SIG1 signal is supplied to the input / output control block 33. The operation of the state machine 32 will be described later in detail with reference to a timing chart.

The input-output control block 33, based on SIG1 signal from the state machine 32 sends a bus control block 34 ₁ to 34C _n to generate a signal for controlling the bus control block 34 ₁ ~34 _n.

Each of the bus control blocks 34 _{1 to} 34 _n includes:
It corresponds to each bit of the n-bit bus width constituting the common bus 10. Since the structure of the bus control block is the same, in the following description, only the bus control block 34 _1.

The bus control block 34 ₁ includes an address register 35, a transmission data FIFO 36, and a reception data FIFO 36.
An O37, a multiplexer 38 and a bus driver 39 are provided. The address register 35 stores an address supplied from the device control block 31. The address stored in the address register 35 is sent to the multiplexer 38. The transmission data FIFO 36 is
The transmission data supplied from the device control block 31 is sequentially stored. The transmission data stored in the transmission data FIFO 36 is sent to the multiplexer 38.

The multiplexer 38 controls the address register 35 according to the control signal from the input / output control block 33.
And transmission data from the transmission data FIFO 36 is selected and passed. The address and transmission data from the multiplexer 38 are supplied to a bus driver 39. The bus driver 39 outputs an address or transmission data from the multiplexer 38 to the bit 0 line of the common bus 10 in response to a control signal from the input / output control block 33. Also, the reception data FIFO 37
Stores data received from the bit 0 line of the common bus 10 sequentially. The reception data output from the reception data FIFO 37 is supplied to the device control block 31.

The device control block 31 sends a data transfer request to the state machine 32 of the bus interface block 30 when it becomes necessary to transmit data to the target and receive data from the target. As a result, the state machine 32 starts control for data transmission and reception. Further, the device control block 31 sends the target address and the transmission data to the bus control block 34 ₁ ~34 _n. The target address is stored in an address register 35 in each bus control block, and the transmission data is stored in a transmission data FIFO 36. Further, the device control block 31 receives reception data from the reception data FIFO 37 in each bus control block.

(1-3) Detailed description of target:
The detailed configuration of the target will be described with reference to the block diagram shown in FIG. This target is roughly composed of a bus interface block 40 and a device control block 41. The bus interface block 40 controls transmission and reception of signals between the target and the common bus 10. Also, the device control block 4
1 controls transmission and reception of signals between the target and the above-described external device.

The bus interface block 30 includes a latch 42A, a latch 42B, a latch 42C, a comparator 4
3, state machine 44, input / output control block 45, address decoder 46, and bus control blocks 47 ₁ to 4
7 _n .

The latch 42A responds to the cycle A signal
The latch 42B receives a signal from the
Are respectively set by the cycleE signal. The latches 42A, 42B, and 42C are cleared by a reset signal from the state machine 44 when data transmission / reception is completed, and maintain the original state when data transmission / reception is interrupted. These latches 42A, 42B and 42
The signal from C is supplied to the comparator 43.

The comparator 43 includes a signal from the latches 42A, 42B and 42C and an external cycle A signal, c
The CycleC signal is compared with the CycleE signal, and the comparison result is supplied to the state machine 44. That is,
The comparator 43 outputs the cycle cl latched by the latches 42A, 42B and 42C at the time of the previous access from the master.
e signal and cycl from the master accessing this time
Compare with the e signal. The state machine 44 determines, based on the signal from the comparator 43, whether the cycle that occurred after the deassertion of the busy signal was caused by the same master as the previous time.

The state machine 44 controls the entire bus interface block 40. That is, the state machine 44 outputs a signal representing the comparison result from the comparator 43,
Based on a decode signal from the address decoder 46 and a transmission data fetch completion signal from the device control block 41, a busy signal, a ready signal, a reset signal, a transmission data fetch request signal, and a SIG2 signal are generated.

The bu generated by this state machine 44
The sy signal is supplied to each master and arbiter 20 via the control bus 11. The ready signal is supplied to each master via the control bus 11. The reset signal is supplied to the latches 42A, 42B and 42C as described above. The transmission data fetch request signal is supplied to the device control block 41. Furthermore, SIG2
The signal is supplied to the input / output control block 45. The operation of the state machine 44 will be described later in detail with reference to a timing chart.

The input-output control block 45, based on SIG2 signals from the state machine 44, respectively to generate a signal for controlling the signals and address decoder 46 for controlling the bus control block 47 ₁ to 47 _n bus sent to the control block 47 ₁ to 47 _n and the address decoder 46.

The address decoder 46 controls the bus control block 4 according to a control signal from the input / output control block 45.
Decoding the received data from 7 ₁ to 47 _n. As a result of this decoding, if the received data is an address addressed to itself, a decode signal is generated and supplied to the state machine 44. The address decoder 46 supplies the received data from the bus control block 47 ₁ to 47 _n to the device control block 41.

Each of the bus control blocks 47 _{1 to} 47 _n includes:
It corresponds to each bit of the n-bit bus width constituting the common bus 10. Since the structure of the bus control block is the same, in the following description, only the bus control block 47 _1.

The bus control block 47 ₁ transmits the transmission data F
It comprises an IFO 48, a reception data FIFO 49 and a bus driver 50. The transmission data FIFO 36 is
The transmission data supplied from the device control block 31 is sequentially stored. The transmission data stored in the transmission data FIFO 36 is supplied to the bus driver 50.

The bus driver 50 responds to a control signal from the input / output control block 45 to transmit data
8 is transmitted to the bit 0 line of the common bus 10. The reception data FIFO 49 is stored in the common bus 10.
The received data from the bit 0 line is sequentially stored. The received data stored in the received data FIFO 49 is supplied to the address decoder 46.

Further, the device control block 41
Responds to the transmission data fetch request from the
Data is read from an external device (not shown). So
When the data reading is completed,
A data fetch completion signal is supplied to the state machine 44.
The read data is transferred to the bus control block 47. ₁
~ 47_nTo the transmission data FIFO 48. In addition,
The chair control block 41 includes a bus control block 47.₁~ 4
7_nFrom the address decoder 46 via the address decoder 46.
Sends the received data to an external device.

(1-4) Detailed Description of Arbiter: Next, the detailed configuration of the arbiter 20 will be described with reference to FIG. The arbiter 20 includes a priority determination block 51,
It comprises a falling edge detection block 52 and a GNT signal output latch block 53.

The falling detection block 52 has a cycle
The falling edge of each of the eA signal, cycleC signal and cycleE signal is detected, and
acycleANEG signal, cycleCNEG signal and c
Generate the cycleENEG signal. These generated c
acycleANEG signal, cycleCNEG signal and c
The cycleENEG signal is supplied to the priority determination block 51 and the GNT signal output latch block 53.

The priority order determination block 51 includes a master A
, A reqC signal from the master C, a reqE signal from the master E, a cycle ANEG signal from the falling edge detection block 52, a cycle
The CNEG signal, the cycle ENEG signal, and an external busy signal are input. When all of the cycle A signal, the cycle C signal, and the cycle E signal are at the L level, the priority order determination block 51 performs the reqA
The priority order of the signal, the reqC signal and the reqE signal is determined, and the pgntA signal, the pgntC signal and the pgntE signal representing the determination result are output. In this case, the pgnt signal corresponding to the high priority req signal is set to the H level.

Pg from the priority order determination block 51
The ntA, pgntC, and pgntE signals are G
The signal is supplied to the NT signal output latch block 53. Also,
The pgntA signal from the priority determination block 51,
The pgntC signal and the pgntE signal are the cycle ANEG signal and the cycle
The signal is returned to the L level by the eCNEG signal and the cycle ENEG signal.

The GNT signal output latch block 53 receives the pgntA signal from the priority determination block 51,
Latch the tC signal and the pgntE signal. Then, according to the state of the cycleANEG signal, cycleCNEG signal and cycleENEG signal from the falling detection block 52 and the state of the external busy signal, gnt
Output as A signal, gntC signal and gntE signal.

The operation of the arbiter 20 configured as described above will be described with reference to the timing chart shown in FIG. This timing chart shows an example in which the following operation is performed. That is, req
The signal A is asserted, but the target B returns a busy signal because of the busy, and the master A releases the common bus 10 without performing a transaction. Thereafter, when the reqC signal is asserted from the master C, the gnt
The C signal is also asserted, and master C initiates a transaction. However, since the busy signal from the target B of the master A is released during the transaction of the master C, the transaction of the master C is interrupted and the transaction of the master A is executed. Then, after the transaction of the master A is completed, the transaction of the master C is resumed.

The above operation will be described with reference to the timing chart of FIG. First, when the master A asserts the reqA signal as shown in FIG.
The priority determination block 51 within 0 determines that the reqA signal has the highest priority, and sets the pgntA signal to the H level as shown in FIG. This pgntA
Gnt signal output latch block 53 to which a signal is input
Sets the gntA signal to the H level as shown in FIG. The master A sets the cycleA signal to the H level by setting the gntA signal to the H level.

In this state, as shown in FIG. 5C, when the target B asserts the busy signal,
As shown in FIG. 5B, the master A sets the cycleA signal to L level. As a result, the falling edge detection block 52, as shown in FIG.
A pulse is generated in the ANEG signal and supplied to the priority determination block 51. As a result, the priority determination block 51 sets the pgntA signal to the L level as shown in FIG. However, the GNT signal output latch block 53 maintains the gntA signal at the H level as shown in FIG.

In the above state, when the master C asserts the reqC signal as shown in FIG. 5 (G), the priority order determination block 51 determines that the reqA signal has already been asserted, but the busy signal is at the H level. Therefore, the priority is determined. Then, it is determined that the reqC signal has the highest priority, and as shown in FIG.
Assert the signal. The GNT signal output latch block 53 to which the pgntC signal has been input sets the gntC signal to the H level as shown in FIG. Master C
Is obtained by setting the gntC signal to the H level,
The cycleC signal is set to the H level. Thereby, the master C starts a transaction.

In this state, when the target B deasserts the busy signal as shown in FIG. 5C, the master C becomes the cycle C as shown in FIG.
Set the signal to L level. As a result, the data transfer of the master C is interrupted. Further, the falling edge detection block 52, as shown in FIG.
A pulse is generated in the G signal to determine the priority order.
To supply. Thereby, the priority order determination block 51
Sets the pgntC signal to the L level as shown in FIG. 5 (J), so that the GNT signal output latch block 53
As shown in FIG. 5 (K), the gntC signal is changed to L level.

On the other hand, in the master A, the target B is busy.
By setting the signal to the L level, the cycleA signal is set to the H level as shown in FIG. 5B, and the data transfer to the target B interrupted earlier is restarted. When the data transfer is completed, the cycleA signal is set to the L level as shown in FIG. As a result, the falling edge detection block 52 performs the operation shown in FIG.
, A pulse is generated in the cycleANEG signal and supplied to the priority determination block 51. This causes the GNT signal output latch block 53 to operate as shown in FIG.
As shown in FIG.
Transaction ends.

On the other hand, when the gntA signal is set to the L level, the GNT signal output latch block 53 operates as shown in FIG.
As shown in (K), the gntC signal is set to the H level.
On the other hand, as shown in FIG.
The eC signal is set to the H level, and the previously interrupted data transfer is resumed. When the data transfer is completed, FIG.
As shown in (H), the cycleC signal is set to L level. Thus, the falling edge detection block 52
Generates a pulse in the cycleCNEG signal and supplies it to the priority determination block 51, as shown in FIG. Thereby, the GNT signal output latch block 53
Sets the gntC signal to the L level as shown in FIG. 5K, and the transaction of the master C ends.

(1-5) Detailed Description of Operation of Information Processing Apparatus Next, a detailed description will be given of the information processing apparatus according to the first embodiment configured using the master, the target, and the arbiter 20 configured as described above. The operation will be described with reference to a timing chart.

First, a read operation in the information processing apparatus will be described with reference to a timing chart shown in FIG. In this timing chart, the master A performs read access to the target B, but the target B
Since the wait is applied by the sy signal, the operation in the case where the master C performs the read access to the target D during the wait is shown.

[0070] First, when a data transfer request read in the master A occurs, the device control block 31 is configured to set the address of the target B to the bus control block 34 ₁ to 34C _n of the address register 35, a data transfer request signal Is supplied to the state machine 32. This allows
As shown in FIG. 6A, the state machine 32
The qA signal is sent to the arbiter 20. Arbiter 20
As already described with reference to FIG. 4 and FIG. 5, if it can respond to this reqA signal, it returns a gntA signal as shown in FIG. 6 (B).

When receiving the gntA signal, the state machine 32 of the master A, as shown in FIG.
It outputs the cleA signal to the control bus 11 and supplies the SIG1 signal to the input / output control block 33. Thus, the input / output control block 33 causes the multiplexer 38 to select the address register 35 and enables the bus driver 39. As a result, the address of the target B is transmitted to the common bus 10 as shown in FIG.

The bus control blocks 47 ₁ to 47 B of the target B
47 _n takes the address sent from the common bus 10 into the reception data FIFO 49 and
Send to 6. The address decoder 46 determines that the address is addressed to itself, and sends a decode signal indicating this to the state machine 44. When the state machine 44 determines that it is a read data transfer request, it sends a transmission data fetch request to the device control block 41 and asserts a busy signal as shown in FIG. The state machine 32 of the master A that has received the busy signal, as shown in FIG.
Deassert the A signal. In addition, the state machine 32
Supplies the SIG1 signal to the input / output control block 33, as shown in FIG.
9 is disabled. As a result, the common bus 10 can be used by another master.

In this state, when a read data transfer request occurs in master C, the same operation as that of master A described above is performed. That is, the state machine 32 of the master C sends the reqC signal to the arbiter 20, as shown in FIG. The arbiter 20 is ready to respond to the reqC signal, determines that the busy signal is at the H level, and has already sent the gntA signal, but as shown in FIG. I will send it back.

The state machine 32 of the master C that has received the gntC signal, as shown in FIG.
It outputs the cleC signal to the control bus 11 and supplies the SIG1 signal to the input / output control block 33. As a result, the same operation as described above is performed, and FIG.
As shown in (J), the address of the target D is sent to the common bus 10.

The address decoder 46 of the target D
Since the address sent from the common bus 10 is an address addressed to itself, a decode signal indicating this is sent to the state machine 44. The state machine 44 has a master C
When it is determined that the data transfer request is read and that the data to be transferred is already prepared by the transmission data fetch completion signal from the device control block 41, as shown in FIG. Assert the signal. At this time, the data to be transmitted has already been written in the transmission data FIFO 48 by the device control block 41. Furthermore, the state machine 44
The bus driver 50 is enabled by sending two signals to the input / output control block 45. As a result, FIG.
As shown in (M), the transmission data to the master C is transmitted to the common bus 10. Master C state machine 32
Are transmitted from the common bus 10 to the bus control blocks 34 ₁ to 34 3 under the condition that the ready signal is at the H level.
4 captures the data written in the received data FIFO37 of _n.

When the state machine 44 of the target B receives the transmission data fetch completion signal from the device control block 41 during the data transfer from the master C to the target D, as shown in FIG. Is deasserted and the ready signal is asserted as shown in FIG. In this state, the data to be transmitted has already been written in the transmission data FIFO 48 by the device control block 41. Furthermore,
The state machine 44 enables the bus driver 50 by sending the SIG2 signal to the input / output control block 45. As a result, the transmission data to the master A is transmitted to the common bus 10 as shown in FIG.

The state machine 32 of the master A has a bus
When the y signal is deasserted, the cycleA signal is set to the H level again as shown in FIG.
On the other hand, the data transfer between the master C and the target D, which has already been performed, is temporarily suspended. That is, since the busy signal is deasserted, the state machine 44 of the target D, as shown in FIG.
Set the signal to L level. In addition, the state machine 32 of the master C sets the cycleC signal to the L level as shown in FIG. Further, the arbiter 20 is configured as shown in FIG.
As shown in the figure, the gntC signal is set to the L level.

The master A has the ready signal H
Under the condition that the level is set to the level, the reception data FIFO from the common bus 10 to the bus control blocks 34 _{1 to} 34 _n
Data is loaded into 37. After that, the state machine 32 of the master A, as shown in FIG.
The signal is set to L level, and the state machine 4 of the target B is set.
4 sets the ready signal to L level, and the transaction of the master A to the target B ends.

On the other hand, when the cycle A signal is set to the L level, the cycle C signal from the master C is set to the H level again as shown in FIG.
The ready signal from the target D is also shown in FIG.
As shown in (K), the level is set to the H level again. Further, the arbiter 20 sets the gntC signal to the H level. As a result, the suspended data transfer from the target D to the master C is resumed. Thereafter, the state machine 32 of the master C sets the cycleC signal to the L level as shown in FIG.
Sets the ready signal to the L level as shown in FIG. 6 (K), and the arbiter 20 sets g as shown in FIG. 6 (I).
The ntC signal is set to the L level, and the transaction of the master C with respect to the target D ends.

Next, a write operation in the information processing apparatus will be described with reference to a timing chart shown in FIG. This timing chart shows an operation in the case where the master A makes a write access to the target B, but waits for the busy signal from the target B, so that the master C makes a write access to the target D during that time.

First, when a write data transfer request occurs in the master A, the device control block 31 sets the address of the target B in the address register 35 of the bus control blocks 34 _{1 to} 34 _n and sets a data transfer request signal. Is supplied to the state machine 32. This allows
The state machine 32, as shown in FIG.
The qA signal is sent to the arbiter 20. Arbiter 20
As described above with reference to FIG. 4 and FIG. 5, if the apparatus can respond to the reqA signal, it returns a gntA signal as shown in FIG. 7B.

The state machine 32 of the master A that has received the gntA signal, as shown in FIG.
It outputs the cleA signal to the control bus 11 and supplies the SIG1 signal to the input / output control block 33. Thus, the input / output control block 33 causes the multiplexer 38 to select the address register 35 and enables the bus driver 39. As a result, the address of the target B is transmitted to the common bus 10 as shown in FIG.

The bus control blocks 47 ₁ to 47 _{1 of the} target B
47 _n takes the address sent from the common bus 10 into the reception data FIFO 49 and
Send to 6. The address decoder 46 determines that the address is addressed to itself, and sends a decode signal indicating this to the state machine 44. The state machine 44 determines that it is a write data transfer request, but if it is not ready to receive data, it asserts a busy signal as shown in FIG. The state machine 32 of the master A that has received the busy signal is shown in FIG.
As shown in (E), the cycleA signal is deasserted. Further, the state machine 32 supplies the SIG1 signal to the input / output
As shown in (C), the bus driver 39 is disabled. As a result, the common bus 10 can be used by another master.

In this state, when a write data transfer request occurs in the master C, the same operation as that of the master A is performed. That is, the state machine 32 of the master C sends a reqC signal to the arbiter 20, as shown in FIG. The arbiter 20 is ready to respond to the reqC signal, and determines that the busy signal is at the H level, and has already transmitted the gntA signal, but as shown in FIG. I will send it back.

The state machine 32 of the master C that has received the gntC signal, as shown in FIG.
It outputs the cleC signal to the control bus 11 and supplies the SIG1 signal to the input / output control block 33. As a result, the same operation as described above is performed, and FIG.
As shown in (I), the address of the target D is sent to the common bus 10. At this time, the data to be transmitted is already transmitted data FIFO by the device control block 31.
36 is written.

The address decoder 46 of the target D
Since the address sent from the common bus 10 is an address addressed to itself, a decode signal indicating this is sent to the state machine 44. The state machine 44 has a master C
If it is determined that the data transfer request is a write, the ready signal is asserted, as shown in FIG. The state machine 32 of the master C is ready
Under the condition that the signal is at H level, SIG
By transmitting one signal to the input / output control block 33, the multiplexer 38 selects the transmission data FIFO 36 and enables the bus driver 39. Thereby, as shown in FIG. 7 (I), the transmission data to the target D is transmitted to the common bus 10. Target D
Fetches data written in the reception data FIFO 49 of the bus control blocks 47 _{1 to} 47 _n from the common bus 10.

During the data transfer from the master C to the target D, when the state machine 44 of the target B determines that it is ready to receive the data,
As shown in FIG. 7 (F), the busy signal is deasserted, and as shown in FIG. 7 (D), the ready signal is asserted.

The state machine 32 of the master A has a bus
When the y signal is deasserted, the cycleA signal is set to the H level again as shown in FIG.
On the other hand, the data transfer between the master C and the target D, which has already been performed, is temporarily suspended. That is, since the busy signal is deasserted, the state machine 44 of the target D, as shown in FIG.
Set the signal to L level. Also, the state machine 32 of the master C sets the cycleC signal to L level as shown in FIG. Further, the arbiter 20 is arranged as shown in FIG.
As shown in the figure, the gntC signal is set to the L level.

Then, the state machine 32 of the master A
Indicates that the SIG is in a state where the ready signal is at the H level.
By transmitting one signal to the input / output control block 33, the multiplexer 38 selects the transmission data FIFO 36 and enables the bus driver 39. As a result, as shown in FIG. 7C, the transmission data to the target B is transmitted to the common bus 10. Target B
Fetches data written in the reception data FIFO 49 of the bus control blocks 47 _{1 to} 47 _n from the common bus 10. After that, the state machine 32 of the master A
As shown in (E), the cycle A signal is set to L level, and the state machine 44 of the target B is ready.
The signal is set to the L level, and the transaction of the master A with respect to the target B ends.

On the other hand, as the cycle A signal is set to L level, the cycle C signal from the master C is set to H level again as shown in FIG.
Also, the ready signal from the target D is
As shown in (J), the level is set to the H level again. As a result, the suspended data transfer from the master C to the target D is resumed. Thereafter, as shown in FIG. 7K, the state machine 32 of the master C sets the cycleC signal to the L level, and sets the state machine 44 of the target D.
Sets the ready signal to the L level as shown in FIG. 7 (J), and the arbiter 20 sets g as shown in FIG. 7 (H).
The ntC signal is set to the L level, and the transaction of the master C with respect to the target D ends.

[Second Embodiment] (2-1) Schematic description of information processing apparatus: An information processing apparatus to which a bus control apparatus according to a second embodiment of the present invention is applied
In the data transfer between the master and the target, when the master interrupts the operation by receiving the busy signal from the target and releases the common bus, the master uses the common bus at that time after the busy signal is released. It is configured so that the master with the highest priority among the masters operating operates. The other points are the same as those of the information processing apparatus to which the bus control device according to the first embodiment shown in FIG. 1 is applied.

(2-2) Detailed description of the master: The configuration and operation of the master used in the second embodiment are the same as those of the master described in the first embodiment.

(2-3) Detailed Description of Target: The configuration and operation of the target used in the second embodiment are the same as those of the target described in the first embodiment.

(2-4) Detailed Description of Arbiter: The arbiter used in the second embodiment differs from the arbiter 20 used in the first embodiment in the function of the priority order determination block 51. That is, the priority determination block 51
As in the first embodiment, in addition to allowing the use of the common bus 10 by judging the priority of the req signals from a plurality of masters, when the busy signal is deasserted, the req It has a function of judging the priorities of signals and giving permission to use the common bus 10 to a master with a higher priority.

The operation of the arbiter 20 will be described below with reference to the timing chart shown in FIG. This timing chart shows an example in which the following operation is performed.

That is, although the reqA signal is asserted from the master A, the target B is busy because the target B is busy.
A signal is returned, and the master A releases the common bus 10 without performing a transaction. Then, from master C to reqC
When the signal is asserted, the gntC signal is also asserted, and the master C starts a transaction. However, since the busy signal of the target B of the master A was released during the transaction of the master C,
Is suspended, and the master A and the master C determine the priority. Then, it is determined that the priority of the master A is high, and the transaction of the master A is performed. Then, after the transaction of the master A is completed, the transaction of the master C is resumed.

The above operation will be described with reference to the timing chart of FIG. First, when the master A asserts the reqA signal as shown in FIG. 8A, the priority determination block 51 determines that the reqA signal has the highest priority, and as shown in FIG. 8D. Next, the pgntA signal is set to the H level. The pgntA signal from the priority determination block 51 is set to the L level after a predetermined time. Further, the gnt signal output latch block 53 to which the pgntA signal has been input is, as shown in FIG.
The tA signal is set to the H level. Master A uses this gntA
When the signal is set to the H level, the cycleA signal is set to the H level.

In this state, as shown in FIG. 8C, when the target B asserts the busy signal,
As shown in FIG. 8B, the master A sets the cycleA signal to L level. As a result, the falling edge detection block 52, as shown in FIG.
A pulse is generated in the ANEG signal and supplied to the GNT signal output latch block 53. As a result, the GNT signal output latch block 53, as shown in FIG.
The ntA signal is set to L level.

In the above state, when the master C asserts the reqC signal as shown in FIG. 8 (G), the priority order determination block 51 determines that the reqA signal has already been asserted, but the busy signal is at the H level. Therefore, the priority is determined. Then, it is determined that the reqC signal has the highest priority, and as shown in FIG.
Assert the signal. The GNT signal output latch block 53 to which the pgntC signal has been input sets the gntC signal to the H level as shown in FIG. Master C
Is obtained by setting the gntC signal to the H level,
The cycleC signal is set to the H level. Thereby, the master C starts a transaction.

In this state, as shown in FIG. 8C, when the target B deasserts the busy signal, the priority determination block 51 is input to the priority determination block 51 at that time. reqA signal and re
The priority determination with the qC signal is performed. As a result, when it is determined that the priority of the reqA signal is high, the pgntA signal is set to the H level as shown in FIG. Thus, G
The NT signal output latch block 53 sets the gntA signal to the H level as shown in FIG.
As shown in (K), the gntC signal is set to L level.

On the other hand, since the busy signal is set to L level, as shown in FIG.
The leA signal is set to the H level, and the master C sets the cycleC signal to the L level, as shown in FIG.

On the other hand, when the master C sets the cycleC signal to the L level as shown in FIG. 8H, the falling detection block 52 outputs a pulse to the cycleCNEG signal as shown in FIG. To generate GN
The signal is supplied to the T signal output latch block 53. As a result, the pgntC signal maintains the L level, and the data transfer of the master C is suspended.

When the master A completes the cycle,
The cycleA signal is set to L level. As a result, the falling detection block 52, as shown in FIG.
A pulse is generated in the cycleANEG signal and supplied to the priority determination block 51. As a result, the GNT signal output latch block 53, as shown in FIG.
The gntA signal is set to L level. Above, arbiter 20
A series of operations on the master A is terminated. At the end of the master A cycle, as described above, cycleANE
When the G signal is set to the H level, the priority determination block 51 sets the pgntC signal to the H level as shown in FIG. As a result, the GNT signal output latch block 53 sets the gntC signal to the H level. Thereby, master C executes the remaining cycles. When the cycle is completed, the master C sets the cycleC signal to L level. As a result, the falling detection block 52, as shown in FIG.
A pulse is generated for the G signal and supplied to the GNT signal output latch block 53. As a result, the GNT signal output latch block 53, as shown in FIG.
Set the signal to L level. Thus, a series of operations of the arbiter 20 on the master C is completed.

(2-5) Detailed Description of Operation of Information Processing Apparatus Next, a detailed description will be given of the information processing apparatus according to the second embodiment configured using the master, the target, and the arbiter 20 configured as described above. The operation will be described with reference to a timing chart. The operations of the master and the target are the same as those in the first embodiment, and a detailed description thereof will be omitted below.

First, a read operation in the information processing apparatus will be described with reference to a timing chart shown in FIG. This timing chart shows an operation in the case where the master A makes a read access to the target B, but waits for the busy signal from the target B, so that the master C makes a read access to the target D during that time.

First, when a read data transfer request occurs in the master A, the master A sends a reqA signal to the arbiter 20, as shown in FIG. As described above with reference to FIG. 8, if the arbiter 20 can respond to the reqA signal, it returns a gntA signal as shown in FIG. 9B. Master A that has received the gntA signal, as shown in FIG.
The CycleA signal is output to the control bus 11 and the address of the target B is sent to the common bus 10 as shown in FIG.

When determining that the address sent from the common bus 10 is an address addressed to itself, the target B asserts the busy signal as shown in FIG. 9 (F). Master A, which has received this busy signal,
As shown in FIG. 9E, the cycle A signal is deasserted. As shown in FIG. 9B, the gntA signal is also low.
Become a level. Further, as shown in FIG. 9C, the output to the common bus 10 is disabled. As a result, the common bus 10 can be used by another master.

In this state, when a read data transfer request occurs in master C, the same operation as master A described above is performed. That is, the master C sends a reqC signal to the arbiter 20, as shown in FIG.
The arbiter 20 determines that it is in a state in which it can respond to the reqC signal, and as shown in FIG.
Send back signal.

Master C receiving this gntC signal
9 outputs the cycleC signal to the control bus 11 as shown in FIG. 9 (L) and sends the address of the target D to the common bus 10 as shown in FIG. 9 (J). In the target D, the address sent from the common bus 10 is an address addressed to itself, and therefore, the target D in FIG.
As shown in (1), the ready signal is asserted. Furthermore,
The target D is connected to the common bus 1 as shown in FIG.
The transmission data to the master C is transmitted to 0. Master C
Under the condition that the ready signal is at H level, data is taken in from the common bus 10.

When the preparation of the data is completed, the target B deasserts the busy signal as shown in FIG. 9F even during the data transfer from the master C to the target D. As a result, reqA
The priority of the signal and the priority of the reqC signal are determined. If the priority of the reqA signal is higher than the priority of the reqC signal, the operation shown by the solid line in FIG.
When the priority of the eqC signal is higher than the priority of the reqA signal, the operations shown by the broken lines in FIG. 9 are performed.

The operation when the priority of the reqA signal is higher than the priority of the reqC signal is the same as the operation of the first embodiment described with reference to FIG.

On the other hand, the operation when the priority of the reqC signal is higher than the priority of the reqA signal is as follows. That is, even if the busy signal is deasserted, the target D maintains the ready signal at the H level as shown in FIG. Further, the target D sends the next transmission data to the master C to the common bus 10 as shown in FIG.

As shown in FIG. 9L, the master C
The cycleC signal is maintained at the H level. On the other hand, as shown in FIG. 9D, the target B changes the ready signal to L
Keep at the level. Further, the master A maintains the cycle A signal at the L level as shown in FIG. Therefore, data transfer between the master A and the target B is not restarted.

Then, the master C has the ready signal at H level.
The data is taken in from the common bus 10 under the condition that the level is set to the level. When this loading is completed, Master C
Is completed, the master C sets the cycleC signal to L level and the target D sets the ready signal to L level as shown in FIG. 9 (L). Thus, the transaction of the master C with respect to the target D ends.

On the other hand, since the cycleC signal is set to L level, the cycleA signal from the master A is set to H level again as shown in FIG.
The ready signal from the target B is also shown in FIG.
As shown in (D), the level is set to H level. This allows
The suspended data transfer from the target B to the master A is resumed. When this data transfer is completed, the master A changes the cycleA signal to L as shown in FIG.
Level, and the target B sets the ready signal to L level. Thus, the transaction of the master A with respect to the target B ends.

Next, a write operation in the information processing apparatus will be described with reference to a timing chart shown in FIG. This timing chart shows an operation in the case where the master A makes a write access to the target B, but waits for the busy signal from the target B, so that the master C makes a write access to the target D during that time.

First, when a write data transfer request occurs in the master A, the master A sends a reqA signal to the arbiter 20, as shown in FIG. If the arbiter 20 can respond to the reqA signal as described above with reference to FIG.
A gntA signal as shown in FIG. The master A that has received the gntA signal outputs the cycleA signal to the control bus 11 as shown in FIG. 10E, and also transfers the address of the target B to the common bus 10 as shown in FIG. Send out.

The target B determines that the address sent from the common bus 10 is an address addressed to itself, but when the target B is not ready to receive data,
As shown in FIG. 10F, the busy signal is asserted. Master A, which has received the busy signal,
As shown in (E), the cycleA signal is deasserted. As shown in FIG. 10B, the gntA signal also becomes L level. The master A disables the output to the common bus 10. As a result, the common bus 10 can be used by another master.

In this state, when a write data transfer request occurs in the master C, the same operation as that of the master A is performed. That is, the master C is as shown in FIG.
The reqC signal is sent to the arbiter 20 as shown in FIG. The arbiter 20 determines that it is in a state in which it can respond to this reqC signal, and as shown in FIG.
Return the ntC signal.

Master C receiving this gntC signal
Outputs the cycleC signal to the control bus 11 as shown in FIG. 10 (K) and sends the address of the target D to the common bus 10 as shown in FIG. 10 (I). In the target D, since the address sent from the common bus 10 is the address addressed to itself,
As shown in (J), the ready signal is asserted.
The master C sends the transmission data to the target D to the common bus 10 under the condition that the ready signal is at the H level, as shown in FIG. Thus, the target D takes in data from the common bus 10.

When the target B determines that it is ready to receive data, it deasserts the busy signal as shown in FIG. 10F even during the data transfer from the master C to the target D. I do. Thus, the arbiter 20 determines the priority of the reqA signal and the priority of the reqC signal. Then, the priority of the reqA signal is r
When the priority of the eqC signal is higher than that of the eqC signal, the operation shown by the solid line in FIG.
When the priority is higher than the signal priority, the operation shown by the broken line in FIG. 10 is performed.

The operation when the priority of the reqA signal is higher than the priority of the reqC signal is the same as the operation of the first embodiment described with reference to FIG.

The operation when the priority of the reqC signal is higher than the priority of the reqA signal is as follows. That is, even if the busy signal is deasserted, the target D sets the ready signal to H as shown in FIG.
Keep at the level.

As shown in FIG. 10K, the master C
The cycleC signal is maintained at the H level. On the other hand, the target B maintains the ready signal at the L level as shown in FIG. The master A is shown in FIG.
As shown in (E), the cycleC signal is maintained at the L level. Therefore, data transfer between the master A and the target B is not restarted.

Then, the master C has the ready signal at H level.
While the level is maintained, the next transmission data to the target D is transmitted to the common bus 10 as shown in FIG. The target D takes in data from the common bus 10. When the fetching is completed and the cycle of the master C ends, the master C sets the cycleC signal to the L level and sets the target D as shown in FIG.
Sets the ready signal to L level. Thus, the transaction of the master C with respect to the target D ends.

On the other hand, when the cycleC signal is set to L level, the cycleA signal from the master A is set to H level again as shown in FIG. The ready signal from the target B is also shown in FIG.
As shown in FIG. 0 (D), it is set to the H level. As a result, the temporarily suspended data transfer from the master A to the target B is resumed. When this data transfer is completed, the master A sets the cycleC signal to the L level and the target B sets the ready signal to the L level as shown in FIG. Thereby, the target B of the master A
The transaction for ends.

[0127]

As described in detail above, according to the present invention,
A retry process can be performed in a short time, and a wasteful retry transaction process can be prevented from being performed, and an inexpensive bus control device and bus control method can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an information processing device to which a bus control device according to Embodiments 1 and 2 of the present invention is applied.

FIG. 2 is a block diagram showing a detailed configuration of a master in FIG.

FIG. 3 is a block diagram illustrating a detailed configuration of a target in FIG. 1;

FIG. 4 is a block diagram showing a detailed configuration of an arbiter applied to the bus control devices according to the first and second embodiments of the present invention.

FIG. 5 is a timing chart for explaining an operation of the arbiter applied to the bus control device according to the first embodiment of the present invention.

FIG. 6 is a timing chart for explaining a read operation in the information processing device to which the bus control device according to the first embodiment of the present invention is applied;

FIG. 7 is a timing chart for explaining a write operation in the information processing device to which the bus control device according to the first embodiment of the present invention is applied;

FIG. 8 is a timing chart illustrating an operation of an arbiter applied to the bus control device according to the second embodiment of the present invention.

FIG. 9 is a timing chart for explaining a read operation in an information processing device to which the bus control device according to the second embodiment of the present invention is applied;

FIG. 10 is a timing chart for explaining a write operation in an information processing device to which the bus control device according to the second embodiment of the present invention is applied;

FIG. 11 is a block diagram showing a configuration of an information processing apparatus employing a conventional non-split system.

FIG. 12 is a timing chart for explaining the operation of the information processing apparatus shown in FIG. 11;

FIG. 13 is a block diagram showing a configuration of an information processing apparatus employing a conventional split system.

FIG. 14 is a timing chart for explaining the operation of the information processing apparatus shown in FIG.

[Explanation of symbols]

Reference Signs List 10 common bus 20 arbiter 30, 40 bus interface block 31, 41 device control block 32, 44 state machine 33, 45 input / output control block 34 _{1 to} 34 _n , 47 _{1 to} 47 _n bus control block 35 address register 36, 48 transmission Data FIFO 37, 49 Received data FIFO 38 Multiplexer 39, 50 Bus driver 42A to 42C Latch 43 Comparator 46 Address decoder 51 Priority determination block 52 Falling edge detection block A, C, E Master B, D Target

Claims (11)

[Claims] 1. A master device, comprising: a common bus for performing data transfer between a master device and a target device; and a busy signal line connecting the master device and the target device. A controller for asserting a busy signal to be sent to the busy signal line when the request for data transfer from the device cannot be immediately responded to.The master device responds to the assertion of the busy signal from the busy signal line Interrupting the data transfer with the target device to release the common bus, and restarting the data transfer from the interrupted point in response to the deactivation of the busy signal from the busy signal line A bus control device including a control unit for causing the control unit to perform the control. 2. The control unit of the master device sends an address of the target device to the common bus when the right to use the common bus is acquired, requests data transfer, and responds to the request with the busy condition. In response to the assertion of the busy signal from the signal line, interrupting the data transfer with the target device to release the common bus, and deactivating the busy signal from the busy signal line. 2. The bus control device according to claim 1, wherein transmission and reception of data are started in response to the command. 3. The control unit of the target device latches a signal indicating the master when the data transfer with the master device is interrupted, and resumes the latched signal and the current access when resuming the data transfer. A cycle that occurs after deasserting the busy signal based on the comparison result of the same master that has occurred since the previous master. The bus control device according to claim 1, which determines whether or not the bus control is performed. 4. The first and second master devices and the first and second master devices.
A common bus for performing data transfer with a target device; a busy signal line connecting the first and second master devices to the first and second target devices; Includes a control unit that asserts a busy signal to be sent to the busy signal line when the request for data transfer from the first master device cannot be immediately responded. The first master device includes a busy signal from the busy signal line. Interrupts the first data transfer with the first target device in response to the assertion of the first target device to release the common bus, and responds to the deactivation of the busy signal from the busy signal line. A control unit for resuming the first data transfer from the point at which it was interrupted, wherein the second master device is configured to release the second target device when the common bus is released. And a controller for performing a second data transfer between the second data transfer and the second data transfer in response to a busy signal from the busy signal line being deasserted. 5. A control unit of the first master, further comprising: a priority determination unit that determines a priority between the first data transfer and the second data transfer, wherein the control unit of the first master receives a busy signal from the busy signal line. When deasserted, the first data transfer and the second data transfer are performed based on the determination result of the priority determination unit.
The bus control device according to claim 4, wherein any one of data transfer is performed. 6. The control unit of the first master device sends an address of the first target device to the common bus when the right to use the common bus is acquired, requests data transfer, and responds to the request. In response to the assertion of the busy signal from the busy signal line, data transfer with the first target device is interrupted to release the common bus, and the busy signal from the busy signal line is released. 6. The bus control device according to claim 4, wherein transmission and reception of data are started in response to the deassertion of the bus control. 7. A bus control method for performing data transfer between a master device and a target device using a common bus, wherein (A1) the target device responds to a data transfer request from the master device. When the busy signal is not asserted, (B1) the master device interrupts data transfer with the target device in response to the busy signal being asserted to release the common bus, and (C1) A) the bus control method, wherein the master device resumes the data transfer from the interrupted point in response to the deassertion of the busy signal. 8. The method according to claim 8, further comprising the step of: (D1) sending an address of the target device to the common bus to request data transfer when the right to use the common bus is acquired. In response to the busy signal being asserted in response to the request of the step (D1), the data transfer between the master device and the target device is interrupted to release the common bus, and the step (C1) 8.) The bus control method according to claim 7, wherein in the step (b), data transmission and reception are started in response to the deassertion of the busy signal. 9. The first and second master devices and the first and second master devices.
A bus control method for performing data transfer with a target device using a common bus, wherein (A2) the first target device is busy when it cannot immediately respond to a data transfer request from the first master device Assert the signal, (B
2) in response to the busy signal being asserted, the first master device interrupts the first data transfer with the first target device to release the common bus;
2) The first master device restarts the first data transfer from the point at which the first data transfer was interrupted in response to the deassertion of the busy signal, and (D2) the second master device:
Performing a second data transfer with the second target device when the common bus is released; and (E2) the second master device responds to the de-assertion of the busy signal. 2. A bus control method for interrupting data transfer. 10. The method according to claim 10, further comprising: determining a priority between the first data transfer and the second data transfer. In the step (C2), when the busy signal is deasserted, The bus control method according to claim 9, wherein one of the first data transfer and the second data transfer is performed based on a result of the determination in step (F2). 11. A step (G2) of sending an address of the first target device to the common bus and requesting a data transfer when the right to use the common bus is acquired, and the step (B2). In response to the assertion of the busy signal in response to the request of the step (G2), the first data transfer is interrupted to release the common bus. In the step (C2), the busy signal 11. The bus control method according to claim 9, wherein transmission and reception of data are started in response to deassertion of data.