JPH06326680A - Path monitoring bit extracting device - Google Patents

Abstract

PURPOSE:To extract the monitoring bits of respective paths without using a memory with a large storage capacity such as a frame aligner or the like. CONSTITUTION:The multiplexing position of the path monitoring bit and the starting position of an intra-frame block within a data transmission frame are detected by a pointer interpretation part 8. The write address of a memory 1 is generated while successively being changed from an initial value in address generation parts 2, 4-1-4-3 and 6 in response to the detection of the block starting position, the write enable of the memory 1 is performed in response to the position detection timing of the path monitoring bit and the path monitoring bit is selectively written in the memory 1. Read is performed by read addresses generated in response to frame pulses for the read by a read address generation part 7. The number of the path monitoring bits is sufficient for a memory capacity.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a path monitoring bit extracting device, and more particularly, it divides an information transmission frame into a plurality of blocks and assigns time slots in each block to data of a plurality of paths, each containing a path monitoring bit. The present invention relates to a path monitoring bit extraction device in a transmission communication system for time-division multiplexing and transmission.

[0002]

2. Description of the Related Art This type of path monitoring bit extraction device is
Known as a path alarm termination device. This pass alarm termination will be described with reference to FIGS. 11 (A) and 11 (B). NNI (NETWORK N) by CCITT recommendation
ODE INTERFACE) Hierarchy
As shown in FIG. 11A, in the frame of the multiplexed signal STM1, the multiplexing unit VC3 path (VIRTUAL CO
Three pieces of each information of (NTAINER 3 PATH) are multiplexed and shown as VC3 × 3.

Each multiplexing unit VC3 path includes, in addition to data to be transmitted, a path monitoring bit for monitoring the path, which is various alarm information detected in the section of the path.

The frame format of FIG. 11 (A) is shown in a time chart of FIG. 11 (B). The information transmission frame is divided into a plurality of blocks, and each of the blocks 1 to 3 is further divided into a plurality of time slots. The data of the first pass is 1-C, 1-A, 1
-B, data 1C in the first time slot of block 1, data 1-A in the first time slot of block 2, data 1-B in the first time slot of block 3, respectively. It is superimposed. Similarly, the respective data of the second and third paths are also divided and superimposed, and the data of the three paths are time-division multiplexed.

The SOH is a section overhead, and the pointer indicates the position of the path monitoring bit of each path.

The path alarm terminating device is a device for detecting and extracting the path monitoring bits of each of these paths from the frame. FIG. 12 is a schematic block diagram of this path alarm termination device. By passing all the data of the information transmission frame 201 through the frame aligner 21, the frame phase of each path is aligned and then the path monitoring bit of each path is extracted.

FIG. 13 is an operation time chart of this path alarm terminating device. The input data 201 is input to the frame aligner 21 and sequentially written in the memory in the frame aligner 21 in synchronization with the write frame pulse 202. The output data 203 is read from the frame aligner 21 in a state where each path is aligned with the frame phase by the read frame pulse 204. This output data 203 is input to the path alarm termination circuit 22, where only the path monitoring bits are extracted and output as the path alarm output signal 205. In FIG. 13, the data 1-A for the first pass, the data 2-A for the second pass, and the data 3-A for the third pass.
The data 3-A of the path is shown as the path monitoring bit of each path.

[0008]

SUMMARY OF THE INVENTION In such a conventional example,
Although the path monitoring bit occupies a very small percentage of all data, the frame aligner needs a memory having a capacity to hold all the data in order to align the phases of the paths. There is.

An object of the present invention is to provide a path monitoring bit extraction device which can extract a path monitoring bit using a memory having a small capacity.

[0010]

A path supervisory bit extraction device according to the present invention divides an information transmission frame into a plurality of blocks, and time slots in this block are respectively converted into data of a plurality of paths each including a path supervisory bit. A device for extracting the path monitoring bit in a transmission communication system for allocating and time-division multiplexing and transmitting, comprising a readable / writable memory, a multiplexing position of the path monitoring bit in the information transmission frame, and start of the block. Detecting means for detecting the position, means for writing enable of the memory in response to detection timing of the multiplexing position of the path monitoring bit by the detecting means, and detection of the start position of the block by the detecting means. Write address generated while sequentially changing the write address of the memory from the initial value in response to And forming means, characterized in that in response to the frame pulse for reading including a read address generating means for generating being sequentially contain altered the read address of said memory from an initial value.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. The memory 1 is a writable and readable RAM, and writes the input data 101 to the write address WA (upper address 111, lower address 106) in response to the write enable signal WE (102).

The pointer interpreter 8 receives the input data 101 and the frame pulse 113 as input, and generates a path monitoring bit designating signal 102 indicating the multiplexing position of the path monitoring bit and a block designating signal 103 indicating the start position of the block. . The path monitor bit instruction signal 102 is the write enable signal WE of the memory 1.

The lower address generation unit 2 generates the lower address 106 of the write addresses of the memory 1 in response to the block instruction signal 103. The path supervisory bit instruction signal separation unit 3 uses the lower address 106 and the supervisory bit instruction signal 10
2 and 2 as input, path monitoring bit instruction signal 1 for each path
07-1 to 107-3 (a signal indicating the multiplexing position of each path monitoring bit of paths 1 to 3) are separated and output.

The upper address generators 4-1 to 4-3 are provided corresponding to the paths, and the state value is inverted (0 when the corresponding path monitoring bit instruction signals 107-1 to 107-3 are input).
or 1), and the state value (1/0) is derived as the write upper address 108-1 to 108-3. This state value is also inverted and controlled by slip control signals 110-1 to 110-3 of the phase comparators 5-1 to 5-3 described later.
These upper addresses 108-1 to 108-3 are multiplexed by the upper address multiplexer 6 and used as the write upper address 111 of the memory 1.

The read address generator 7 generates the read address RA (upper address 114, lower address 112) of the memory 1 in response to the read frame pulse 104, and also the phase comparators 5-1 to 5-3. A window signal 109 for address phase comparison is also generated.

The phase comparators 5-1 to 5-3 are provided for the paths and detect the phase difference between the read upper address 114 and the write upper addresses 108-1 to 108-3 corresponding to the paths. , The upper address relative phase difference of writing and reading is detected only while the window signal 109 is active. If this relative phase difference becomes substantially zero and the upper addresses for writing and reading overlap, the correct path monitoring bit cannot be read, so the write upper address is slip-controlled to make a constant relative phase difference. To Therefore, the slip control signals 110-1 to 110-1
110-3 is generated, and each upper address generation unit 4-1 to 4-1 is generated.
It is input to 4-3.

FIG. 2 is a time chart showing the operation of the block shown in FIG. 1. As in the example described with reference to FIGS. 11A, 11B and 13, three pieces of each information of the multiplexing unit VC3 path are multiplexed. In this case, the path monitoring bits of the paths 1 to 3 are represented by 1-A, 2-A, and 3-A.

Input data 101 and frame pulse 113
Is input to the pointer interpretation unit 8 to generate a path monitoring bit instruction signal 102 and a block instruction signal 103. FIG. 3 is a block diagram of the pointer interpretation unit 8.
The frame counter 81 responds to the frame pulse 113 from the initial value to the basic clock of the data 101 (not shown).
Is a counter for counting, and the decoder 82 decodes this count value to determine the pointer position (see FIG. 11A) and the block start position.

The block start position is the block designation signal 10
3 is output, and the pointer position is the pointer latch 83.
It is used as a latch instruction signal of. Pointer latch 8
The pointer in the input data 101 latched by 3 is decoded by the decoder 84, so that the path monitoring bit position of each path can be determined. This decoder 8
The output of No. 4 becomes the path monitoring bit instruction signal 102 and becomes the write enable signal WE of the memory 1.

The block instruction signal 103 is input to the lower address generation unit 2 and the lower address 10 for writing in the memory 1 is written.
6 is generated. FIG. 4 shows the configuration of the lower address generation unit 2, which responds to the block instruction signal 103 by "1",
It is a ternary counter that counts "2" and "3" in this order, and performs a count-up operation in synchronization with a basic clock (not shown) of input data. The lower addresses "1", "2" and "3" correspond to the paths 1, 2 and 3, respectively.

The path monitoring bit designating signal 102 and the lower address 106 are input to the path monitoring bit designating signal separating section 3 to generate upper bits 07-1 to 107-3. As shown in FIG. 5, the path supervisory bit instruction signal separation unit 3 has a lower address 106 of "1",
A "1" decoder 31, which detects "2" and "3" respectively,
It has a “2” decoder 32 and a “3” decoder 33. The outputs (low active) of these decoders 31 to 33 become one input of each of the OR gates 34 to 36, and the path monitoring bit designating signal 102 (low active) is applied to each of the other inputs. Therefore, OR gates 34-36
Is output to the path monitoring bit instruction signal 1 corresponding to each path
07-1 to 107-3 are obtained separately.

The path monitoring bit instruction signals 107-1 to 107-3 separated for each path are input to the corresponding upper address generation units 4-1 to 4-3 and the upper address 108-1 for each path. ~ 108-3 are generated. FIG. 6 is a diagram showing a specific example of the higher-order address generation unit 4-1 and is the same for the other higher-order address generation units 4-2 and 4-3. Basically, the D-type flip-flop 41 is a toggle-type flip-flop configuration in which the state value (1 or 0) is inverted every time the path monitoring bit instruction signal 107-1 is input, and its Q output is the upper address 108.
It becomes -1. A switch 42 is provided to perform slip control by the slip control signal 110-1.
The state value of the flip-flop 41 can be inverted by switching the switch 42 with the slip control signal 110-1.

Upper address 108-1 for each path
Up to 108-3 are multiplexed by the higher-order address multiplexing unit 6. The multiplexer 6 is a 3: 1 selector 61 as shown in FIG.
The lower address 106 is "1",
Corresponding to the contents of "2" and "3", the upper address 108-1 of path 1, the upper address 108-2 of path 2, and the upper address 108-3 of path 3 are selected respectively to select the memory 1
Of the write upper address 111.

FIG. 8 is a block diagram of the read address generator 7, and FIG. 9 shows an operation time chart thereof. The read frame pulse 104 is input to the frame counter 71. The frame counter 71 counts from an initial value 0 to n in response to the frame pulse 104, and counts a basic clock (not shown) on the read side. Of this count output 115, "1"-
Only "3" is output via the gate 73 and becomes the read lower address 112.

The read frame pulse 104 is input to the D type flip-flop 72, and the frame pulse 10 is input.
It is a toggle-type flip-flop whose state value (0 or 1) is inverted every four inputs. The Q output becomes the read upper address 114 and is input to the decoder 74. The lower address of this decoder 74 is "1",
When "2" and "3" and the upper address is "0", the decode output (low active) 109 is output, and this decode output becomes the window signal 109 for phase comparison.

This window signal 109 is supplied to the phase comparator 5
-1 to 5-3, the write upper address 108-1 to -1 during the active period of the window signal 109.
The relative phase difference between 08-3 and the read upper address 114 is detected. If this relative phase difference becomes substantially zero and coincides, writing and reading are simultaneously performed in the same address area in the memory 1, which causes an error, so slip control of the upper address is performed. Be seen.

FIGS. 10A and 10B are time charts for explaining this slip control. First, FIG. 10 (A)
Is a time chart showing the relationship of addresses when writing and reading are not performed simultaneously in the same address area. In this case, since both upper addresses for writing and reading have a constant phase difference, there is no problem because the address area in the memory 1 is different between writing and reading.

On the other hand, as shown in FIG. 10 (B), if the upper addresses for writing and reading are the same, it causes an error. To detect slip control signals 110-1 to 110-
3 is generated. In response to this slip control signal, the switches 42 shown in FIG. 6 are switched in the upper address generation units 4-1 to 4-3, the state value of the flip-flop 41 is inverted, and slip control becomes possible. Of.

In the phase comparators 5-1 to 5-3, the upper addresses of writing and reading are compared while the window signal 109 is active, but reading is performed during the active period of the window signal 109. Since the upper address 114 is "0" (see FIG. 9), it is determined whether the write upper addresses 108-1 to 108-3 are "0" or "1" during the active period of the window signal 109. A circuit configuration for detection is also good.

Although the number of multiplexing unit VC3 paths is three in the above embodiment, it is clear that the number may be m (m ≧ 4), and in this case, each lower address for writing and reading is 1. ~ M.

[0032]

As described above, according to the present invention, only the path monitor bit is selectively written and read directly in the memory without passing through the frame aligner, so that the capacity is extremely small. There is an effect that the path monitoring bit can be extracted using the memory.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a time chart showing the operation of the blocks of FIG.

FIG. 3 is a diagram showing a configuration of a pointer interpretation unit 8 in FIG.

FIG. 4 is a diagram showing a configuration of a lower address generation unit 2 of FIG.

5 is a diagram showing a configuration of a path monitoring bit designating signal separation unit 3 of FIG.

6 is a diagram showing a configuration of a higher-order address generation unit 4-1 of FIG.

7 is a diagram showing a configuration of a higher-order address multiplexing unit 6 in FIG.

8 is a diagram showing a configuration of a read address generation unit 7 in FIG.

FIG. 9 is a time chart showing the operation of the read address generation unit 7.

FIG. 10 is a time chart illustrating slip control of upper address generation units 4-1 to 4-3.

FIG. 11 is a diagram showing an information transmission frame format according to NNI hierarchy according to CCITT recommendation.

FIG. 12 is a block diagram of a conventional path alarm termination device.

FIG. 13 is a time chart showing the operation of the blocks of FIG.

[Explanation of symbols]

 1 Memory 2 Lower Address Generator 3 Path Monitoring Bit Indication Signal Separator 4-1 to 4-3 Upper Address Generator 5-1 to 5-3 Phase Comparator 6 Upper Address Multiplexer 7 Read Address Generator 8 Pointer Interpreter

Claims (2)

[Claims] 1. A transmission communication system in which an information transmission frame is divided into a plurality of blocks, time slots in the blocks are respectively assigned to data of a plurality of paths each including a path monitoring bit, and time-division multiplexed transmission is performed. A device for extracting a path monitoring bit, comprising: a readable / writable memory; a detecting means for detecting a multiplexing position of the path monitoring bit and a start position of the block in the information transmission frame; The means for enabling the writing of the memory in response to the detection timing of the multiplexing position of the path monitoring bit, and the writing address of the memory in response to the detection of the start position of the block by the detecting means, The write address generating means which is generated while being sequentially changed, and the above-mentioned in response to the frame pulse for reading Path monitoring bit extraction device which comprises a read address generating means for generating being brought sequentially changing the read address of the memory from an initial value. 2. The path monitor according to claim 1, further comprising phase control means for detecting a relative position difference between the read address and the write address and controlling the relative position difference to be a predetermined value. Bit extractor.