JPH06326329A - Static induction transistor - Google Patents

Abstract

PURPOSE:To form a mesa type static induction transistor(SIT) in such a way that a P-N junction section can be completely coated even after a deep mesa groove is formed so as to excellently stabilize the surface of the transistor by constituting the peripheral section of the mesa groove in a three-layer structure composed of source regions, gate regions, and drain regions in the laminating direction. CONSTITUTION:The transistor has a buried gate structure composed of a source region 4 and drain region 2 which are respectively composed of semiconductor layers of one conductivity and a gate region 3 which has the opposite conductivity and put between the regions 4 and 2 and the periphery of an element is separated by a mesa groove B proved in the laminating direction of the layers 2-4. In such mesa type static induction transistor, the peripheral section of the groove B is constituted in a three-layer structure composed of source regions 4' and 4'', gate areas 3' and 3'', and drain regions 2 and 2'. Therefore, a highly reliable high-withstand voltage mesa type SIT having high surface stability can be obtained, because the exposed part J of a P-N junction can be coated excellently with a passivation layer 6 composed of glass, etc.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention mainly relates to a buried gate type static induction transistor (StaticInduction) for power.
Transistor; hereinafter referred to as SIT), and particularly to the structure of the peripheral portion of the mesa groove for realizing a high breakdown voltage.

[0002]

2. Description of the Related Art FIG. 6 shows an overall cross-sectional schematic view of an example of a conventional mesa-type SIT, and FIG. 7 shows an enlarged view in the vicinity of a mesa groove B'encircled by a broken line circle. Further, FIG. 8 is a view showing a state in which the surface coating resin is spin-coated and cured or glass fine powder is electrodeposited on the mesa groove portion B ′ in the state of FIG. 7.

In the mesa type SIT shown in FIG. 6, an N ^- drain layer 2 is formed on an N ⁺ drain ohmic layer 1, and a P ⁺ gate layer 3 and a P ⁺ gate electrode layer 3'are further formed thereon. Further, the N source layer 4 is formed on the P ⁺ gate layer.
And the N ⁺ source ohmic layer 5 is formed on the N source layer 4. Also, as shown in FIG.
^A mesa groove portion B'from the ⁺ gate electrode layer 3'to the N ⁺ drain ohmic layer 1 is formed, and the bottom portion and the edge portion of the mesa groove portion B'are, as shown in FIG. 8, a passivation layer 7 made of resin or glass. , 7 ', 7 ".

[0004]

Conventionally, in the mesa type SIT, the thickness of the drain N ⁻ layer 2 must be increased so as to increase the breakdown voltage. Therefore, the mesa groove B ′ for element isolation is also proportional to the thickness. I needed to deepen it. When such a deep mesa groove B ′ is formed, backfilling of the mesa groove B ′ with an organic substance or glass for surface stabilization (passivation) of the element causes the mesa groove B ′ to be deep, so that the mesa groove B ′ is deep. It is difficult to completely cover the exposed PN junction J between the gate and drain, and discharge occurs when a voltage is applied, resulting in a short circuit between the gate and drain.

Therefore, the technical problem of the present invention is to eliminate such drawbacks of the conventional structure and to completely cover the PN junction even after the formation of the deep mesa groove, and to provide the SIT excellent in surface stabilization. To do.

[0006]

A static induction transistor (SIT) according to the present invention comprises a source region and a drain region each formed of a semiconductor layer of one conductivity type, and a gate region of an opposite conductivity type sandwiched by the source and drain regions. In a mesa-type static induction transistor having a buried gate type structure provided with the periphery of the element separated by a mesa groove provided in the stacking direction of the semiconductor layers, The structure is characterized by having a three-layer structure including a source region, a gate region, and a drain region.

[0007]

In the present invention, since the peripheral portion of the mesa groove has three layers, the P layer of the PN junction between the gate and the drain is located at a position much deeper than the top of the mesa groove.
The mesa groove can be backfilled well with organic materials for passivation, glass, etc., and S with excellent surface stabilization.
IT will be obtained.

[0008]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a sectional view showing the structure of an SIT according to an embodiment of the present invention, and FIG. 2 is an enlarged view of the vicinity of the mesa groove B of the SIT of FIG. 1, showing a portion excluding the passivation layer. Further, FIG. 3 is an enlarged view of the vicinity of the mesa groove B surrounded by a broken line circle in FIG. 1 to 3, the PN junction J between the gate and the drain exposed on the side wall of the mesa groove B is located relatively inside the mesa groove B. This is because the N source layer 4'by epitaxial growth remains on the P ⁺ gate electrode layer 3 '. PN junction J of mesa groove B
Similarly, the opposite wall of the side wall having the same has a shape in which the P ⁺ gate electrode layer 3 ″ and the N source layer 4 ″ are left. Normally, the N source layers 4 ', 4''are formed with a thickness of about 15 to 20 .mu.m, so that the position of the PN junction J should be formed at a depth of about 18 to 23 .mu.m from the top of the mesa groove B. become. Inside the mesa groove B shown in FIG. 2, a polyimide-based surface coating resin is spin-coated and cured as shown in FIG. 3, or glass fine powder for surface sealing is selectively applied by, for example, electrophoresis. The PN junction J exposed on the side wall portion in the groove is covered with the passivation layer 6 after being formed and baked and cured. In this way, the PN junction portion J, which influences the gate / drain breakdown voltage of the SIT element, is completely covered with the passivation layer 6, and excellent surface stabilization can be realized. It should be noted that reference numerals 6 ′ and 6 ″ indicate passivation materials remaining on the surface when the passivation layer 6 is formed.

FIGS. 4 and 5 show the SI shown in FIGS.
It is a figure which shows each process for manufacturing T in order. Figure 4
(A) is ^N - Onn a silicon wafer of ⁺ 2-layer structure N ^- layer 2 is specific resistance 100 .OMEGA.cm, a thickness of 100 [mu] m. The N ⁺ layer 1 has a specific resistance of 0.01 Ωcm and a thickness of 150.
μm. The entire surface of the wafer shown in FIG. 4A is thermally oxidized, and selective opening in a mesh or stripe shape is performed on the surface of the N ⁻ drain layer 2 by using a normal photolithography technique, and P type diffusion such as boron nitride is performed. FIG. 4B shows a state in which the P ⁺ gate 3 and the P ⁺ gate electrode 3'are selectively formed by diffusion by using the source.

FIG. 4C shows a state in which the N source layer 4 is epitaxially grown on the wafer surface in the state of FIG. 4B using SiCl ₄ as a growth source and H ₂ as a carrier gas at a temperature of 1150 ° C. Indicates. The formed N source layer 4 has a specific resistance of 5 to 10 Ωcm and a thickness of 15 to 20 μm.

In FIG. 5A, the wafer in the state of FIG. 4C is selectively opened by a normal photolithography technique, and the buried P ⁺ gate electrode layer 3'is dug up by selective etching to form a gate electrode. The state which formed the groove A is shown. As a silicon etching solution, a general etchant of hydrofluoric acid or nitric acid was used.

In FIG. 5B, selective opening is performed on the wafer surface in the state of FIG. 5A by the usual photolithography technique as before, and the same silicon etchant is used to form the mesa groove B for element isolation. The one formed by selective etching is shown. Due to the mesa groove B, the P ⁺ gate electrode layers 3 ', 3', N
The source layers 4 ', 4''and the N ^- drain layers 2, 2'are defined, and the depth of the mesa groove B is set to reach the N ⁺ drain ohmic layer 1 and is set to 140 μm in the embodiment of the present invention.

FIG. 5C shows a state in which the passivation layer 6 made of glass is attached and formed by the electrophoresis method in the state of FIG. 5B. The glass forming conditions were as follows: GP-190 material manufactured by Nippon Electric Glass Co., Ltd. was mixed with isopropyl alcohol, and platinum was used as an anode electrode, and an electric field of 100 V / cm was applied to deposit glass powder. Further, it was melted and baked at 870 ° C. for 10 minutes to form a passivation layer 6 made of glass, thus completing the basic structure of SIT.

Next, the effect of the SIT according to the embodiment of the present invention and the SIT according to the conventional example will be compared and described. From the comparison between FIGS. 6 to 8 and FIG. 2, the PN junction J is located much closer to the top of the mesa groove B ′ of the conventional example as compared with the case of the embodiment of the present invention, and 3 from the top surface. The depth is up to 4 μm. From the comparison of FIGS. 8 and 3, in the conventional case, the coating of the passivation layer 7 made of resin or glass at the PN junction J, which influences the breakdown voltage between the gate and the drain, is not so good as in the case of the embodiment of the present invention. Perfect.
The difference in the depth of the PN junction J from the top surface of the mesa groove appears as the difference in the coverage between the two.

The yield comparison of the breakdown voltage between the gate and the source between the embodiment of the present invention shown in FIGS. 1 to 5 and the conventional example shown in FIGS. It was 92% by the example and 42% by the conventional example. The dimensions of the SIT elements are both 14 mm square and the parameter is 1.
It was 20 pieces.

As described above, according to the embodiment of the present invention, a part of the source epitaxy layer 4 for burying the gate P ⁺ layer 3 is exposed at the end of the peripheral edge of the mesa groove B, so that it is exposed. An example is shown in which the PN junction portion J is formed at a position deeper than the top surface of the mesa groove B. However, this does not necessarily leave a part of the epitaxial layer and the thickness of, for example, a polyimide resin or a vapor-deposited metal film. It is also possible to use a film, and the covering property can be greatly improved only by taking a means to relatively increase the distance in the depth direction from the top of the mesa groove B.

Although the embodiments of the present invention propose the mesa type SIT, it is extremely easy to apply the gist of the present invention to any other semiconductor device formed by epitaxial growth. Is.

[0019]

As described above, according to the present invention, since the exposed PN junction can be coated very well, it is possible to provide a highly reliable high withstand voltage mesa SIT having extremely high surface stability. became.

[Brief description of drawings]

FIG. 1 is an overall sectional view showing a structure of an SIT according to an embodiment of the present invention.

FIG. 2 is an enlarged schematic cross-sectional view in the vicinity of the mesa groove surrounded by a broken line circle in FIG. 1, in which a passivation material is removed.

3 is an enlarged cross-sectional schematic view of the vicinity of a mesa groove surrounded by a broken line circle in FIG.

FIG. 4 is a cross-sectional view showing a process for manufacturing the SIT shown in FIGS. 1 to 3.

FIG. 5 is a cross-sectional view showing a process for manufacturing the SIT shown in FIGS. 1 to 3.

FIG. 6 is an overall sectional view showing the structure of a SIT according to a conventional example.

7 is an enlarged cross-sectional view of the vicinity of a mesa groove surrounded by a dashed circle of SIT in FIG.

8 is an enlarged cross-sectional view of the vicinity of a mesa groove surrounded by a broken line circle in FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 N ⁺ drain ohmic layer 2 N ⁻ drain layer 3 P ⁺ gate layer 3 ′, 3 ″ P ⁺ gate electrode layer 4 N source layer 4 ′, 4 ″ part of N source layer (dummy layer) 5 N ⁺ Source ohmic layer 6,7 Passivation layer A Gate electrode step B, B'Mesa groove J Gate-drain PN junction

Claims (1)

[Claims] 1. A buried gate type structure comprising a source region and a drain region each composed of a semiconductor layer of one conductivity type and a gate region of an opposite conductivity type sandwiched between the source and drain regions, wherein the periphery of the element is the semiconductor layer. In a mesa-type electrostatic induction transistor that is separated by a mesa groove provided in the stacking direction, the structure in the stacking direction at the peripheral edge of the mesa groove is a source region,
An electrostatic induction transistor having a three-layer structure including a gate region and a drain region.