JPH06326326A - Manufacture of nonvolatile semiconductor storage device - Google Patents

Abstract

PURPOSE:To obtain a nonvolatile memory cell which is made to be free from erroneous writing and reduced in level difference so as to reduce the fluctuation of erasing time and easily process electrode wiring by successively forming a first gate oxide film, floating gate, second gate oxide film, and control gate on a field oxide film formed in a flat state. CONSTITUTION:At the time of manufacturing a nonvolatile semiconductor storage device, a field oxide film 2 is formed on an Si substrate 1 by an oxidizing process and the surface of the film 2 is flattened after the substrate 1 is etched by chemical or dry etching. After flattening the surface of the film 2, a first gate oxide film 3, floating gate 4, second gate oxide film 6, and control gate 7 are successively formed on the film 2. For example, after forming the film 2 in a flat state by providing steps on the surface of the substrate 1, the floating gate 4 and an erasing gate 5, both of which are composed of polysilicon, are formed on the same surface of the film 2 so that the gates 4 and 5 can be counterposed to each other on both sides of the film 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure and a manufacturing method of a semiconductor non-volatile memory device, and more particularly to a flash E ² PROM (Flash Electrical Flash Erase) which has a floating gate, an erase gate and a control gate and can be erased in a batch. Erasable Prog
The present invention relates to a method for manufacturing a rammable read only memory).

[0002]

^2. Description of the Related Art A flash E ² PROM has its memory cell composed of a transistor having a three-layer structure gate of a control gate, a floating gate and an erase gate, and has a function of electrically erasing written information at all bits at the same time. It is a non-volatile memory provided with. FIG. 7 is a sectional view showing the structure of a memory cell of such a conventional flash E ² PROM.

A field oxide film 2 for separating adjacent memory cells is formed on the surface of a substrate 1. On this field oxide film 2, an erasure made of a first layer of polycrystalline silicon (polysilicon). The gate 5 is formed.

A field oxide film 2 is formed on the substrate 1.
The floating gate 4 made of polycrystalline silicon (polysilicon) of the second layer is sandwiched by the gate oxide film 3
Are formed. Further, a control gate made of a third layer of polycrystalline silicon (polysilicon) is formed on the floating gate 4 and the erase gate 5 via a gate oxide film 6.

In the memory cell having such a structure, when writing information, the erase gate 5 is grounded and the control gate 7 is used.
By applying a high voltage to the floating gate 4
Is performed by increasing the threshold voltage of the transistor. On the other hand, in erasing, a high voltage is applied to apply a high electric field to the insulating film to forcibly discharge the electrons injected into the floating gate 4 to the erasing gate 5 and lower the threshold voltage of the transistor. Done by

In FIG. 7, since a corner portion 16 is formed in a portion where the floating gate 4 and the erase gate 5 face each other, variations occur in the leak current, resulting in variations in the erase time.

[0007]

In the memory cell shown in FIG. 7, since the floating gate 4 and the erase gate 5 face each other with a step, the floating gate 4 and the erase gate 5 face each other. The variation in the leak current flowing through the corner portion 16 causes a large variation in the erase time, which makes it difficult to speed up the erase time.

Further, since the corner portion 16 has a large leak current, there is a problem that erroneous writing is likely to occur.

Further, since each gate has a three-layer structure, the step of the interlayer insulating film formed on the control gate 7 becomes large, making it difficult to process the electrode wiring and causing a defect such as disconnection of the electrode wiring. Was there.

In view of these problems, an object of the present invention is to provide a non-volatile memory cell which eliminates erroneous writing, has less variation in erasing time, and has less steps to facilitate processing of electrode wiring. is there.

[0011]

In order to achieve the above object, a method of manufacturing a semiconductor nonvolatile memory device according to the present invention is directed to a field oxidation method in which an element isolation region on a surface of a semiconductor substrate is pre-etched to form a step. A step of forming a flat film to form a first insulating film; a step of depositing polycrystalline silicon on the entire surface and performing patterning to form a floating gate and an erase gate so as to face each other; And a step of forming a second insulating film on the surface of the erase gate, and a step of depositing polycrystalline silicon on the entire surface to form a control gate.

A second invention is a step of forming a step in the element isolation region on the surface of the semiconductor substrate in advance by etching to stop the field oxide film before it becomes flat and forming a first insulating film, and an erase gate in the step. To form a planarization step, a step of forming a second insulating film on the surface of the floating gate and the erase gate, and a step of depositing polycrystalline silicon on the entire surface,
And a step of forming a control gate.

A third invention is a step of forming a field oxide film in a device isolation region on the surface of a semiconductor substrate to form a first insulating film, and etching the field oxide film to etch a portion where a floating gate and an erase gate are buried. , The step of forming a floating gate and an erase gate in the etching part, the step of forming a second insulating film on the surface of the floating gate and the erase gate, and depositing polycrystalline silicon on the entire surface to control it. And a step of forming a gate.

A fourth invention is a step of forming a field oxide film in an element isolation region on the surface of a semiconductor substrate to form a first insulating film, and depositing polycrystalline silicon on the entire surface and patterning to form a floating gate. A step of forming, a step of tapering the end of the floating gate facing the erase gate by etching, a step of forming a second insulating film on the surface of the floating gate, and an erase gate via the second insulating film. And a step of forming a third insulating film on the surface of the erase gate, and a step of depositing polycrystalline silicon on the entire surface to form a control gate.

[0015]

According to the first invention, the surfaces of the first gate oxide film and the field oxide film are flattened, and the floating gate and the erase gate formed on the surfaces are opposed to each other. According to the invention, the surfaces of the first gate oxide film, the field oxide film, and the erase gate are planarized, and the floating gate, the second gate oxide film, and the control gate formed on the surface are formed. The flatness on the substrate is excellent,
Breakage or short circuit of the metal wiring formed on these is less likely to occur, and it is possible to improve the manufacturing yield and reliability.

According to the third aspect of the invention, the floating gate and the erase gate are formed so as to be opposed to each other and embedded in the etching portion of the field oxide film, and the second gate oxide film and the control gate are further formed. Since the upper flatness is excellent, disconnection or short circuit of the metal wiring formed on them is not likely to occur, and it is possible to improve the manufacturing yield and reliability.

According to the fourth aspect of the invention, by tapering the end portion of the floating gate by etching, the facing area between the floating gate and the erase gate is increased through the second gate oxide film, and the tunnel current is increased. Therefore, the erase time can be shortened.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the method and apparatus for manufacturing a semiconductor device of the present invention will be described below with reference to FIGS.

1 to 4 are sectional views showing a structure in the width direction of a nonvolatile memory cell according to an embodiment of the present invention. The non-volatile memory cell shown in the figure is a flash E ² PROM memory cell, which has a floating gate 4, an erase gate 5 and a control gate 7, and performs writing and erasing in the same manner as the conventional one. is there.

In FIG. 1, a memory cell has a field oxide film 2 formed on a substrate 1, and a floating gate 4 and an erase gate 5 made of polysilicon are formed on the same plane on the field oxide film 2. The second gate oxide film 6 is formed so as to face each other.

A method of forming the field oxide film 2 on the same plane will be described with reference to FIGS. FIG. 5 shows a conventional process for forming the field oxide film 2. When the Si ₃ N ₄ mask 14 is placed on the substrate 1 and an oxidation process is performed, the oxide layer under the Si ₃ N ₄ mask 14 is thin (first gate oxide film 3), and the portion other than the mask becomes a thick field oxide film 2. . Therefore, a step is formed in the portion of the first gate oxide film 3. Therefore, as shown in FIG. 6, the step 15 is formed in advance by etching the portion other than the Si ₃ N ₄ mask 14. Next, when the oxidation is performed, the field oxide film 2 and the first gate oxide film 3 are the same. It will be formed on a plane.

Then, a control gate 7 made of polysilicon is formed on the floating gate 4 and the erase gate 5 via a second gate oxide film 6.

In such a structure, electrons are input and output to and from the floating gate 4 and the erase gate 5, and side surfaces of the floating gate 4 and the erase gate 5 on the same plane are opposed to each other via the second gate oxide film 6. Will be done only.

In FIG. 2, the field oxide film 2 and the first gate oxide film 3 are formed by oxidizing the substrate 1 in the same process as in FIG.
The oxidation process is completed at the time when the step 9 becomes equal to the film thickness of the erase gate 5 formed later. Next, when the erase gate 5 is formed on the step 9, the erase gate 5, the field oxide film 2 and the first gate oxide film 3 are formed on the same plane. Subsequently, the floating gate 4 is formed, and the control gate 7 made of polysilicon is formed on the floating gate 4 and the erase gate 5 via the second gate oxide film 6.

In FIG. 3, the field oxide film 2 and the first gate oxide film 3 are formed by performing the conventional substrate oxidation process described in FIG.
Then, the floating gate etching groove 10 and the erase gate etching groove 11 are formed in the field oxide film 2 by etching. Next, floating gate etching groove 1
0 and the erase gate etching groove 11 are formed with the floating gate 4 and the erase gate 5, and then the control gate 7 made of polysilicon is formed on the floating gate 4 and the erase gate 5 via the second gate oxide film 6. Is formed.

In FIG. 4, the field oxide film 2 and the first gate oxide film 3 are formed by performing the conventional substrate oxidation process described in FIG.
Then, the floating gate 4 made of polysilicon is formed. Next, an end surface facing the erase gate is etched to form a tapered etching surface 12, and the floating gate 4 is opposed to the adjacent floating gate 4 with a second gate oxide film 6 interposed therebetween. Thus, the erase gate 5 made of polysilicon is formed. Then, floating gate 4
A control gate 7 made of polysilicon is formed on the erase gate 5 via the second gate oxide film 6 and the third gate oxide film 13.
Is formed.

[0027]

According to the first and second aspects of the present invention, since the field oxide film and the first gate oxide film on the semiconductor substrate are formed on the same plane, the floating gate formed on the same plane is formed. Since the erase gates are formed so as to face each other via the insulating film, the leak current flowing from the floating gate to the erase gate at the facing portion can be reduced to stabilize the erase current flowing from the erase gate to the floating gate. You can Further, in the control gate formed on this, the floating gate and the erase gate do not overlap with each other, and the step of the control gate can be made gentle, so that the electrode wiring can be easily processed, and defects such as disconnection of the electrode wiring can be prevented. Can be prevented. According to the invention of claim 3, a groove for the floating gate and the erase gate is formed by etching the field oxide film, the floating gate and the erase gate are formed in the groove, and further, the control gate is formed. Since there is no step difference between the floating gate, the erase gate, and the control gate, it is possible to easily process the electrode wiring and prevent defects such as disconnection of the electrode wiring. According to the invention of claim 4, since the floating gate is formed by etching so as to be opposed to the erase gate, the facing area between the floating gate and the erase gate is increased, and the tunnel current is increased. The time can be shortened.

[Brief description of drawings]

FIG. 1 is a sectional view showing the structure of a flash E ² PROM according to an embodiment of the present invention.

FIG. 2 is a flash E ² PRO of the second embodiment of the present invention.
Sectional drawing which shows the structure of M.

FIG. 3 is a flash E ² PRO of the third embodiment of the present invention.
Sectional drawing which shows the structure of M.

FIG. 4 is a flash E ² PRO of the fourth embodiment of the present invention.
Sectional drawing which shows the structure of M.

FIG. 5 is a cross-sectional view illustrating a conventional field oxide film forming process.

FIG. 6 is a cross-sectional view illustrating a forming process for forming a field oxide film and a first gate oxide film on the same plane.

FIG. 7 is a sectional view showing the structure of a conventional flash E ² PROM.

[Strong description]

1 ... Semiconductor substrate, 2 ... Field oxide film, 3 ... First gate oxide film, 4 ... Floating gate, 5 ... Erase gate, 6 ... Second gate oxide film, 7 ... Control gate.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI technical display location G11C 16/04

Claims (4)

[Claims] 1. In a method for manufacturing a semiconductor nonvolatile memory device, before the formation of a field oxide film, chemical etching or dry etching is performed in advance to remove S.
The i substrate is etched, the surface of the field oxide film formed by the oxidation process is flattened, and the first gate oxide film, the floating gate, the second gate oxide film, and the control gate are laminated on the surface. Manufacturing method of semiconductor nonvolatile memory device. 2. A method for manufacturing a semiconductor non-volatile memory device, which comprises performing chemical etching or dry etching in advance to form S before forming a field oxide film.
The i substrate is etched and stopped before the surface of the field oxide film formed by the oxidation process becomes a flat surface, the erase gate is buried in the step and flattened, and then the first gate oxide film and the floating gate are formed. A method of manufacturing a semiconductor nonvolatile memory device, comprising laminating a gate, a second gate insulating film, and a control gate. 3. A method for manufacturing a semiconductor nonvolatile memory device, wherein a first gate oxide film and a field oxide film formed by an oxidation step are subjected to chemical etching or dry etching to etch a Si substrate to thereby obtain a floating gate and an erase gate. Is buried in the etching groove, and a second gate oxide film and a control gate are stacked on the etching groove to planarize the semiconductor non-volatile memory device. 4. A method of manufacturing a semiconductor nonvolatile memory device, wherein an end face of a floating gate formed on a first gate oxide film is tapered by chemical etching or dry etching, and then a second gate oxide film is formed. A method of manufacturing a semiconductor nonvolatile memory device, which comprises forming, followed by forming an erase gate and a control gate.