JPH06326320A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To highly integrate a high-performance MOSFET for power which has low ON-state resistance and its control circuits. CONSTITUTION:In an MOSFET for power, a trench is formed in a semiconductor layer 2 on a semiconductor substrate 1, and a gate oxide film 7 is formed in the inside thereof. A polysilicon of a gate electrode 8 is filled therein. On the other hand, its control circuit part is subjected to element isolation by the use of a trench type element isolation construcion 17, and the isolation areas are provided with control circuits such as a bipolar element, etc. Thanks to a trench gate, unit-area ON-state resistance will not be increased even when the cell density is increased. Furthermore the integration degree thereof can be improved with an aid of the trench construction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a composite semiconductor device in which a power MOS field effect transistor and a control circuit including a signal element for controlling the same are monolithically integrated and a method of manufacturing the same. .

[0002]

2. Description of the Related Art Conventionally, a power MOS type field effect transistor (hereinafter referred to as MOSFET) used for a power switch, a motor drive, a lamp drive and the like is monolithically integrated in a semiconductor substrate together with its control circuit to form a composite semiconductor device ( Hereinafter, referred to as a power IC). This conventional power IC will be described with reference to FIGS. The figure shows the cross-sectional structure. A silicon high impurity concentration N ⁺ semiconductor substrate is used as the semiconductor substrate 1, and a silicon N-type semiconductor layer 2 is formed thereon. A silicon P-type buried isolation layer 3 is formed in a predetermined region between the semiconductor substrate 1 and the N-type semiconductor layer 2. The N-type semiconductor layer 2 on the P-type buried separation layer 3
Is formed with a P-type isolation diffusion region 4 formed so as to reach the P-type buried isolation layer 3 from the surface of the N-type semiconductor layer 2, and is surrounded by the P-type buried isolation layer 3 and the P-type isolation diffusion region 4. The N-type semiconductor layer 2 constitutes an N-type semiconductor region 21,
Power MOSFET used for power switch etc.
A control circuit for T is formed.

N-type semiconductor layer 2 other than N-type semiconductor region 21
A P-type base region 5 of the MOSFET is formed in the surface region of, and an N ⁺ source region 6 is formed in the P-type base region 5. A gate electrode 8 made of polysilicon is formed on the N-type semiconductor layer 2 via a gate oxide film 7 so as to cover the N-type semiconductor layer 2, the P-type base region 5 and the N ⁺ source region 6. 8 is covered with an insulating film 9 such as a silicon oxide film. The control circuit of the N-type semiconductor region 21 includes, for example, a bipolar transistor. This bipolar transistor has a P-type base region 1 formed in a surface region of an N-type semiconductor region 21.
1. It includes an N ⁺ emitter region 121 formed inside the P-type base region 11 and a high impurity concentration N ⁺ collector region 12 formed outside the P-type base region 11. Power IC
The control circuit and the power MOSFET are repeatedly formed in plural.

In order to form a power IC having such a structure, first, impurities such as boron are diffused into the silicon semiconductor substrate 1 having a thickness of about 200 μm by, for example, ion implantation or the like to form a predetermined surface on the semiconductor substrate 1. A P-type impurity diffusion layer is formed in the region of, and an N-type semiconductor layer 2 having a thickness of about 10 μm is epitaxially grown thereon. The P-type impurity diffusion layer becomes the buried separation layer 3. Next, impurities such as boron are diffused from the surface of the N-type semiconductor layer 2 to form a P-type isolation diffusion region 4 reaching the P-type buried isolation layer from the surface of the N-type semiconductor layer and surrounded by this diffusion layer. The N-type semiconductor layer 2 is used as an N-type semiconductor region 21 in which a control circuit is formed. A P-type base region 11, an N ⁺ collector region 12 and an N ⁺ emitter region 121 of a bipolar transistor included in the control circuit are formed in this region, and a base electrode B, a collector electrode C and an emitter electrode connected to these are formed on these regions. E is formed using aluminum as a material. Next, in a region other than the N-type semiconductor region 21, a gate electrode 8 made of polysilicon having a predetermined pattern is formed via the gate oxide film 7. Then, using the polysilicon pattern of the gate electrode 8 as a mask, P-type impurities are added to the N-type semiconductor layer 2.
Next, an N-type impurity is ion-implanted to p-type base region 5
And the N ⁺ source region 6 are formed by self-alignment. Each region diffuses (that is, laterally diffuses) to below the gate electrode 8, and the gate length of the MOSFET cell formed by these regions is the lateral diffusion of the P-type base region 5 and the N ⁺ source region. Determined by the difference in length. Therefore, the cell characteristics are extremely uniform, effective for a power IC formed by connecting a large number of these cells in parallel, and widely used.

[0005]

However, a power MOS is used.
Since the channel of the FET cell is formed by the lateral diffusion of the P-type base region, there is a limit in reducing the cell array pitch, so that high integration is difficult. Further, as the cell array pitch is reduced, the resistance of the JFET portion (J) existing equivalently in the region sandwiched between the P-type base regions of the adjacent cells increases (see FIG. 14). Therefore, even if the array pitch is simply reduced and a large number of cells are integrated, the ON resistance per unit area does not always become the minimum, and the optimum cell pitch exists there. This optimum cell pitch is almost larger than the minimum processing size in manufacturing, and therefore the integration degree of the semiconductor device is not improved. Further, since the element isolation region for isolating the power MOSFET and its control circuit portion is formed with the P-type isolation diffusion region reaching the internal P-type buried isolation layer by diffusion from the surface of the N-type semiconductor layer. It is a design load considering the lateral expansion of the P-type isolation diffusion region. In particular, the higher the breakdown voltage system is, the thicker the N-type semiconductor region 21 in which the control circuit is formed is required. Therefore, the P-type isolation diffusion region needs to have a wide width, which makes it difficult to highly integrate the semiconductor device. The present invention has been made under such circumstances, and an object of the present invention is to provide a semiconductor device in which a high-performance power MOSFET having a low on-resistance and its control circuit can be highly integrated.

[0006]

According to the present invention, a power semiconductor element has a trench gate structure, and a control circuit portion of the power semiconductor element is separated from the power semiconductor element by a trench type element isolation structure. It is characterized by being. That is, the semiconductor device of the present invention is formed on a first conductivity type semiconductor substrate, a first conductivity type semiconductor layer formed on the first conductivity type semiconductor substrate, and the first conductivity type semiconductor layer, and is used for power. A first conductive type first region having a semiconductor element, a first conductive type second region having a control circuit element formed in the first conductive type semiconductor layer, and the first conductive type semiconductor layer. A second conductivity type base region of the power semiconductor element formed in a surface region of the first region and the power formed in the surface region of the first region and surrounded by the second conductivity type base region. A first conductive type source region of the semiconductor device for use, and the first conductive type source region formed in the first conductive type source region,
A gate trench that penetrates the second conductivity type base region from the main surface of the conductivity type semiconductor layer, a gate oxide film of the power semiconductor element formed on a sidewall of the gate trench, and the gate Between the gate electrode of the power semiconductor element formed in the trench and arranged on the gate oxide film, and in the second region or between the first conductive type semiconductor substrate and the first conductive type semiconductor layer. And a second conductivity type buried separation layer formed between the first region and the second region, the second conductivity type buried separation layer being formed at least from the main surface of the first conductivity type semiconductor layer. A trench for element isolation that reaches a layer, and the second conductive type buried isolation layer and the trench for element isolation define the second region of the first conductive type semiconductor layer to the other of the first conductive type semiconductor layer. Separation from the area A first said Rukoto.

Further, the first conductivity type semiconductor substrate and the first
A first conductive type semiconductor layer formed on a conductive type semiconductor substrate; a first conductive type first region formed in the first conductive type semiconductor layer and having a power semiconductor element; and the first conductive type A second region of the first conductivity type formed in the semiconductor layer and having a control circuit element; and a second conductivity type base region of the power semiconductor element formed in a surface region of the first region;
A first conductivity type source region of the power semiconductor element, which is formed in a surface region of the first region of the first conductivity type semiconductor layer and is surrounded by the second conductivity type base region, and the first conductivity type source region. A gate trench formed in a region and penetrating the second conductivity type base region from the main surface of the first conductivity type semiconductor layer therein, and the power semiconductor element formed on a sidewall of the gate trench. Gate oxide film, a gate electrode of the power semiconductor element formed in the gate trench and disposed on the gate oxide film, the second region or the first conductivity type semiconductor substrate, and the first conductive type semiconductor substrate. A second conductive type buried separation layer formed between the first conductive type semiconductor layer and the second region, and formed inward from the main surface of the first conductive type semiconductor layer formed between the first region and the second region. Element isolation trench It is formed between the isolation trenches and the second conductivity type buried isolation layer, a second conductivity type impurity diffusion regions connecting the two, the second
The conductive type buried isolation layer, the element isolation trench, and the second conductive type impurity diffusion region separate the second region of the first conductive type semiconductor layer from other regions of the first conductive type semiconductor layer. This is the second feature.

The depth of the element isolation trench from the main surface of the first conductivity type semiconductor layer can be made equal to the depth of the gate trench. The element isolation trench may include a large diameter portion in an upper portion thereof and a small diameter portion in a lower portion including a bottom portion. The depth of the large diameter portion from the main surface of the first conductivity type semiconductor layer may be equal to the depth of the gate trench. A method of manufacturing a semiconductor device according to the present invention includes a first conductivity type first region in which a power semiconductor element is formed and a first conductivity type second region in which a control circuit element is formed on a first conductivity type semiconductor substrate. With a region of
A step of forming a conductive type semiconductor layer; a step of forming a second conductive type embedded separation layer between the first conductive type semiconductor substrate and the first conductive type semiconductor layer; and a step of forming the first conductive type semiconductor layer. The second area of the power semiconductor device is formed on the surface area of the first area.
Forming a conductive type base region, and forming a first conductive type source region of the power semiconductor device surrounded by a second conductive type base region in a surface region of the first region of the first conductive type semiconductor layer. And a gate trench that is formed in the first conductivity type source region and penetrates the second conductivity type base region from the main surface of the first conductivity type semiconductor layer to the inside thereof. Forming a trench for element isolation that reaches the second conductive type buried isolation layer from the main surface of the layer and has a depth from the main surface of the N-type semiconductor layer that is the same as the trench for gate; The method is characterized by including a step of forming an oxide film on the side wall of the element isolation trench and a step of burying polysilicon in the gate and element isolation trench via the oxide film.

[0009]

Since the power MOSFET has the trench gate structure, there is no phenomenon such as the increase in the on-resistance per unit area, which is remarkable when the cell density is increased as in the above-mentioned conventional technique. Further, since the trench is used for element isolation, the ratio occupied by the isolation region can be greatly reduced. Further, the region where the power semiconductor element is formed and the region where the control circuit element is formed can be formed in the same step.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. First, a first embodiment will be described with reference to FIGS. FIG. 1 is a cross-sectional view of a power IC, FIGS.
Is a cross-sectional view of the manufacturing process thereof, and FIG. 6 is an operation explanatory view thereof. In the figure, the power IC includes a power MOSFET and a control circuit for controlling the power MOSFET, and a bipolar transistor is shown in the control circuit section as an example of a component. The MOSFET and the control circuit are formed on an N-type semiconductor layer 2 having a thickness of about 10 μm formed on a silicon N ⁺ semiconductor substrate 1 having a thickness of about 200 μm. N-type semiconductor substrate 1
A P-type buried isolation layer 3 is formed in a predetermined region between and the N-type semiconductor layer 2. From the surface of the N-type semiconductor layer 2 to P
An element isolation region 17 having a trench structure is formed so as to reach the mold buried isolation layer 3. In the element isolation region 17, the N-type semiconductor region 21 independent of the others is formed in the N-type semiconductor layer 2 together with the P-type buried isolation layer 3, and a control circuit is formed therein similarly to the conventional example. In this semiconductor region 21,
P-type base region 11, high impurity concentration N ⁺ collector region 1
A bipolar transistor with 2 and N ⁺ emitter regions 121 is formed.

Trench 16 constituting the element isolation region 17
Has reached the inside of the P-type buried separation layer 3 and has about 1
There is a depth of 0 μm. Then, a silicon oxide film 14 is formed on the surface of the inner side wall. The surface of the N-type semiconductor layer 2 including the inside of the trench 16 is covered with this oxide film 15, and an insulating film 9 such as a silicon oxide film is formed thereon. The electrodes in each region of the bipolar transistor are exposed to the outside through the contact holes formed in the insulating film 9 and the oxide film 15. That is, the base electrode B connected to the P-type base region 11 and the N ⁺ collector region 12
Collector electrode C and N ⁺ emitter region 121 connected to
The emitter electrode E connected to is exposed on the insulating film 9 through the contact hole. The power MOSFET is formed in a region of the N-type semiconductor layer 2 outside the N-type semiconductor region 21. The P-type base region 5 is formed in the surface region of the N-type semiconductor layer 2, and the N ⁺ source region 6 is formed in the region. A trench 13 is formed through the P-type base region 5 and the N ⁺ source region 6, and a silicon oxide film serving as a gate oxide film 7 is formed on the side surface of the trench 13. Then, inside the trench 13, polysilicon to be the gate electrode 8 is formed. P through the contact holes of the silicon oxide film 7 and the insulating film 9
A part of the mold base region 5 and the N ⁺ source region 6 is exposed, and the source electrode 10 is electrically connected to the exposed part.
Are formed on the insulating film 9.

A drain electrode 18 is formed on the surface of the semiconductor substrate 1 opposite to the surface on which the N-type semiconductor layer 3 is formed. FIG. 6 shows the power I formed on this semiconductor substrate.
FIG. 11 is a cross-sectional view of a semiconductor substrate illustrating the operation of C. M in the figure
When the OSFET cell is turned on, the current I flows from the drain electrode 18 through the channel to the source electrode 10 as shown by the arrow in the figure, but the channel region is formed under the gate oxide film 7 near the drain sidewall. It Therefore, the conventional JFET portion does not exist, and even if the cell arrangement pitch is reduced, the on-resistance is not affected, so that the density of the semiconductor device can be increased.

Next, a method of manufacturing the power IC of this embodiment will be described with reference to FIGS. First, the surface of a silicon N ⁺ semiconductor substrate 1 having a thickness of about 200 μm that is heavily doped with an N-type impurity such as arsenic (As) is exposed to a high-temperature oxidizing atmosphere to form a silicon oxide film. This oxide film is selectively etched using a photoresist to form a pattern for forming a P-type buried isolation layer. After removing the photoresist, a P-type impurity such as boron (B) is thermally diffused in the patterned portion of the oxide film at, for example, about 1200 to 1300 ° C. to form the P-type buried separation layer 3. The oxide film on the surface of the semiconductor substrate 1 is removed, and, for example, a silane compound and a phosphorus compound are decomposed at a high temperature to grow an N-type semiconductor layer 2 having a thickness of about 10 μm on the semiconductor substrate 1 (FIG. 2A). . Next, for example, B is ion-implanted from the surface of the N-type semiconductor layer 2 to form a P-well in the surface region of the N-type semiconductor layer 2 where the P-type buried separation layer 3 is not formed, and the P-type well is formed. The base region 5 is used (FIG. 2B). Next, from the surface of the P-type base region 5, As
N type impurities such as are doped at a high concentration by ion implantation or the like to form N ⁺ source regions 6 in the P type base region 5 (FIG. 3A). A trench 13 is formed from the surface of the N-type semiconductor layer 2 so as to penetrate the P-type base region 5 and the N ⁺ source region 6. The depth from the surface of the trench 13 is several μm larger than the depth of the P-type base region 5.

Then, the surface of the N-type semiconductor layer 2 including the inside of the trench 13 is heated at a high temperature to form a silicon thermal oxide film 1 on the surface.
5 is formed. This thermal oxide film is used as the gate oxide film 7 inside the trench. A polysilicon film is deposited on the surface of the N-type semiconductor layer 2 including the inside of the trench 13, and the polysilicon film is patterned by using a photoresist or the like to embed the polysilicon electrode 8 in the trench 13 (FIG. 4).
(A)). Next, the trench 1 reaching the element isolation region of the N-type semiconductor layer 2 from its surface into the P-type buried isolation layer 3 is formed.
6 is formed, and the silicon oxide film 14 is also formed inside the trench 16 by thermal oxidation or the like (FIG. 4B). A bipolar transistor of a MOSFET control circuit is formed in the N-type element region 21 surrounded by the trench 16 and the P-type buried isolation layer 3. First, a P-type impurity such as B is doped by ion implantation or the like to form a P-well that becomes the P-type base region 11, and then an N-type impurity such as As is ion-implanted or the like to form the P-well and the N-type element region 21. To a high concentration to form an N ⁺ emitter region 121 and an N ⁺ collector region 12 in the P well 11. After forming the control circuit, for example, SiO ₂ is formed on the surface of the N-type semiconductor layer _2.
An insulating film 9 such as a film is formed by the CVD method or the like. Si
The O ₂ film is naturally formed also in the trench 16, and the side wall is covered with the oxide film 14 and the trench 16 filled with the SiO ₂ film is used as the element isolation region 17 (see FIG. a)).

Next, a contact pattern of the insulating film 9 is formed by using photoresist, and the insulating film 9 and the oxide film 15 thereunder are selectively etched to form contact holes to form the P-type base region 5. , 11, N ⁺ source region 6, N ⁺
The emitter region 121 and the N ⁺ collector region 12 are partially exposed. In this state, in vacuum, for example, A
l is evaporated to deposit an Al film on the entire surface of the N-type semiconductor layer 2. At this time, the Al film is also deposited in the contact hole exposing each region and connected to each region. Then, a photoresist is formed and patterned, and the Al film is selectively etched using the patterned photoresist as a mask to form an emitter electrode, a base electrode, a collector electrode and a source electrode 10 in each region. (FIG.5 (b)). After that, the entire surface of the back surface of the semiconductor substrate 1 is covered with a drain electrode 18 such as an Al film. The surface of each electrode is protected by a protective insulating film or the like (not shown). The present invention is not limited to the manufacturing process of the above embodiment, and for example, the isolation trench 16 and the gate trench 13 may be formed in the same process, or the isolation trench 16 may be formed first. You may implement the process to do.

Next, a second embodiment will be described with reference to FIG. FIG. 7 is a sectional view of the power IC. In the figure, the power IC includes a power MOSFET and a control circuit for controlling the power MOSFET, and a bipolar transistor or the like is formed in the control circuit portion. The MOSFET and the control circuit are composed of an N-type semiconductor layer 2 having a thickness of about 10 μm formed on a silicon N ⁺ semiconductor substrate 1 having a thickness of about 200 μm.
Is formed in. N-type semiconductor substrate 1 and N-type semiconductor layer 2
A P-type buried separation layer 3 is formed in a predetermined region between and. From the surface of the N-type semiconductor layer 2 to the P-type buried separation layer 3
An element isolation region 17 having a trench structure is formed so as to reach the. This element isolation region 17 forms an N-type semiconductor region 21 independent of the others in the N-type semiconductor layer 2 together with the P-type buried isolation layer 3 and forms a control circuit therein. And
The surface of the N-type semiconductor layer 2 is covered with this oxide film 15, and an insulating film 9 such as a silicon oxide film is formed thereon. The electrodes in each region of the bipolar transistor are exposed to the outside through the contact holes formed in the insulating film 9 and the oxide film 15. The power MOSFET is formed in a region of the N-type semiconductor layer 2 outside the N-type semiconductor region 21.

The P type base region 5 is formed in the surface region of the N type semiconductor layer 2, and the N ⁺ source region 6 is formed in the region. The P-type base region 5 and the N ⁺ source region 6 have trenches formed therethrough,
A silicon oxide film to be the gate oxide film 7 is formed on the side surface. Then, polysilicon to be the gate electrode 8 is formed inside the trench. Part of the P-type base region 5 and the N ⁺ source region 6 is exposed through the contact holes of the silicon oxide film 7 and the insulating film 9, and the source electrode 10 electrically connected to this exposed portion is the insulating film 9 Is formed on. Further, a drain electrode 18 is formed on the surface of the semiconductor substrate 1 opposite to the surface on which the N-type semiconductor layer 3 is formed. The surface of each electrode is protected by a protective insulating film. This embodiment is characterized by the structure of the element isolation region 17. This element isolation region 17
Is composed of the oxide film 14 formed on the inner wall of the trench 16 formed in the N-type semiconductor layer 2 and the polysilicon 19 embedded in the trench 16. In the figure, the polysilicon 19 is exposed on the surface of the N-type semiconductor layer 2, that is, outside the trench, but the surface can be thermally oxidized to confine the polysilicon in the trench. In this embodiment, the parasitic capacitance can be reduced. The tip of the trench 16 reaches the inside of the P-type buried isolation layer 3 and has a depth of about 10 μm.

Next, a third embodiment will be described with reference to FIG. The figure is a cross-sectional view of the power IC. In the figure, the power IC includes a power MOSFET and a control circuit for controlling the power MOSFET, and a bipolar transistor or the like is formed in the control circuit portion. This MOSFET and the control circuit consist of a silicon N ⁺ semiconductor substrate 1 with a thickness of about 200 μm.
Is formed on the N-type semiconductor layer 2 having a thickness of about 20 μm. In the first and second embodiments, N
The P type buried separation layer 3 was formed in a predetermined region between the type semiconductor substrate 1 and the N type semiconductor layer 2. In this embodiment, the surface of the P-type buried separation layer 3 is formed in the middle of the N-type semiconductor layer 2 at a depth of about 10 μm from the surface thereof. Then, an element isolation region 17 having a trench structure is formed so as to reach the P-type buried isolation layer 3 from the surface of the N-type semiconductor layer 2. This element isolation region 17 forms an N-type semiconductor region 21 independent of the others in the N-type semiconductor layer 2 together with the P-type buried isolation layer 3 and forms a control circuit therein. The surface of the N-type semiconductor layer 2 is covered with an oxide film 15, and an insulating film 9 such as a silicon oxide film is formed thereon.
The electrodes in each region of the bipolar transistor are exposed to the outside through the contact holes formed in the insulating film 9 and the oxide film 15. The power MOSFET is formed in a region of the N-type semiconductor layer 2 outside the N-type semiconductor region 21.

The P type base region 5 is formed in the surface region of the N type semiconductor layer 2, and the N ⁺ source region 6 is formed in the region. The P-type base region 5 and the N ⁺ source region 6 have trenches formed therethrough,
A silicon oxide film to be the gate oxide film 7 is formed on the side surface. Then, polysilicon to be the gate electrode 8 is buried inside the trench. Part of the P-type base region 5 and the N ⁺ source region 6 is exposed through the contact holes of the silicon oxide film 7 and the insulating film 9, and the source electrode 10 electrically connected to this exposed portion is the insulating film 9 Is formed on. Further, the drain electrode 18 is formed on the back surface of the semiconductor substrate 1 opposite to the surface on which the N-type semiconductor layer 3 is formed. The surface of each electrode is protected by a protective insulating film. This embodiment is characterized in that the depth of the element isolation region 17 trench from the surface of the N-type semiconductor layer 2 is shallower than the depth of the gate trench. In the above embodiments, the thickness of the N-type semiconductor layer 2 is 10 μm.
Since the power MOSFET formed therein has a withstand voltage of about 60 V, the N-type semiconductor layer 2 is further thickened to further increase the withstand voltage, and the epitaxial growth is performed to, for example, about 20 μm. And the gate electrode 8
The depth of the buried trench 13 from the surface of the N-type semiconductor layer 2 is increased.

In this embodiment, the P-type buried separating layer 3 is
Instead of being formed at the boundary between the semiconductor substrate 1 and the N-type semiconductor layer 2, it is formed in the N-type semiconductor layer 2. Therefore, the P-type buried separation layer 3 is formed in the N-type semiconductor layer 2 by ion implantation after the N-type semiconductor layer 2 is epitaxially grown on the semiconductor substrate 1. This element isolation region 17
Is composed of an oxide film 14 formed on the inner wall of the trench 16 formed in the N-type semiconductor layer 2 and an insulating film formed inside the trench 16. Next, a fourth embodiment will be described with reference to FIG. The figure is a cross-sectional view of the power IC. In the figure, the power IC includes a power MOSFET and a control circuit for controlling the power MOSFET, and a bipolar transistor or the like is formed in the control circuit portion. The semiconductor device of this embodiment is structurally the same as the semiconductor device shown in FIG. 7 except for the depths of the element isolation and gate trenches. Also in this embodiment, in the trench of the element isolation region 17, the polysilicon 19 which is electrically independent from the others is buried on the oxide film 14 as in FIG. It is characterized in that the depth from the surface of the N-type semiconductor layer 2 to its bottom is equal to the depth of the trench for the gate electrode. In this way, by making all the trenches have the same depth, the trench forming process can be made common. Therefore, for example, the element isolation trench 16 can be formed in the gate trench forming step shown in FIG. 3B, so that the step can be simplified.

Next, a fifth embodiment will be described with reference to FIG. The figure is a cross-sectional view of the power IC. In the figure, the power IC includes a power MOSFET and a control circuit for controlling the power MOSFET, and a bipolar transistor or the like is formed in the control circuit portion. The semiconductor device of this embodiment is different from the semiconductor device shown in FIG. 9 in that the structure of the element isolation trench is different, and there is no other particular structural difference. In the trench of the element isolation region 17, an insulating film 9 such as CVD SiO ₂ that covers the N-type semiconductor layer 2 is formed on the oxide film 14. The upper part of the element isolation trench including the opening has a large diameter part, and the lower part including the bottom part embedded in the P-type buried isolation layer 3 has a small diameter part. The depth of the upper large diameter portion from the surface of the N-type semiconductor layer 2 is equal to the depth of the gate trench 13. Therefore, until the large-diameter portion is formed, it is formed in the gate trench forming step as in the previous embodiment, and the large-diameter portion and the small-diameter portion are formed by adding a few trenches until the P-type buried isolation layer 3 is reached. A deep element isolation trench having a portion can be formed.
A high breakdown voltage semiconductor device having a thick N-type semiconductor layer can be provided in a small number of steps. It is also possible to fill this element isolation trench with polysilicon.

Next, a sixth embodiment will be described with reference to FIG. The figure is a cross-sectional view of the power IC. In the figure, the power IC includes a power MOSFET and a control circuit for controlling the power MOSFET, and a bipolar transistor or the like is formed in the control circuit portion. The semiconductor device of this embodiment is structurally the same as the semiconductor device shown in FIG. 7 except that the structure of the element isolation trench is different. Also in this embodiment, in the trench of the element isolation region 17,
Similar to FIG. 7, polysilicon 19 electrically isolated from the others is buried on the oxide film 14, but in FIG. 7, the bottom of the element isolation trench reaches the P-type buried isolation layer 3. First, the P-type impurity diffusion region 20 is formed on the trench bottom and P
It is connected to the mold embedding separation layer 3. That is, the element isolation region 17 is composed of this trench and the P-type impurity diffusion region 20. The P-type impurity diffusion region 20 is formed by the following procedure, for example. In the step of forming the trench 16 in the element isolation region 17 as shown in FIG. 4, the trench formation is stopped before the bottom reaches the P-type buried isolation layer 3, and thereafter, ion implantation or solid phase diffusion is performed from the bottom of the trench. Thus, the impurities are diffused to form the P-type disordered substance diffusion region 20 connected to the P-type buried isolation layer 3. A deep element isolation region 17 can be formed by forming a trench to a certain depth and forming a small amount of diffusion region until reaching the P-type buried isolation layer 3. N
A high breakdown voltage semiconductor device having a thick type semiconductor layer can be provided in a small number of steps. It is also possible to fill the trench for element isolation with polysilicon instead of polysilicon.

Next, a seventh embodiment will be described with reference to FIG. The figure is a cross-sectional view of the power IC. In the figure, the power IC includes a power MOSFET and a control circuit for controlling the power MOSFET, and a bipolar transistor or the like is formed in the control circuit portion. The semiconductor device of this embodiment is structurally the same as the semiconductor device shown in FIG. 11 except that the structure of the element isolation trench is different.
Also in this embodiment, in the trench of the element isolation region 17, polysilicon 19 which is electrically independent from the others is buried on the oxide film 14 similarly to FIG. 11, and the bottom of the element isolation trench is P. The mold embedded separation layer 3 has not been reached,
A P-type impurity diffusion region 20 connects the bottom of the trench and the P-type buried isolation layer 3. That is, the element isolation region 1
Reference numeral 7 is composed of this trench and a P-type impurity diffusion region 20. However, this embodiment is characterized in that the depth of the element isolation trench is substantially equal to the depth of the gate trench. By making the depths of all the trenches equal, the trench forming process can be made common. Therefore, for example, the element isolation trenches 16 can be formed during the gate trench formation step shown in FIG. 3B, so that the step can be simplified.

In order to form the P-type impurity diffusion region 20, for example, the following procedure is performed. In the step of forming the trench 16 in the element isolation region 17 as shown in FIG. 4, the trench formation is stopped before the bottom reaches the P-type buried isolation layer 3, and thereafter, ion implantation or solid phase diffusion is performed from the bottom of the trench. Thus, the impurities are diffused to form the P-type disordered substance diffusion region 20 connected to the P-type buried isolation layer 3. A deep element isolation region 17 can be formed by forming a trench to a certain depth and forming a small amount of diffusion region until reaching the P-type buried isolation layer 3. Also,
A high breakdown voltage semiconductor device having a thick N-type semiconductor layer can be provided in a small number of steps. It is also possible to fill the trench for element isolation with polysilicon instead of polysilicon.

[0025]

According to the present invention, with the above-mentioned structure, even if the cell density is increased, the phenomenon of increasing the on-resistance per unit area is small and the density of the cells can be easily increased. Can be significantly reduced, so that a semiconductor device with a high degree of integration can be provided. Further, the region having the power semiconductor element and the region having the control circuit element can be formed in the same step, which facilitates the manufacturing thereof.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of the manufacturing process of the semiconductor device of the first embodiment.

FIG. 3 is a cross-sectional view of the manufacturing process of the semiconductor device of the first embodiment.

FIG. 4 is a cross-sectional view of the manufacturing process of the semiconductor device of the first embodiment.

FIG. 5 is a cross-sectional view of the manufacturing process of the semiconductor device of the first embodiment.

FIG. 6 is a cross-sectional view illustrating the operation of the semiconductor device according to the first embodiment.

FIG. 7 is a sectional view of a semiconductor device according to a second embodiment.

FIG. 8 is a sectional view of a semiconductor device according to a third embodiment.

FIG. 9 is a sectional view of a semiconductor device according to a fourth embodiment.

FIG. 10 is a sectional view of a semiconductor device according to a fifth embodiment.

FIG. 11 is a sectional view of a semiconductor device according to a sixth embodiment.

FIG. 12 is a sectional view of a semiconductor device according to a seventh embodiment.

FIG. 13 is a sectional view of a conventional semiconductor device.

FIG. 14 is a cross-sectional view illustrating the operation of a conventional semiconductor device.

[Explanation of symbols]

1 semiconductor substrate 2 N-type semiconductor layer 3 P-type buried isolation layer 4, 17 P-type element isolation region 5, 11 P-type base region 6 N ⁺ source region 7 gate oxide film 8 gate electrode 9 insulating film 10 source electrode 12 N ⁺ Collector region 13 Gate trench 14, 15 Oxide film 16 Element isolation trench 18 Drain electrode 19 Polysilicon film 20 P-type impurity diffusion region 21 N-type semiconductor region 121 N ⁺ emitter region

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI Technical indication location H01L 21/331 29/73 H01L 29/72 9055-4M 29/78 321 C

Claims (6)

[Claims] 1. A first-conductivity-type semiconductor substrate, a first-conductivity-type semiconductor layer formed on the first-conductivity-type semiconductor substrate, and a power semiconductor element formed on the first-conductivity-type semiconductor layer. A first region of a first conductivity type, a second region of a first conductivity type formed in the first conductivity type semiconductor layer and having a control circuit element, and a surface region of the first region. A second conductivity type base region of the power semiconductor element; and a first conductivity type source region of the power semiconductor element formed in a surface region of the first region and surrounded by the second conductivity type base region. A gate trench formed in the first conductivity type source region and penetrating from the main surface of the first conductivity type semiconductor layer to the second conductivity type base region, and formed on a sidewall of the gate trench. Of the power semiconductor device Oxide film, a gate electrode of the power semiconductor element formed in the gate trench and disposed on the gate oxide film, in the second region or in the first conductivity type semiconductor substrate, and in the first conductive type semiconductor substrate. A second conductive type buried separation layer formed between the first conductive type semiconductor layer and the second conductive region, and a second conductive type buried separation layer formed between the first conductive type semiconductor layer and the first conductive type semiconductor layer; An element isolation trench reaching a second conductivity type buried isolation layer, the second conductivity type buried isolation layer and the element isolation trench forming the second region of the first conductivity type semiconductor layer with the first region; A semiconductor device characterized by being separated from other regions of a conductive type semiconductor layer. 2. A first conductivity type semiconductor substrate, a first conductivity type semiconductor layer formed on the first conductivity type semiconductor substrate, and a power semiconductor element formed on the first conductivity type semiconductor layer. A first region of a first conductivity type, a second region of a first conductivity type formed in the first conductivity type semiconductor layer and having a control circuit element, and a surface region of the first region. Further, the power semiconductor element is formed in the second conductivity type base region of the power semiconductor element and the surface region of the first region of the first conductivity type semiconductor layer, and is surrounded by the second conductivity type base region. A first-conductivity-type source region, and a gate trench formed in the first-conductivity-type source region and penetrating the second-conductivity-type base region from the main surface of the first-conductivity-type semiconductor layer therein. Before formed on the sidewall of the gate trench A gate oxide film of the power semiconductor element, a gate electrode of the power semiconductor element formed in the gate trench and disposed on the gate oxide film, in the second region or in the first conductivity type A second conductive type buried separation layer formed between a semiconductor substrate and the second region; and a first conductive type semiconductor layer formed at least between the first region and the second region. An element isolation trench formed inward from the main surface of the element, and a second conductivity type impurity diffusion region formed between the element isolation trench and the second conductivity type buried isolation layer and connecting the two. The second conductivity type buried isolation layer, the element isolation trench, and the second conductivity type impurity diffusion region, and the second region of the first conductivity type semiconductor layer is replaced with the other of the first conductivity type semiconductor layer. Specially separated from The semiconductor device according to. 3. The depth of the element isolation trench from the main surface of the first conductivity type semiconductor layer is equal to the depth of the gate trench.
The semiconductor device according to. 4. The device isolation trench according to claim 1, wherein a large diameter portion is provided at an upper portion of the element isolation trench, and a small diameter portion is provided at a lower portion including a bottom portion. Semiconductor device. 5. The depth of the large-diameter portion from the main surface of the first conductivity type semiconductor layer is equal to the depth of the gate trench. The semiconductor device according to. 6. A first-conductivity-type first region in which a power semiconductor element is formed and a first-conductivity-type second region in which a control circuit element is formed on a first-conductivity-type semiconductor substrate. Forming a first conductive type semiconductor layer, forming a second conductive type buried separation layer between the first conductive type semiconductor substrate and the first conductive type semiconductor layer, and the first conductive type semiconductor Forming a second conductivity type base region of the power semiconductor element on a surface region of the first region of the layer; and forming a second conductivity type base region of the first conductivity type semiconductor layer on the surface region of the first region.
Forming a first conductivity type source region of the power semiconductor element surrounded by a conductivity type base region; and forming a first conductivity type source region in the first conductivity type source region from a main surface of the first conductivity type semiconductor layer. Inside the gate trench that penetrates the second conductivity type base region and the main surface of the first conductivity type semiconductor layer to the second conductivity type buried separation layer, the depth from the main surface of the N type semiconductor layer is the above. Forming a device isolation trench that is the same as the gate trench, forming an oxide film on the sidewalls of the gate and device isolation trenches, and forming the oxide film in the gate and device isolation trenches And a step of burying polysilicon through the via.