JPH06325584A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To expand an operating margin, and to increase the speed of an access time by substantially equalizing the potential of erase voltage supplied to sources bonded in common in cells constituting each memory block while successively reducing the number of erase pulses in full erase modes from the memory blocks. CONSTITUTION:When holding information is written to two-layer gate structure type memory cells MC, positive potential having a large absolute value is applied to control gates and positive voltage at intermediate potential to drains respectively, and hot electrons generated by an avalanche breakdown are injected into floating gates. When the holding information of the cells MC is erased, large positive potential is applied to sources, and the holding information is erased by extracting electrons stored in the floating gates by a tunnel phenomenon to the source sides. The number of erase pulses supplied on full erase modes is reduced successively from memory blocks adjacent to bonding pads for feeding erase voltage at that time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a technique which is particularly effective when used in a flash memory or the like having an erase control circuit for the full erase mode.

[0002]

2. Description of the Related Art A so-called two-layer gate structure type non-volatile memory cell having a control gate and a floating gate (hereinafter referred to as a two-layer gate structure cell) is arranged in a grid pattern as a basic constituent element. There is flash memory. Further, there is a so-called block erasing type flash memory in which the memory array is divided into a plurality of memory blocks in units of a predetermined number of memory cells and the retained information can be collectively erased in units of these memory blocks.

A block erase type flash memory is described in, for example, US Pat. No. 5,065,365.

[0004]

Prior to the present invention, the inventors of the present invention incorporate an erase control circuit ERC to hold all memory cells while suppressing variations in threshold voltage after the memory cells are erased. We have developed a block erase type flash memory that has an all erase mode for erasing information in a batch. This flash memory has 32 memory blocks MB0 to MB31 in which a memory array is divided.
And 32 erase gates EG0 to EG31 for selectively transmitting the erase voltage VPP of, for example, +12 V to the commonly connected sources of a plurality of memory cells provided corresponding to these memory blocks and configuring the corresponding memory blocks. And a source switch SS including.

When the flash memory is set to the all-erase mode, the erase control circuit ERC first executes so-called pre-write for writing data of logic "0" to all memory cells and then blocks as shown in FIG. The number BN and the in-block address AD are initialized to 0 and the erase operation is started. This erase operation is an erase determination for verifying the retained information of the memory cell of the specified address to identify the erased state, that is, the change to the logic "1", and the common combination of the memory cells forming all the memory blocks. This is performed by repeating the operation of supplying the pulsed erase voltage VPP, that is, the erase pulse to the source. When the memory cell is in the erased state as a result of the erase determination, the address of the memory cell to be erased is counted up. When the erase determination of all the memory cells forming the memory block MB0 is completed, the supply of the erase pulse to the memory block MB0 is stopped and the block number is counted up, and the memory cells forming the next memory block MB1 are counted. Then, the process proceeds to the erase determination. Hereinafter, the same erase operation is performed in the memory block MB31.
This process is repeated until the erase determination of all the memory cells that make up the memory cell is completed, which does not lower the threshold voltage of the memory cells more than necessary and does not require the control of an external microprocessor. By the way
All the memory cells of the flash memory can be put in the erased state.

However, increasing the capacity of the flash memory
It has been clarified by the inventors of the present application that the following problems remain in the flash memory having the above-mentioned all-erasure mode as the scale increases. That is, in the above flash memory, as illustrated in FIG. 5, memory blocks MB0 to MB31 are arranged in alignment in the vertical direction of the semiconductor substrate PSUB, and the commonly combined sources of the memory cells forming these memory blocks are arranged. Erase voltage V
The erase gates EG0 to EG31 of the source switch SS for selectively supplying PP are also arranged close to the right side of the corresponding memory block. On the other hand, the bonding pad VPP for inputting the erase voltage VPP to the flash memory is arranged, for example, at the lower right end of the semiconductor substrate PSUB, and the erase voltage VPP input via this bonding pad VPP is the erase voltage supply wiring SVP. It is transmitted to the erase gates EG0 to EG31 via the erase gates.

As is well known, the threshold voltage of the two-layer gate structure cell in the erase operation decreases faster as the absolute value of the erase voltage VPP applied to the source increases. Further, the erase voltage supply wiring SVP and the like made of a metal wiring layer have a distributed resistance according to the wiring width and the wiring thickness, and are connected to the erase voltage supply bonding pad VPP and the erase gates EG0 to EG31 constituting the source switch SS. In between, as shown in FIG. 10, wiring resistors RS0 to RS31 corresponding to the wiring length are equivalently coupled. In addition, in the all erase mode of the flash memory, as described above, the erase determination is performed in order from the memory block MB0 arranged at the position farthest from the erase voltage supply bonding pad VPP, that is, the sum of the wiring resistances is maximum. The pulse-shaped erase voltage VPP is continuously applied to the memory block MB31 arranged closest to the erase voltage supply bonding pad VPP until the erase determination is completed for all the memory blocks. Therefore, as shown in FIG. 9, for example, the memory block M
The central value Vth1b of the distribution of threshold voltages after erasing of the memory cells forming B31 and the central value Vth of the distribution of threshold voltages after erasing of the memory cells forming the memory block MB0.
A relatively large erase variation occurs between th1c and th1c. As a result, the operation margin on the minimum power supply voltage side of the flash memory is reduced, and the speeding up of the access time is restricted.

An object of the present invention is to reduce erase variation in all erase modes of a flash memory having an erase control circuit. Another object of the present invention is to expand the operation margin on the side of the minimum value of the power supply voltage of a flash memory or the like and promote the speeding up of the access time.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0010]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, a predetermined erase voltage is selectively applied to a plurality of memory blocks formed by dividing a memory array and a common-coupled source of a plurality of memory cells provided corresponding to these memory blocks and forming the corresponding memory blocks. In a block erase type flash memory, etc., which has a source switch including a plurality of erase gates for transmitting to the memory and an erase control circuit for collectively erasing information held in all memory cells, input through an erase voltage supply bonding pad The smoothing resistor for equalizing the resistance value is provided between each branch point of the erase voltage supply wiring that transmits the erase voltage to be erased to a plurality of erase gates and the corresponding erase gate. A memory block that is placed close to the bonding pad for supplying the erase voltage for the erase determination in the erase mode. Carried out in order from.

[0011]

According to the above means, even when the capacity and the size of the flash memory are increased and the chip is increased in size,
The potential of the erase voltage supplied to the commonly connected sources of the memory cells that make up each memory block can be made almost uniform, and the number of erase pulses supplied in all erase modes can be set close to the erase voltage supply bonding pad. It is possible to reduce the number of memory blocks sequentially arranged. As a result, it is possible to reduce the variation in threshold voltage between blocks after erasing the memory cell, so that it is possible to expand the operation margin on the minimum power supply voltage side of the flash memory and accelerate the access time.

[0012]

1 is a block diagram showing an embodiment of a flash memory to which the present invention is applied. Also,
FIG. 2 shows a partial circuit diagram of one embodiment of the memory array MARY included in the flash memory of FIG. 1 and its peripheral portion. Further, FIG. 3 shows a cross-sectional structural view of one embodiment of the two-layer gate structure cell that constitutes the memory array MARY of FIG. 2, and FIG. 4 shows the relationship between the drain current and the gate-source voltage. A characteristic diagram of one embodiment for explaining the above is shown. Based on these figures,
First, an outline of the configuration and operation of the flash memory of this embodiment will be described. The circuit elements shown in FIG. 2 and the circuit elements constituting the blocks shown in FIG. 1 are not particularly limited, but may be formed on a single semiconductor substrate surface such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique. It is formed.

In FIG. 1, the flash memory of this embodiment is not particularly limited, but 32 memory blocks MB0 to MB3 formed by dividing the memory array MARY.
1 is its basic component. Each of these memory blocks is arranged in parallel with the vertical direction of the drawing, as represented by the memory block MB0 of FIG.
It includes +1 word lines W0 to Wm and n + 1 data lines B0 to Bn arranged in parallel in the horizontal direction. At the intersection of these word lines and data lines, (m + 1) ×
(N + 1) memory cells MC are arranged in a grid pattern.

Here, the memory blocks MB0 to MB31
As shown in FIG. 3, the memory cell MC constituting the
A so-called two-layer gate structure cell, which is a P-type semiconductor substrate P
A pair of high-concentration N-type diffusion layers N ⁺ formed on the surface of the SUB
That is, the N-type diffusion layers ND1 and ND2 are used as its source and drain. Of these, a low-concentration N-type semiconductor region N ⁻ is formed between the diffusion layer ND1 serving as the source and the P-type semiconductor substrate PSUB, and the diffusion layer ND2 serving as the drain and the P-type semiconductor substrate are not particularly limited. A low concentration P-type semiconductor region P ⁻ is formed between the PSUB and PSUB.

A floating gate FG is formed in the middle of the diffusion layers ND1 and ND2, that is, in the upper layer of the channel region, with a relatively thin insulating film IS1 in between, and the upper layer of the floating gate FG is relatively thick. A control gate CG is formed across the insulating film IS2. The control gate CG is coupled to the so-called gate terminal of the memory cell MC.

In this embodiment, the holding information write operation to the memory cell MC of the two-layer gate structure type is such that the control gate CG is applied with a positive potential having a relatively large absolute value such as +12 V and the drain is applied with +5 V, for example.
It is realized by applying a positive intermediate potential as described above and injecting hot electrons generated by avalanche breakdown into the floating gate FG.
When hot electrons are injected into the floating gate FG, the memory cell MC is supposed to hold information of logic "0" as shown in FIG.
The threshold voltage is set to a relatively large value Vth0 such as 6V.

Next, in the erasing operation of the information held in the memory cell MC, a positive potential having a relatively large absolute value such as +12 V is applied to the source, and the electrons accumulated in the floating gate FG by the tunnel phenomenon are source side. It is realized by pulling out. When electrons are extracted by the tunneling phenomenon, the memory cell MC is supposed to hold information of logic "1" as shown in FIG.
The threshold voltage is set to a relatively small value Vth1 such as 0.5V.

On the other hand, the read operation of the information held in the memory cell MC is weak write, that is, the floating gate F.
In order to avoid inadvertent injection of carriers into G, for example, it is realized by applying a positive potential having a relatively small absolute value of about +1 V to the drain and applying a positive intermediate potential of about +5 V to the control gate CG. . When the memory cell MC holds information of logic "1" and its threshold voltage is set to a relatively small value Vth1, a relatively large read current is passed between its drain and source. When the memory cell holds the information of logic "0" and the threshold voltage is set to a relatively large value Vth0,
A relatively small read current is passed between the drain and source. These read currents are transmitted from the corresponding data lines B0 to Bn to the common data line C0, as will be described later.
Through C7 to the corresponding unit circuit of the sense amplifier SA, the logic level of the information held in the memory cell MC can be determined by the magnitude of the read current.

Returning to FIG. 2, the memory block MB0 will be taken as an example to explain the memory blocks MB0 to MB31 and their peripheral portions. The gates of the n + 1 memory cells MC arranged in the same row of the memory block MB0, that is, the control gates CG have corresponding word lines W0 to W0.
m + which are commonly connected to m and arranged in the same column
The drains of one memory cell MC are commonly coupled to the corresponding data lines B0 to Bn, respectively. The sources of all the memory cells MC that make up the memory block MB0 are
Commonly coupled to the corresponding source line S0. Needless to say, the word lines W0 to Wm are connected to the memory blocks MB1 to M.
The memory blocks MB1 to M are also shared by B31.
B31 includes n + 1 data lines B0 to Bn, respectively. Further, the sources of all the memory cells MC configuring the memory blocks MB1 to MB31 are commonly coupled to the corresponding source lines S1 to S31, respectively.

Word lines W0 to Wm forming memory blocks MB0 to MB31 are coupled to an X address decoder XD, as shown in FIG. The X address decoder XD is supplied with i + 1-bit internal address signals X0 to Xi from the X address buffer XB. Further, the X address buffer XB has address input terminals AX0 to AX.
X address signals AX0 to AXi are supplied via Xi, and erase X address signals EX0 to EXi are supplied from an erase control circuit ERC described later.

The X address buffer XB fetches and holds the X address signals AX0 to AXi supplied through the address input terminals AX0 to AXi when the flash memory is selected in the normal read mode or write mode. . Further, when the flash memory is set to the all erase mode, the erase X address signals EX0 to EXi supplied from the erase control circuit ERC are fetched and held. Then, the internal address signals X0 to Xi are formed based on these X address signals or erase X address signals,
It is supplied to the X address decoder XD.

The X address decoder XD has internal address signals X0 to Xi supplied from the X address buffer XB.
Are decoded to set the corresponding word lines W0 to Wm of the memory array MARY to a predetermined selected or non-selected level.
In this embodiment, the selection level of the word lines W0 to Wm in the write mode is the positive potential VPP such as + 12V, and the non-selection level is the ground potential VSS, as described above. The selection level of the word lines W0 to Wm in the read mode is the power supply voltage VCC such as + 5V, and the non-selection level thereof is the ground potential VSS. When the flash memory is set to the verify mode, the selection levels of the word lines W0 to Wm are +3.
When the positive potential having a relatively small absolute value such as 5 V is used and the erasing operation for the corresponding memory blocks MB0 to MB31 is performed, the word lines W0 to Wm have the ground potential VSS.
It is a non-selection level such as.

Next, the data lines B0 to Bn forming the memory blocks MB0 to MB31 are, as represented by the memory block MB0 in FIG. 2, representative of the N channel type switch MOSFET (metal) corresponding to the Y switch YS. An oxide semiconductor field effect transistor.
The MOSFET is collectively referred to as an insulated gate field effect transistor) N2. Y switch YS
The memory blocks MB0 to MB31 are not particularly limited.
Data lines B0 to Bn and eight common data lines C0 to C7
32 × (n + 1) switches MO provided between and
Includes SFETN2. These switch MOSFETN
The two gates are sequentially connected in common by eight, and the corresponding data line selection signals YS0 to YS from the Y address decoder YD.
Sp is supplied in common. Needless to say, the number of bits p + 1 of the data line selection signal has a relationship of p + 1 = 32 × (n + 1) / 8.

Switch MOS which constitutes the Y switch YS
FETN2 has corresponding data line selection signals YS0 to YS.
When p is set to the high level, eight pieces are selectively turned on, and eight corresponding data lines B0 to Bn forming the memory blocks MB0 to MB31 and the common data line C0.
To C7 are selectively connected.

The Y address decoder YD outputs a j + 1-bit internal address signal Y0 from the Y address buffer YB.
~ Yj are supplied. The Y address buffer YB is supplied with the Y address signals AY0 to AYj via the address input terminals AY0 to AYj, and the erase Y address signals EY0 to EYj from the erase control circuit ERC.

The Y address buffer YB fetches the Y address signals AY0 to AYj supplied through the address input terminals AY0 to AYj when the flash memory is selected in the normal read or write mode.
Hold. Further, when the flash memory is set to the all erase mode, the erase Y address signals EY0 to EYj supplied from the erase control circuit ERC are fetched and held. Then, the internal address signals Y0 to Yj are formed based on these Y address signal or erase Y address signal and are supplied to the Y address decoder YD. Y address decoder YD
Decodes the internal address signals Y0 to Yj supplied from the Y address buffer YB and selectively sets the corresponding data line selection signals YS0 to YSp to the high level.

On the other hand, the source lines S0 to S31 of the memory blocks MB0 to MB31 of the memory array MARY are as shown in FIG.
, The source switch S0 is coupled to the output terminals of the corresponding erase gates EG0 to EG31 of the source switch SS. The source switch SS includes 32 erase gates EG0 to EG3 provided corresponding to the memory blocks MB0 to MB31, that is, the source lines S0 to S31.
1 and each of these erase gates includes an erase voltage V 1 as represented by the erase gate EG0 in FIG.
P provided in series between PP and the ground potential VSS
Channel MOSFET P1 and N channel MOSF
Including ETN1. The gates of these MOSFETs P1 and N1 are commonly connected to each other, and the corresponding inverted internal control signal E is supplied from a decoder (not shown) of the source switch SS.
0B to E31B (here, a so-called inverted signal or the like which is selectively brought to a low level when it is valid is represented by adding B to the end of the name. The same applies hereinafter). The inverted internal control signals E0B to E31B
Is normally set to a high level such as +12 V, and when the flash memory is set to the full erase mode or the block erase mode, the ground potential VS is alternatively provided with a predetermined pulse width.
It is set to a low level like S.

Corresponding inverted internal control signals E0B-E31
When B is set to a high level such as + 12V, the erase gates EG0 to EG31 of the source switch SS have MO
The SFETN1 is turned on and the MOSFET P1 is turned off. Therefore, the source lines S0 to S31 are
It is set to a low level like the ground potential VSS.

On the other hand, the corresponding inverted internal control signals E0B ...
When E31B is at a low level such as the ground potential VSS, the erase gates EG0 to EG3 of the source switch SS
In 1, the MOSFET N1 is turned off, and instead M
The OSFET P1 is turned on. Therefore, the erase voltage VPP of + 12V is supplied to the source lines S0 to S31, and the corresponding memory blocks MB0 to MB are thereby supplied.
All the memory cells forming B31 are simultaneously erased. As described above, the inverted internal control signals E0B-E
31B is set to the ground potential VSS with a predetermined pulse width and erase voltage VPP supplied to the source lines S0 to S31.
Is a similar pulse signal. In this embodiment, the pulse width of the inversion internal control signals E0B to E31B is set to be relatively short so that even the fastest memory cell does not invert to the erased state, and the erase voltage VPP having such a pulse width is used.
Is repeatedly supplied, the memory cells forming the corresponding memory block are gradually changed to the erased state.

The source switch SS is not particularly limited, but as shown in FIG.
From the upper 5 bits of the internal address signals Yj-4 to Yj. The source switch SS, when the flash memory is set to the all erase mode or the block erase mode,
The internal address signals Yj-4 to Yj supplied from the Y address buffer YB are decoded to selectively output the corresponding inverted internal control signals E0B to E31B to the ground potential VSS.
And low level.

Common data lines C0 to C7 in which the data lines B0 to Bn forming the memory blocks MB0 to MB31 are selectively connected to each other by eight via the Y switch YS.
Is coupled to the output terminal of the corresponding unit circuit of the write amplifier WA and is coupled to the input terminal of the corresponding unit circuit of the sense amplifier SA.

Write amplifier WA and sense amplifier SA
Includes eight unit circuits provided corresponding to the common data lines C0 to C7, respectively. Of these, the light amplifier W
The output terminal of each unit circuit A is the corresponding common data line C
0 to C7, the input terminals of which are coupled to the output terminals of the corresponding unit circuits of the data input buffer IB.
The input terminals of each unit circuit of the data input buffer IB are coupled to the corresponding data input / output terminals IO0 to IO7.
On the other hand, the input terminal of each unit circuit of the sense amplifier SA is coupled to the corresponding common data lines C0 to C7, and the output terminal thereof is coupled to the input terminal of the corresponding unit circuit of the data output buffer OB. The output terminal of each unit circuit of the data output buffer OB has corresponding data input / output terminals IO0-IO0.
Commonly connected to IO7.

Each unit circuit of the data input buffer IB is
When the flash memory is selected in the write mode, the write data input via the corresponding data input / output terminals IO0 to IO7 is fetched and transmitted to the corresponding unit circuit of the write amplifier WA. These write data are converted into a predetermined write signal by each unit circuit of the write amplifier WA, and are written in the selected eight memory cells of the memory blocks MB0 to MB31 via the common data lines C0 to C7. The level of the write signal output from each unit circuit of the write amplifier WA is +5 V when the corresponding write data is logic "0".
When the corresponding write data is set to logic "1", it is set to the ground potential VSS.

On the other hand, each unit circuit of the sense amplifier SA is
When the flash memory is selected in the read mode or the verify mode, the memory blocks MB0 to M
The read signal output from the selected eight memory cells of B31 via the corresponding common data lines C0 to C7 is amplified. These read signals are output by the data output buffer O when the flash memory is in the read mode.
The corresponding data input / output terminal I from the corresponding unit circuit of B
It is sent to the outside of the flash memory via O0 to IO7. Further, when the flash memory is set to the verify mode, it is transmitted to the erase control circuit ERC, which will be described later, and is used for judging the erased state of the selected eight memory cells. In this embodiment, memory blocks MB0 to MB
The read signal output from the eight selected 31 memory cells is a current signal having a value corresponding to the threshold voltage of the corresponding memory cell, as described above. Therefore, each unit circuit of the sense amplifier SA includes a current-voltage conversion circuit for converting a read signal obtained as a current signal into a voltage signal.

The flash memory of this embodiment further includes an erase control circuit ERC for collectively setting all the memory cells forming the memory array MARY to the erased state when the flash memory is set to the all erase mode. The erase control circuit ERC includes a timing control circuit TC
Is supplied with an all erase mode start signal (not shown) and an 8-bit read signal in the verify read mode is supplied from the sense amplifier SA. The erase control circuit ERC includes an erase determination circuit, an address counter, and a block counter, which are not shown, and selectively executes prewrite and erase operations for all memory cells according to an algorithm described later. At this time, the erase control circuit ERC
Are erase X address signals EX0 to EXi and erase Y
The address signals EY0 to EYj are formed and supplied to the X address buffer XB and the Y address buffer YB, and a predetermined write signal for prewriting is formed.
It is transmitted to the write amplifier WA. As a result, all the memory cells forming the memory blocks MB0 to MB31 can be brought into the erased state without lowering the threshold voltage of the memory cells more than necessary. The algorithm of the erase control circuit ERC in the all erase mode will be described in detail later.

The timing control circuit TC has a chip enable signal CE which is externally supplied as a start control signal.
Based on B, the write enable signal WEB, the output enable signal OEB and the erase enable signal EEB, various internal control signals are selectively formed and supplied to each part of the flash memory. The timing control circuit TC also has a function of identifying all the erase modes in response to the erase enable signal EEB being at the low level for a predetermined period and activating the erase control circuit ERC.

FIG. 5 shows a substrate layout diagram of an embodiment of the flash memory of FIG. 1, and FIG. 6 shows an equivalent circuit diagram of the erase voltage supply path. In addition, in FIG.
A process flow diagram of an embodiment of the full erase mode of the flash memory of FIG. 1 is shown, and FIG. 8 shows a threshold voltage after erasing of a two-layer gate structure cell forming the memory array of the flash memory of FIG. A distribution characteristic diagram showing one example is shown. Based on these drawings, the outline and features of the substrate arrangement and erase voltage supply path of the flash memory of this embodiment and the full erase mode will be described.

In FIG. 5, 32 memory blocks MB which are the basic constituent elements of the flash memory of this embodiment.
0 to MB31 occupy most of the central area of the P-type semiconductor substrate PSUB and are aligned. Memory block MB
An X address decoder XD is arranged at the upper ends of the word lines W0 to Wm forming the 0 to MB31, that is, at the upper part of the memory block MB0, and at the lower ends thereof, that is, the memory blocks MB.
An erase control circuit ERC is arranged below 31. Further, a Y switch YS and a Y address decoder YD are arranged on the left end side of the data lines B0 to Bn forming the memory blocks MB0 to MB31, and a source switch SS including the erase gates EG0 to EG31 is arranged on the right end side thereof. Will be placed. Erase gates EG0 to EG31 are arranged close to corresponding memory blocks MB0 to MB31, respectively.

Above the X address decoder XD, a predetermined number of bonding pads PAD are arranged in rows along the upper side of the semiconductor substrate PSUB. In addition, the semiconductor substrate PSUB is provided below the erase control circuit ERC.
Other predetermined number of bonding pads PA along the lower side
Ds are arranged in rows, and an erase voltage supply bonding pad VPP for inputting the erase voltage VPP to the flash memory is arranged at the right end thereof. Source switch S
On the further right side of S, the erase voltage VPP, which is formed of a predetermined metal wiring layer and is input via the erase voltage supply bonding pad VPP, is applied to the erase gates EG0 to EG31 of the source switch SS along the right side of the semiconductor substrate PSUB. The erase voltage supply wiring SVP to be transmitted is arranged.

As is well known, the erase voltage supply wiring SVP made of a metal wiring layer has a predetermined distributed resistance according to its wiring width and wiring thickness. Therefore, as shown in FIG. 6, wiring resistors RS0 to RS31 corresponding to the wiring length are coupled between the erasing voltage supply bonding pad VPP and the erasing gates EG0 to EG31 of the source switch SS. The potential drop of the erase voltage VPP supplied to the erase gates EG0 to EG31 is different due to the voltage drop of the wiring resistance.

To deal with this, in the flash memory of this embodiment, the erase voltage supply bonding pad VPP and each erase gate are provided between each branch point of the erase voltage supply wiring SVP and the corresponding erase gate EG1 to EG31. Smoothing resistors R1 to R31 are provided to equalize the resistance values between and. That is, the sum of the wiring resistances RS0 to RS31 between the erase voltage supply bonding pad VPP and the erase gates EG0 to EG31 is ΣRS, respectively.
In the case of 0 to ΣRS31, a smoothing resistor R1 of R1≅ΣRS0−ΣRS1 is provided between the erase gate EG1 and the corresponding branch point of the erase voltage supply wiring SVP. Similarly, the erase gate E
A smoothing resistor R2 of R2≈ΣRS0−ΣRS2 is provided between G2 and the corresponding branch point of the erase voltage supply wiring SVP, and the qth erase gate E is provided.
A smoothing resistor Rq of Rq≈ΣRS0−ΣRSq is provided between Gq and the corresponding branch point of the erase voltage supply wiring SVP.

As a result, the resistance value between the erase gates EG0 to EG31 and the erase voltage supply bonding pad VPP is substantially equalized, and the potential of the erase voltage VPP supplied to each erase gate is substantially equalized. In the flash memory of this embodiment, although not particularly limited, between the erase voltage supply bonding pad VPP and the erase gate EG31 arranged closest to the erase voltage supply bonding pad VPP in order to correspond to the algorithm of the all erase mode described later. Of the erase gate E and the other erase gate E
The resistance value between G30 and EG0 is set to increase little by little.

On the other hand, in the full erase mode by the erase control circuit ERC of the flash memory of this embodiment, as shown in FIG. 7, first, in step ST1, all the memory cells constituting the memory blocks MB0 to MB31 are logically "logic". It starts from pre-write to write data of "0". This pre-writing is performed to unify the threshold voltages of all the memory cells before erasing, so that the changing tendency of the threshold voltage of each memory cell due to the supply of the erase pulse is made uniform. Is.

Next, in step ST2, the block number, that is, the initial value BN of the block counter is set to 31 which specifies the memory block MB31 closest to the erase voltage supply bonding pad VPP.
At T3, the in-block address, that is, the initial value AD of the address counter is set to 0 which specifies the head address. As a result, in step ST4, the address 0 of the memory block MB31, that is, the X address signal EX.
0-EXi and Y address signals EY0-EYj are subjected to the verify read of the memory cells corresponding to the address where all the bits are logic "0", and in step ST5, the erase determination based on the read data is performed. Then, when the read data remains the logical "0",
It is determined that the selected memory cell is not in the erased state, and the erase pulse is supplied in step ST6. The erase pulse is supplied in step ST6
All memory blocks MB0 to MB0 whose erase operation is not completed
MB31, that is, the erase gates EG0 to EG31 are simultaneously performed.

The verify-read data is logic "1" by repeatedly supplying a predetermined erase pulse.
When it changes to, it is determined that the selected memory cell is in the erased state. Therefore, in step ST7, it is determined whether or not it is the final address. If it is not the final address, the address counter AD is counted up in step ST8, and the same erase operation is performed on the memory cell at the next address of the memory block MB31. The action is taken.

When it is determined in step ST7 that it is the final address of the memory block MB31, it is determined in step ST9 whether the block number BN is the final block number 0 corresponding to the last memory block MB0. If the final block number is not 0, in step ST10, the block counter B
N is counted down, and the next memory block MB30
A similar erase operation for is started. Further, in step ST11, the supply of the erase pulse in step ST6 to the memory block MB31 which has already been erased is selectively stopped, whereby the threshold voltage of the memory cells constituting the memory block MB31 becomes lower than necessary. Can be prevented.

Hereinafter, in step ST9, step ST3 is performed until the block number BN becomes the final block number 0.
The erase operation of step ST11 is repeated, and when the erase operation of all the memory cells forming the memory block MB0 is completed, the series of all erase modes is completed.

As described above, in the flash memory of this embodiment, the resistance value between the erase voltage supply bonding pad VPP and the erase gate EG31 arranged closest to the erase voltage supply bonding pad VPP is minimized although there is a slight difference. Thus, the resistance value between the erasing voltage supply bonding pad VPP and the other erasing gates EG30 to EG0 is set to increase little by little. In the algorithm of FIG. 7, the erase voltage supply bonding pad V is used.
Erase determination is performed in order from the memory block MB31 arranged closest to PP, in other words, the resistance value between the pad and the erase voltage supply bonding pad VPP is set to the smallest and the erase operation of the memory cell progresses fastest. Be seen. Therefore, as shown in FIG. 8, the distribution of the threshold voltage after erasing of the memory cell is arranged farthest from the memory block MB31 arranged closest to the erase voltage supply bonding pad VPP. Even the difference with the memory block MB0 is reduced, which reduces erase variations. As a result, the operation margin on the minimum power supply voltage side of the flash memory is expanded, and the access time is accelerated.

By applying the present invention to a semiconductor memory device such as a flash memory having a built-in erase control circuit for the full erase mode as shown in the above embodiment, the following effects can be obtained. To be That is, (1) a predetermined erase voltage is applied to a plurality of memory blocks formed by dividing a memory array and a common-coupled source of a plurality of memory cells that are provided corresponding to these memory blocks and configure the corresponding memory blocks. In a block erase type flash memory or the like, which includes a source switch including a plurality of erase gates selectively transmitting, and an erase control circuit for collectively erasing information held in all memory cells,
By providing a predetermined smoothing resistor between each branch point of the erase voltage supply wiring that transmits the erase voltage input through the erase voltage supply bonding pad to the plurality of erase gates and the corresponding erase gate, The resistance value between the erase voltage supply bonding pad and each erase gate can be made substantially uniform, and the potential of the erase voltage supplied to each erase gate can be made substantially uniform.

(2) In the above item (1), erase determination in the all erase mode is performed in order from the memory block arranged closest to the erase voltage supply bonding pad, so that the all erase mode is supplied. The number of erase pulses should be reduced in order from the memory block arranged closest to the erase voltage supply bonding pad, in other words, from the memory block having the smallest resistance value to the erase voltage supply bonding pad. The effect of being able to do is obtained. (3) According to the above items (1) and (2), even if the capacity and the size of the flash memory are increased and the chip is enlarged, the variation in the threshold voltage between blocks after the memory cell is erased is increased. It is possible to obtain the effect of reducing (4) By the above items (1) to (3), the operation margin on the minimum power supply voltage side of the flash memory is expanded,
It is possible to obtain the effect that the access time can be accelerated.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, the number of divisions of the memory array MARY, that is, the number of memory blocks installed can be set arbitrarily and X
A plurality of peripheral parts such as the address decoder XD and the Y address decoder YD can be provided corresponding to a predetermined number of memory blocks, that is, memory mats. The data input / output terminals IO0 to IO7 can be dedicated as data input terminals or data output terminals, and the number of bits of stored data that can be input to or output from the flash memory is 8 in particular.
It is not mandatory to be in bit units. further,
Various embodiments can be adopted for the block configuration of the flash memory, the combination of the activation control signal and the address signal, the polarity and absolute value of each power supply voltage, and the like.

In FIG. 2, the memory array MARY is
It may include a predetermined number of redundant word lines and redundant data lines. In addition, the switch MOS that constitutes the Y switch YS
The FET may be constituted by a P-channel MOSFET, a P-channel MOSFET and an N-channel MOSFET.
A complementary switch formed by combining The selection and non-selection levels of the word lines W0 to Wm, the data lines B0 to Bn, and the source lines S0 to S31 are not restricted by this embodiment, and the erase gates EG0 to EG31 are not restricted.
The specific circuit configuration of can also adopt various embodiments. In FIG. 3, the specific device structure of the two-layer gate structure cell is not restricted by this embodiment. Further, in FIG. 4, the logic levels of the retained information in the memory cells after erasing and after programming can be set interchangeably,
One or both of the threshold voltages of the memory cells can be set to a negative potential.

In FIG. 5, memory blocks MB0 to MB
B31 can be arranged in reverse order to the erase voltage supply bonding pad VPP. The arrangement position of the erase voltage supply bonding pad VPP can be set arbitrarily, and the specific substrate arrangement of the flash memory is not restricted by this embodiment. In FIG. 6, smoothing resistors R1 to R1 provided corresponding to the erase gates EG1 to EG31, respectively.
The value of R31 is the bonding pad VP for supplying the erase voltage.
The resistance value between P and each erase gate may be set to completely match, or the potential of the erase voltage supplied to each erase gate may be completely matched in consideration of the current when the erase voltage is supplied. You may set so that it may be done. On the other hand, the erase voltage supply bonding pad VPP and the erase gates EG0 to EG3
When decreasing the resistance value between 1 and 1 in the reverse order, it is necessary to switch the order of the erase determination in FIG. Furthermore, the measure by the smoothing resistor in FIG. 6 can be independently implemented without the measure by the algorithm in FIG. 7, and vice versa.

In the above description, the case where the invention made by the present inventor is mainly applied to the flash memory having the erase control circuit which is the field of application as the background has been described, but the invention is not limited thereto. For example, it can be applied to a similar flash memory incorporated in a single-chip microcomputer or the like, a gate array integrated circuit incorporating the flash memory, or the like. The present invention can be widely applied to a semiconductor memory device including at least an erase control circuit for all erase modes, and devices and systems including such a semiconductor memory device.

[0055]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, a predetermined erase voltage is selectively applied to a plurality of memory blocks formed by dividing a memory array and a common-coupled source of a plurality of memory cells provided corresponding to these memory blocks and forming the corresponding memory blocks. In a block erase type flash memory, etc., which has a source switch including a plurality of erase gates for transmitting to the memory and an erase control circuit for collectively erasing information held in all memory cells, input through an erase voltage supply bonding pad The smoothing resistor for equalizing the resistance value is provided between each branch point of the erase voltage supply wiring that transmits the erase voltage to be erased to a plurality of erase gates and the corresponding erase gate. A memory block that is placed close to the bonding pad for supplying the erase voltage for the erase determination in the erase mode. Even if the flash memory has a large capacity and a large scale and the chip becomes large, the potential of the erase voltage supplied to the commonly connected sources of the memory cells forming each memory block is The number of erase pulses supplied in the all erase mode can be made substantially uniform, and the number of erase pulses can be sequentially reduced from the memory block arranged near the erase voltage supply bonding pad. This allows
Since variation in threshold voltage between blocks after erasing in the memory cell full erase mode can be reduced, it is possible to expand the operation margin on the minimum power supply voltage side of the flash memory and accelerate the access time. it can.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a flash memory to which the present invention is applied.

2 is a partial circuit diagram showing an embodiment of a memory array and its peripheral portion included in the flash memory of FIG.

3 is a cross-sectional structural view showing an example of a two-layer gate structure cell that constitutes the memory array of FIG.

4 is a characteristic diagram showing an example for explaining the relationship between the gate-source voltage and the drain current of the two-layer gate structure cell of FIG.

5 is a board layout diagram showing an embodiment of the flash memory of FIG. 1. FIG.

6 is an equivalent circuit diagram of an erase voltage supply path of the flash memory of FIG.

7 is a process flow chart showing an embodiment of an all erase mode by an erase control circuit of the flash memory of FIG. 1. FIG.

8 is a distribution characteristic diagram showing an example of a threshold voltage after erasing of a two-layer gate structure cell that constitutes the memory array of the flash memory of FIG. 1. FIG.

FIG. 9 is a distribution characteristic diagram showing an example of a threshold voltage after erasing of a two-layer gate structure cell that constitutes a memory array of a flash memory developed by the inventors of the present application prior to the present invention.

10 is an equivalent circuit diagram showing an example of an erase voltage supply path of the flash memory of FIG.

FIG. 11 is a process flow chart showing an example of an all erase mode by the erase control circuit of the flash memory of FIG. 9;

[Explanation of symbols]

MARY ... Memory array, MB0-MB31 ...
Memory block, XD ... X address decoder, XB
... X address buffer, YS ... Y switch, Y
D ... Y address decoder, SS ... source switch, YB ... Y address buffer, WA ... write amplifier, SA ... sense amplifier, IB ... data input buffer, OB ... data Output buffer, ERC
..Erase control circuit, TC ... Timing control circuit M
C ... Memory cell (two-layer gate structure cell), W0 to W
m: word line, B0 to Bn: data line, S0
S31 ... Source line, YS0 to YSp ... Bit line selection signal, C0 to C7 ... Common data line, EG0 to E
G31 ... Erase gate, P1 ... P channel MO
SFET, N1 to N2 ... N-channel MOSFE
T. PSUB ... P-type semiconductor substrate, FG ... Floating gate, CG ... Control gate, IS
1 to IS2 ... Insulating film, N ⁺ (ND1 to ND2) ...
· N-type high concentration diffusion layer, N ^- · · · N-type low concentration diffusion layer, P
^- ··· P-type low-concentration diffusion layer. VPP ... Erase voltage supply bonding pad (erase voltage), PAD ... Other bonding pad, SVP ... Erase voltage supply wiring. RS0 to RS31 ... Wiring resistance, R1 to R31.
..Smoothing resistance

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazuto Izawa 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Hitachi Ltd. Semiconductor Division (72) Inventor Yasuki Mori Moroyama-cho, Iruma-gun, Saitama Prefecture Asahidai No. 15 Inside Hitachi East Semiconductor Co., Ltd. (72) Inventor Takeshi Wada 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Inside Hitachi Semiconductor Business Division, Ltd.

Claims (3)

[Claims] 1. A memory array in which non-volatile memory cells of a two-layer gate structure type are arranged in a lattice, a plurality of memory blocks formed by dividing the memory array, and a memory block provided corresponding to the memory blocks. A source switch including a plurality of erase gates for selectively transmitting a predetermined erase voltage to commonly connected sources of a predetermined number of memory cells forming a corresponding memory block, and an erase voltage supply to which the erase voltage is input Between a bonding pad, an erase voltage supply wiring for transmitting an erase voltage input from the erase voltage supply bonding pad to the plurality of erase gates, and the erase gate corresponding to each branch point of the erase voltage supply wiring. 2. A semiconductor memory device comprising: a smoothing resistor provided in each of the. 2. The semiconductor memory device sequentially determines the erased state of each memory block while selectively supplying the pulsed erase voltage to the commonly connected sources of the memory cells forming the plurality of memory blocks. The erase control circuit includes an erase control circuit that erases all memory cells by sequentially stopping the supply of the erase voltage from the erased memory block. 2. The semiconductor memory device according to claim 1, wherein the steps are sequentially performed from a memory block adjacent to an erase voltage supply bonding pad. 3. A memory array in which non-volatile memory cells of a two-layer gate structure type are arranged in a grid, a plurality of memory blocks into which the memory array is divided, and a memory block provided corresponding to the memory blocks. A source switch including a plurality of erase gates for selectively transmitting a predetermined erase voltage to commonly connected sources of a predetermined number of memory cells forming a corresponding memory block, and an erase voltage supply to which the erase voltage is input A memory that is in the erased state by sequentially determining the erased state of each memory block while selectively supplying the pulsed erase voltage to the bonding pad and the sources commonly connected to the memory cells that form the plurality of memory blocks. An erase control circuit that erases all memory cells by stopping the supply of erase voltage in order from the block; A semiconductor memory device, wherein the erase state is judged by an erase control circuit in order from a memory block adjacent to the erase voltage supply bonding pad.