JPH06325500A - Information reproducing device - Google Patents

Abstract

PURPOSE:To reduce a cost by sampling a regenerative signal with a clock signal obtained in a voltage control means and forming a reproducing clock for detecting regenerative data based on the clock signal. CONSTITUTION:The output of a D/A converter 13 is outputted to a VCO as a signal according to a phase difference between the regenerative signal and the clock signal, similar to the phase comparison signal of a phase comparator in an analog circuit. In the VCO, an oscillation frequency is controlled according to an inputted level difference signal, and a sampling clock for sampling the regenerative signal is outputted. Further, the sampling clock is frequency dimultiplexed to double by a frequency divider 9, and a regenerative clock is generated. The obtained regenerative clock is outputted to a data detection circuit 4, and the regenerative data 5 are detected using the regenerative clock in the data detection circuit 4. In such a case, the regenerative clock is extracted without necessitating the sampling of ten times or above of a data clock, and thus, a cost is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information reproducing apparatus for reproducing information recorded on an information recording medium.

[0002]

2. Description of the Related Art Conventionally, when reproducing information in an information recording / reproducing apparatus, a reproduced signal read from a recording medium is waveform-equalized in analog and then binarized. Then, after the binarization, the PLL is applied to extract the reproduction clock, and the reproduction data is detected using the obtained reproduction clock. FIG. 6 is a block diagram showing an example of such a data reproducing device, and FIG. 7 is a signal waveform diagram showing signals of respective parts of FIG. The conventional data reproducing apparatus will be described below with reference to FIGS. 6 and 7. Reference numeral 101 in the figure denotes a reproduction signal read from an information recording medium such as an optical disk, which is waveform-equalized by the waveform equalization circuit 102 as described above and then binarized by a predetermined slice level by the binarization circuit 103. Valued. Figure 7
(A) shows a reproduction signal read from the recording medium, which is 2 at a predetermined slice level after waveform equalization.
When binarized, a binarized signal as shown in FIG. 7B is generated.

The binarized signal is input to the PLL circuit 108, where the phase is compared with that of the binarized signal to obtain the signal shown in FIG.
The reproduced clock 109 as shown in (c) is extracted.
Further, the data detection circuit 104 generates the reproduction data 105 by detecting the binarized signal with the reproduction clock. The PLL circuit 108 is controlled by a control signal sent from a main control circuit (not shown) so that the reproduction clock is locked to the reference clock before the reproduction signal is input. FIG. 8 is a block diagram showing a concrete configuration of the PLL circuit 108, and 110 is a control signal 1
It is a changeover switch controlled by 07. When the reproduction signal 101 is not input, that is, when the operation mode of the device is not the reproduction mode, the changeover switch 110 is connected to the b side by the control signal 107, and the PLL
By inputting the reference clock 106 to the phase comparator 111 of the circuit 108, the reproduction clock 109 becomes the reference clock 1
It is locked at 06. Then, when the operation mode becomes the reproduction mode, the changeover switch 110 is connected to the a side by the control signal 107, and the binarized signal is input to the phase comparator 111.

The phase comparator 111 compares the phase of the reproduced clock 109 shown in FIG. 7C with the phase of the binarized signal.
As shown in (d), a phase comparison signal indicating the phase difference between the two signals is generated. The obtained phase comparison signal is output to the charge pump circuit 112 and converted into a signal having a voltage value proportional to the phase difference as shown in FIG. The output signal of the charge pump circuit 112 is VCO (Voltage Cont
Roll Oscilater) 113, and the reproduced clock 109 is extracted by changing the frequency in proportion to the voltage of the charge pump output. Thus PLL
The circuit 108 generates the reproduced clock 109, and the data detection circuit 104 generates the reproduced data using the reproduced clock 109 as described above.

[0005]

In the conventional information recording / reproducing apparatus, when the information recording medium is exchanged or the information transfer rate is changed, the quality and frequency characteristics of the reproduced signal are changed, so that the waveform etc. The characteristics of the digitized circuit must also be changed. However, in the above-mentioned conventional data reproducing apparatus, since the reproduced signal is equalized in waveform in an analog manner, there is a problem that the circuit configuration becomes complicated to change the characteristic of the waveform equalization and the cost of the apparatus is increased. Therefore, as a solution to this problem, for example, a method of A / D converting a reproduction signal and detecting reproduction data or a reproduction clock by digital signal processing has been considered, but in the conventional reproduction clock extraction method, When the phases are compared digitally, a sampling clock that is 10 times or more the data clock is required, and thus a high-speed A / D converter is required, which causes a problem of cost increase.

The present invention has been made in order to solve such a problem, and enables the reproduction clock to be extracted without the need for a high-speed A / D converter, whereby the waveform equalization characteristic of the reproduction signal is improved. It is an object of the present invention to provide an information reproducing apparatus which can be easily changed by digital signal processing.

[0007]

SUMMARY OF THE INVENTION An object of the present invention is to provide an information reproducing apparatus which digitizes a reproduced signal read from an information recording medium, performs signal processing to detect reproduced data, and samples the reproduced signal. Edge detection means for detecting that the digital data obtained by the detection is within a predetermined range with respect to the slice level and an edge with respect to the slice level of the reproduction signal, and the edge detected by this edge detection means Level difference detecting means for detecting the difference between the slice level and the digital data at the position, and the voltage controlled oscillating means for controlling the oscillation frequency of the clock signal according to the level difference detected by the level difference detecting means. The reproduction signal is sampled by the clock signal obtained by the voltage controlled oscillation means, and the clock signal It is achieved by the information reproducing apparatus characterized by creating a reproduction clock for detecting the reproduced data on the basis.

[0008]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the information reproducing apparatus of the present invention. In FIG. 1, reference numeral 2 is an A / D converter for sampling the reproduction signal 1 read from the information recording medium at a predetermined sampling point and converting it into a digital signal. The reproduction signal 1 is a signal optically reproduced from an information recording medium such as an optical disk (not shown), and the A / D converter 2 converts an analog signal into a digital data signal sequence based on a reference voltage instructed by the CPU 11. To be done. Reference numeral 3 is a waveform equalizing circuit composed of a digital filter, and 4 is a data detecting circuit for comparing the data of the waveform equalizing circuit 3 with a slice level given from the CPU 11 to detect the reproduced data 5. C
The PU 11 controls the entire apparatus, and as described above, A
The reference voltage is output to the D / D converter 2, the filter coefficient is output to the waveform equalization circuit 3, and the slice level is output to the data detection circuit 4, thereby controlling the AGC (Auto Gain Controll) characteristic, the waveform equalization characteristic, and the data detection characteristic. To be done. 8 is a PLL circuit for extracting a sampling clock, and 9 is P
It is a frequency divider for dividing the sampling clock of the LL circuit 8 to generate the reproduction clock 10. PLL circuit 8
A reference clock 6 and a control signal 7 are sent from a main control circuit (not shown).

FIG. 2 is a block diagram showing a concrete configuration of the PLL circuit 8. In FIG. 2, reference numeral 12 is a level detection circuit having a phase comparison function, which detects an edge of the sampled reproduction signal data with respect to the slice level and a phase difference of the reproduction signal with respect to the sampling clock. 13 is a level detection circuit 1
A D / A converter for converting the output of 2 into an analog signal, and 16 is a changeover switch controlled by the control signal 7. Further, 14 is a phase comparator, 15 is a charge pump circuit, 17 is a VCO (voltage controlled oscillator), and these are the same as those shown in FIG.

Next, the operation of the above embodiment will be described with reference to the time chart of FIG. First, when the reproduction signal is not input, that is, when the operation mode of the device is not the reproduction mode, the changeover switch 16 is connected to the b side by the control signal 7. Therefore, at this time, the reference clock 6 is input to the phase comparator 14, and the reproduction clock is locked to the reference clock 6 as in the conventional case. On the other hand, when the operation mode of the device becomes the reproduction mode, the changeover switch 16 is switched to the a side by the control signal 7. As a result, as shown in FIG. 3A, the reproduction signal waveform-equalized by the waveform equalization circuit 3 is sampled at the sampling points indicated by black circles and taken into the level detection circuit 12 as a digital data string. The reproduced signal is sampled by the sampling clock shown in FIG.

In the level detection circuit 12, as shown in FIG. 3A, a predetermined voltage range V _{1 to} V ₂ is determined with respect to the slice level of the reproduction signal, and the reproduction signal is in this voltage range. At times, an edge with respect to the slice level of the reproduction signal is detected. Further, the level detection circuit 12 detects the difference between the reproduction signal data and the slice level at the detected edge position, and the obtained signal is sent to the D / A converter 13 as a level difference detection signal as shown in FIG. Is output. In the D / A converter 13, the output of the level detection circuit 12 is converted into an analog signal, and as shown in FIG. 3D, the changeover switch 16 is converted into an analog signal corresponding to the level difference.
Is output to the VCO 17 via.

In this case, whether the edge with respect to the slice level of the reproduced signal is the rising edge or the falling edge from the sampling clocks before and after the output signal of the level difference detection circuit 12 of FIG. It is determined whether the phase is ahead of or behind the sampling clock, and D /
The output of the A converter 13 is inverted. That is, the output of the D / A converter 13 is output to the VCO 17 as a signal corresponding to the phase difference between the reproduction signal and the clock signal, like the phase comparison signal of the phase comparator of the analog circuit. The VCO 17 controls the oscillation frequency according to the input level difference signal and outputs it as a sampling clock for sampling the reproduction signal. The sampling clock is doubled by the frequency divider 9 to generate a reproduction clock as shown in FIG. The obtained reproduction clock is output to the data detection circuit 4, and the data detection circuit 4 detects the reproduction data 5 using the reproduction clock.

In this embodiment, when the digital data of the sampled reproduction signal is within a predetermined voltage range predetermined with respect to the slice level, the edge with respect to the slice level of the reproduction signal is detected and the edge position is detected. By detecting the level difference between the digital data and the slice level in the above, and controlling the frequency of the VCO according to the level difference to control the frequency of the sampling clock, the reproduced signal is digitally compared with the phase difference of the sampling clock. Thus, it is possible to provide a PLL function by digital signal processing, which is completely equivalent to the analog PLL circuit. Therefore, when the signal processing of information reproduction is digitized, the reproduction clock can be extracted without requiring a sampling clock that is 10 times or more the data clock, and the information reproduction is digitized without a high-speed A / D converter. be able to. In particular, when the waveform equalization circuit is configured by a digital circuit and the waveform equalization characteristic is changed according to the exchange of the information recording medium or the change of the information transfer rate, the high speed A / D converter is not required as described above. To be
Digitization is possible without increasing costs. Further, when the characteristics of the waveform equalization circuit are changed by this digitization, the circuit configuration can be greatly simplified as compared with the analog circuit. Further, in this embodiment, data can be sampled with the clock signal having a frequency twice as high as the data clock.

FIG. 4 is a block diagram showing another embodiment of the information reproducing apparatus of the present invention. In FIG. 4, the same parts as those in the embodiment of FIG. In this embodiment, NRZI conversion is used as the recording code. In the case of NRZI conversion, "1" of the recording data corresponds to the position of the edge, so that the position may be detected. Therefore, also in this case, as in the embodiment of FIGS. The edge position with respect to the slice level is detected. However, in this embodiment, since the sampling clock and the reproduction clock from the data coincide with each other, the frequency of the sampling clock can be further lowered.

FIG. 5A shows a reproduced signal of the waveform equalizing circuit 3,
FIG. 5B shows a sampling clock, and the reproduction signal is sampled by the sampling clock and taken into the level detection circuit 12 of the PLL circuit 8 as digital data. Similar to the embodiment of FIG. 1, the level detection circuit 12 detects the edge of the reproduction signal with respect to the slice level when the reproduction signal is within the predetermined voltage range V ₁ -V ₂ . Further, the level detection circuit 12 detects the level difference between the reproduction signal level and the slice level at the edge position, and outputs the level difference detection signal to the D / A converter 13 as shown in FIG. 5C. . D / A converter 13
Then, as shown in FIG. 5D, the level difference detection signal is converted into an analog signal, and the output of the D / A converter 13 leads or lags the phase of the reproduction signal with respect to the sampling clock, as in the embodiment of FIG. Will be inverted accordingly. VCO17
Then, the frequency of the clock signal is controlled according to the output of the D / A converter 13, and is output as a sampling clock for sampling the reproduction signal. Since the sampling clock and the reproduction clock match here, it is not necessary to divide the frequency, and the sampling clock of the VCO 17 is used as it is as the reproduction clock in the data detection circuit 4.
Is output to. As described above, also in this embodiment, the PLL can be applied by the digital signal processing in exactly the same manner as the embodiment of FIG. 1, and the reproduction clock can be extracted without the need for a high-speed D / A converter.

[0016]

As described above, according to the present invention, it is possible to digitally compare the phase of the reproduction signal and the phase of the sampling clock and to have the function of the PLL circuit. The reproduced clock can be extracted without requiring more than double the clock. Therefore, when the signal processing for information reproduction is digitized, a high-speed A / D converter is not required, and when the waveform equalization circuit is configured by a digital circuit, the configuration is simpler than that of the analog circuit, and the cost is low. There is an effect that the waveform equalization characteristics can be changed without becoming high.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an information reproducing apparatus of the present invention.

FIG. 2 is a block diagram showing a specific configuration of the PLL circuit of FIG.

FIG. 3 is a time chart showing the operation of the embodiment of FIG.

FIG. 4 is a block diagram showing another embodiment of the present invention.

5 is a time chart showing the operation of the embodiment of FIG.

FIG. 6 is a block diagram showing a conventional information reproducing apparatus.

7 is a time chart showing the operation of the apparatus of FIG.

8 is a block diagram showing the PLL circuit of FIG. 6 in detail.

[Explanation of symbols]

 2 A / D converter 3 Waveform equalization circuit 4 Data detection circuit 8 PLL circuit 9 Frequency divider 11 CPU 12 Level detection circuit 13 D / A converter 14 Phase comparator 15 Charge pump circuit 16 Changeover switch 17 VCO (voltage control Oscillator)

Claims (3)

[Claims] 1. An information reproducing apparatus for digitizing a reproduced signal read from an information recording medium to perform signal processing to detect reproduced data, wherein digital data obtained by sampling the reproduced signal is slice level. With respect to the slice level of the reproduction signal by detecting that it is within a predetermined range, digital data at the position of the edge detected by this edge detection means and the slice level And a voltage control oscillation means for controlling the oscillation frequency of the clock signal according to the level difference detected by the level difference detection means. The reproduction signal is sampled by the obtained clock signal, and the reproduction data is detected based on the clock signal. An information reproducing apparatus characterized by generating a reproducing clock for the reproduction. 2. The reproducing clock is created as the reproducing clock by dividing the clock signal or by directly using the clock signal.
Information reproducing device. 3. The information reproducing apparatus according to claim 1, wherein the frequency of the clock signal created for sampling is not more than twice the data clock of the reproduced data.