JPH06325285A - Pulse receiving circuit - Google Patents
Pulse receiving circuitInfo
- Publication number
- JPH06325285A JPH06325285A JP5109208A JP10920893A JPH06325285A JP H06325285 A JPH06325285 A JP H06325285A JP 5109208 A JP5109208 A JP 5109208A JP 10920893 A JP10920893 A JP 10920893A JP H06325285 A JPH06325285 A JP H06325285A
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- pulse
- input
- resistor
- input pulse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
Landscapes
- Details Of Flowmeters (AREA)
- Arrangements For Transmission Of Measured Signals (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は電子式水道メータ等から
発信されるオン・オフパルスを受信するパルス受信回路
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse receiving circuit for receiving on / off pulses transmitted from an electronic water meter or the like.
【０００２】[0002]
【従来の技術】電子式水道メータ等では、図４に示すよ
うに、メータ１に内蔵したオープンコレクタ接続のトラ
ンジスタ２からのオン・オフパルスを２芯のケーブル３
で受信器４に伝送する。オン・オフパルスの発信手段と
しては、トランジスタ２のオープンコレクタ接続の代り
に無電圧接点が用いられることもある。2. Description of the Related Art In an electronic water meter or the like, as shown in FIG. 4, an on / off pulse from an open collector connection transistor 2 built in a meter 1 is supplied to a two-core cable 3.
Is transmitted to the receiver 4. A non-voltage contact may be used in place of the open collector connection of the transistor 2 as the on / off pulse transmitting means.
【０００３】受信器４は入力端子５、６の一方５が電源
８の一端に、他方６がプルアップ抵抗７を介して電源８
の他端に接続されている。９は受信パルスを波形整形す
る増幅器である。In the receiver 4, one of the input terminals 5 and 6 is connected to one end of a power supply 8 and the other 6 is connected to a power supply 8 via a pull-up resistor 7.
Is connected to the other end of. Reference numeral 9 is an amplifier for shaping the received pulse.
【０００４】トランジスタ２がオンのときはケーブル３
の線間がトランジスタ２で短絡されるため、入力端子
５、６間の電圧はゼロになる。トランジスタ２がオフの
ときは入力端子５、６間の電圧は電源８の電圧Ｖ迄上昇
する。Cable 3 when transistor 2 is on
The voltage between the input terminals 5 and 6 becomes zero because the line between these lines is short-circuited by the transistor 2. When the transistor 2 is off, the voltage between the input terminals 5 and 6 rises to the voltage V of the power supply 8.
【０００５】トランジスタ２がオンのときに抵抗７に流
れる電流を小さくして、電池の消耗を少なくするよう
に、抵抗７の抵抗値Ｒをなるべく大きく定めるようにし
ている。The resistance value R of the resistor 7 is set as large as possible so that the current flowing through the resistor 7 is reduced when the transistor 2 is turned on and the consumption of the battery is reduced.
【０００６】[0006]
【発明が解決しようとする課題】前記従来の技術では、
メータ１と受信器４との距離が大きくなってケーブル３
の線間容量Ｃが大きくなると、時定数Ｃ・Ｒが大きくな
って、周波数が大きいオン・オフパルスを受信できなく
なるという問題点があった。SUMMARY OF THE INVENTION In the above conventional technique,
As the distance between the meter 1 and the receiver 4 increases, the cable 3
When the line capacitance C of 2 becomes large, the time constant C / R becomes large, and there is a problem that it is not possible to receive an ON / OFF pulse having a large frequency.
【０００７】もっとも、このとき、プルアップ抵抗７の
抵抗値Ｒを小さくすると、高い周波数のオン・オフパル
スでも受信できるようになるが、プルアップ抵抗７を流
れる電流が増大して、電源８の電池の消耗が早くなると
いう別の問題点が生じる。At this time, however, if the resistance value R of the pull-up resistor 7 is reduced, even a high-frequency on / off pulse can be received, but the current flowing through the pull-up resistor 7 increases, and the battery of the power source 8 increases. Another problem arises in that the consumption of water becomes faster.
【０００８】図５に、受信器４の入力端子５、６間に受
信するパルス信号波形を示す。オン・オフパルスの周波
数が低いとき、つまり、オン・オフパルスの周期Ｔが同
図（ａ）のように大きいときは、トランジスタ２がオフ
のときにパルス信号は“Ｈ”レベルが電源８の電圧Ｖま
で上昇する。しかし、オン・オフパルスの周期Ｔが同図
（ｂ）のように小さくなると（つまり周波数が高くなる
と）、トランジスタ２がオフの間にパルス信号の“Ｈ”
レベルは電源８の電圧Ｖまで到達できない。FIG. 5 shows a pulse signal waveform received between the input terminals 5 and 6 of the receiver 4. When the frequency of the on / off pulse is low, that is, when the cycle T of the on / off pulse is large as shown in FIG. 9A, the pulse signal is “H” level when the transistor 2 is off. Rise to. However, when the cycle T of the on / off pulse becomes small as shown in FIG. 6B (that is, the frequency becomes high), the pulse signal is "H" while the transistor 2 is off.
The level cannot reach the voltage V of the power supply 8.
【０００９】これは、トランジスタ２がオフのときの入
力端子５、６間の電圧が上昇するのに、時定数Ｃ・Ｒに
比例した充電時間で線間容量Ｃを充電する必要があるか
らである。This is because it is necessary to charge the line capacitance C in a charging time proportional to the time constant C · R even when the voltage between the input terminals 5 and 6 rises when the transistor 2 is off. is there.
【００１０】図５（ｂ）に示す不都合を無くすには、前
述のプルアップ抵抗７の抵抗値Ｒを小さくすればよい
が、電源８に電池を用いることが多いこの種の受信器で
は、電池寿命が短かくなってしまうという問題点が生じ
る。In order to eliminate the inconvenience shown in FIG. 5 (b), the resistance value R of the pull-up resistor 7 may be reduced, but in this type of receiver that often uses a battery for the power source 8, a battery is used. There is a problem that the life is shortened.
【００１１】又、水道メータでは、水の流れが止まった
ときに、トランジスタ２がオンのままになることがある
ため、単純に抵抗値Ｒを小さくするのは、消費電流的に
問題が大きい。Further, in the water meter, when the flow of water is stopped, the transistor 2 may remain on. Therefore, simply reducing the resistance value R causes a large current consumption problem.
【００１２】更に又、水道メータは夜間等に停止してい
る時がかなりあって、羽根車が高速で回転しオン・オフ
パルスが高い周波数になるのは、極まれと考えてよい。
従って、そのときのために、抵抗値Ｒを小さくするのは
不合理でもある。Furthermore, it is extremely rare that the water meter is stopped at night, etc., and the impeller rotates at high speed and the on / off pulse has a high frequency.
Therefore, it is also unreasonable to reduce the resistance value R for that case.
【００１３】そこで、本発明は、長距離の伝送が高い周
波数迄可能で、かつ電池寿命への悪影響が小さいパルス
受信回路を提供することを目的とする。Therefore, an object of the present invention is to provide a pulse receiving circuit capable of long-distance transmission up to a high frequency and having a small adverse effect on battery life.
【００１４】[0014]
【課題を解決するための手段】前記目的を達成するため
に、請求項１の発明は、入力端子（５），（６）間にオ
ン・オフパルスを受信する受信器（４）において、一方
の入力端子（６）と電源（８）の一端との間に設けた抵
抗器（７Ａ）の抵抗値を入力パルスの周波数又は間隔に
応じて変更するように構成して、入力パルスの周波数が
大きくなるか又は間隔が小さくなると前記抵抗値を小さ
くするように定めた。In order to achieve the above-mentioned object, the invention of claim 1 provides a receiver (4) for receiving an on / off pulse between input terminals (5) and (6). The resistance value of the resistor (7A) provided between the input terminal (6) and one end of the power supply (8) is configured to be changed according to the frequency or the interval of the input pulse to increase the frequency of the input pulse. It is determined that the resistance value becomes smaller when the distance becomes shorter or the interval becomes smaller.
【００１５】請求項２の発明は、請求項１の発明におい
て、一方の入力端子（６）と電源（８）の一端に接続さ
れた第１の抵抗器（７Ｂ）と、入力パルスの周波数が一
定以上のとき又は入力パルスの間隔が一定以下のときに
信号を出す周波数検知部（１０）と、この周波数検知部
（１０）の信号で閉じるスイッチ（Ｓ1 ）と第２の抵抗
器（７ｃ）との直列回路（７Ｄ）とを具備し、この直列
回路（７Ｄ）を前記第１の抵抗器（７Ｂ）と並列に接続
したことを特徴とする。According to a second aspect of the invention, in the first aspect of the invention, the first resistor (7B) connected to one input terminal (6) and one end of the power source (8) and the frequency of the input pulse are A frequency detection unit (10) that outputs a signal when it is equal to or more than a certain value or when the interval between input pulses is less than a certain value, a switch (S 1 ) that is closed by the signal of the frequency detection unit (10), and a second resistor (7c). ) And a series circuit (7D), and the series circuit (7D) is connected in parallel with the first resistor (7B).
【００１６】又、請求項３の発明は、請求項１の発明に
おいて、一方の入力端子（６）と電源（８）の一端に接
続された第１と第２の抵抗器（７Ｅ）（７Ｆ）の直列回
路（７Ｇ）と、第１と第２の抵抗器（７Ｅ）（７Ｆ）の
うち何れか一方の抵抗器（７Ｆ）又は（７Ｅ）に並列に
接続したスイッチ（Ｓ2 ）と、入力パルスの周波数が一
定以上のとき又は入力パルスの間隔が一定以下のときに
前記スイッチ（Ｓ2 ）を閉じる周波数検知部（１０）と
を具備したことを特徴とする。According to a third aspect of the invention, in the first aspect of the invention, the first and second resistors (7E) (7F) connected to one input terminal (6) and one end of the power source (8). ) Series circuit (7G), and a switch (S 2 ) connected in parallel to any one resistor (7F) or (7E) of the first and second resistors (7E) (7F), And a frequency detector (10) for closing the switch (S 2 ) when the frequency of the input pulse is equal to or more than a certain value or when the interval of the input pulse is less than or equal to a certain value.
【００１７】[0017]
【作用】入力パルスの周波数が小さいとき又は間隔が大
きいときは、一方の入力端子と電源の一端の間に設けた
抵抗器の抵抗値が大きいままであり、この抵抗器に流れ
る電流が小さく保たれる。When the frequency of the input pulse is small or the interval is large, the resistance value of the resistor provided between one input terminal and one end of the power supply remains large, and the current flowing through this resistor is kept small. Be drunk
【００１８】入力パルスの周波数が大きくなるか又は間
隔が小さくなると、前記抵抗器の抵抗値が小さくなり、
入力パルスの変化に対応する。すなわち、メータとの間
の距離が長くても、高い周波数又は短い間隔の入力パル
スでも確実に受信する。As the frequency of the input pulse increases or the interval decreases, the resistance value of the resistor decreases,
It corresponds to the change of the input pulse. That is, even with a long distance from the meter, it is possible to reliably receive an input pulse having a high frequency or a short interval.
【００１９】[0019]
【実施例】図１は第１実施例で、１は電子式水道メー
タ、２はオープンコレクタ接続のトランジスタ、３は２
芯のケーブル、４は受信器、５、６は入力端子、７Ａは
抵抗器、８は電源電池、９は波形整形のための増幅器、
１０は入力パルスの周波数を監視して周波数が一定以上
になったとき又は入力パルスの間隔（周期）が一定以下
になったときに信号を出して前記抵抗器７Ａの抵抗値を
小さく変える周波数検知部で、それぞれ図示のように接
続されている。DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a first embodiment, 1 is an electronic water meter, 2 is an open collector connected transistor, and 3 is 2.
Core cable, 4 receiver, 5 and 6 input terminals, 7A resistor, 8 power battery, 9 amplifier for waveform shaping,
Reference numeral 10 is a frequency detector that monitors the frequency of the input pulse and outputs a signal when the frequency exceeds a certain level or when the interval (cycle) of the input pulse is less than a certain level to change the resistance value of the resistor 7A small. The parts are connected as shown.
【００２０】図２は、第２実施例で、一方の入力端子６
と電源電池８の一端に接続された第１の抵抗器７Ｂと、
入力パルスの周波数が一定以上のとき又は入力パルスの
間隔（周期）が一定以下のときに信号を出す周波数検知
部１０と、この周波数検知部１０の信号で閉じるスイッ
チＳ1 と第２の抵抗器７Ｃとの直列回路７Ｄとを具備
し、この直列回路７Ｄを第１の抵抗器７Ｂと並列に接続
してある。FIG. 2 shows a second embodiment of the present invention in which one input terminal 6
And a first resistor 7B connected to one end of the power supply battery 8,
When the frequency of the input pulse is equal to or higher than a certain value or when the interval (cycle) of the input pulse is equal to or less than a certain value, the frequency detection unit 10 and the switch S 1 and the second resistor which are closed by the signal of the frequency detection unit 10 7C and a series circuit 7D, and this series circuit 7D is connected in parallel with the first resistor 7B.
【００２１】図３は第３実施例で、一方の入力端子６と
電源電池８の一端に接続された第１と第２の抵抗器（７
Ｅ）（７Ｆ）のうち一方の抵抗器７Ｆに並列接続したス
イッチＳ2 と、入力パルスの周波数が一定以上のとき又
は入力パルスの間隔（周期）が一定以下のときに前記ス
イッチＳ2 を閉じる周波数検知部１０とを具備し、これ
らが図示のように接続されている。FIG. 3 shows a third embodiment, in which the first and second resistors (7) connected to one input terminal 6 and one end of the power supply battery 8 are connected.
E) A switch S 2 connected in parallel to one of the resistors 7F of (7F) and the switch S 2 is closed when the frequency of the input pulse is above a certain level or when the interval (cycle) of the input pulse is below a certain level. The frequency detector 10 is provided, and these are connected as shown in the figure.
【００２２】上記各実施例で、入力パルスの周波数が一
定以上になるか、入力パルスの間隔（周期）が一定以下
になると、周波数検知部１０がそのことを検出して、プ
ルアップ抵抗を小さい抵抗値に変更する。そのため受信
器の応答性（厳密にはケーブル３を含めた受信器の応答
性）が早くなる。In each of the above-described embodiments, when the frequency of the input pulse becomes equal to or higher than a certain value or the interval (cycle) of the input pulse becomes less than a certain value, the frequency detecting section 10 detects this and reduces the pull-up resistance. Change to resistance value. Therefore, the response of the receiver (strictly speaking, the response of the receiver including the cable 3) becomes faster.
【００２３】なお、上記各実施例において、波形整形用
の増幅器９は必ずしも必要ではない。この増幅器９がな
くて、入力端子６の信号を周波数検知部１０に直接入力
してもよい。又、実施例で、増幅器９の出力である流量
パルスは、図示されてないカウンタで積算され、積算値
は液晶等の表示器に表示される周知の方式で受信器４が
構成されている。In each of the above embodiments, the waveform shaping amplifier 9 is not always necessary. The signal at the input terminal 6 may be directly input to the frequency detection unit 10 without the amplifier 9. Further, in the embodiment, the flow rate pulse which is the output of the amplifier 9 is integrated by a counter (not shown), and the integrated value is displayed on a display such as a liquid crystal, etc., and the receiver 4 is constructed by a known method.
【００２４】上記各実施例で、入力パルスの周波数を検
出するには、一定時間の間に入力される入力パルスの数
を周波数検知部１０で計数し、その数が一定値を超えた
ときに周波数検知部１０からスイッチＳ1 ，Ｓ2 を閉じ
たり、抵抗器７Ａの抵抗値を小さく変える信号を出力す
る。又、周波数と周期とは逆比例の関係にあるので、周
波数検知部１０が、入力パルスの間隔（周期）を基準ク
ロックで測定し、間隔（周期）が一定以下になったらス
イッチＳ1 ，Ｓ2 を閉じたり、抵抗器７Ａの抵抗値を小
さく変える信号を出すようにしてもよい。In each of the above-described embodiments, the frequency of the input pulse is detected by counting the number of input pulses input during a fixed time by the frequency detection unit 10, and when the number exceeds a fixed value. The frequency detection unit 10 outputs a signal that closes the switches S 1 and S 2 or changes the resistance value of the resistor 7A small. Further, since the frequency and the cycle are in inverse proportion to each other, the frequency detection unit 10 measures the interval (cycle) of the input pulse with the reference clock, and when the interval (cycle) becomes less than a certain value, the switches S 1 , S 2 may be closed or a signal for changing the resistance value of the resistor 7A small may be output.
【００２５】更に又、入力パルスの周波数や間隔（周
期）の検出を、周波数検知部１０に代るマイクロコンピ
ュータで構成し、同様にソフトで実現してもよい。な
お、入力パルス周波数の大小の切り分け周波数は、プル
アップ抵抗の大きい方の抵抗値で十分受信可能の小さい
周波数に設定しておく。Further, the detection of the frequency or interval (cycle) of the input pulse may be realized by software, which is constituted by a microcomputer instead of the frequency detecting section 10. Note that the input pulse frequency division frequency is set to a frequency at which the resistance value with the larger pull-up resistance is sufficiently small for reception.
【００２６】又、メータは構造上、急にオン・オフパル
スの周波数が大きな値に変化することがないので、この
特性を本発明では有効に利用している。入力パルスの周
波数が一定以下に戻ると、周波数検知部１０がそれを検
出して、プルアップ抵抗の抵抗値はもとの大きな値に戻
る。Further, since the frequency of the on / off pulse does not suddenly change to a large value due to the structure of the meter, this characteristic is effectively utilized in the present invention. When the frequency of the input pulse returns below a certain level, the frequency detection unit 10 detects it and the resistance value of the pull-up resistor returns to the original large value.
【００２７】[0027]
【発明の効果】本発明のパルス受信回路は、上述のよう
に構成されているので、受信器の入力回路の消費電流を
抑えながら、長距離・高速パルスの受信が可能となり、
特に電池を電源とする受信器に利用すると電池容量を小
さくでき、受信器のコストダウンに寄与する。Since the pulse receiving circuit of the present invention is configured as described above, it becomes possible to receive long distance and high speed pulses while suppressing the current consumption of the input circuit of the receiver.
In particular, when used in a receiver using a battery as a power source, the battery capacity can be reduced, which contributes to cost reduction of the receiver.
【図１】 本発明の第１実施例の電気回路の要部。FIG. 1 is a main part of an electric circuit according to a first embodiment of the present invention.
【図２】 本発明の第２実施例の電気回路の要部。FIG. 2 is a main part of an electric circuit according to a second embodiment of the present invention.
【図３】 本発明の第３実施例の電気回路の要部。FIG. 3 is a main part of an electric circuit according to a third embodiment of the present invention.
【図４】 従来技術の電気回路の一部。FIG. 4 is a portion of a prior art electrical circuit.
【図５】 受信器の入力パルス波形で、（ａ）は周波数
が小さいとき、（ｂ）は周波数が大きいときを示す。5A and 5B show an input pulse waveform of a receiver, where FIG. 5A shows a case where the frequency is small and FIG. 5B shows a case where the frequency is large.
１…メータ、２…オープンコレクタ接続のトランジス
タ、３…ケーブル、４…受信器、５，６…入力端子、７
Ａ…抵抗器、７Ｂ，７Ｅ…第１の抵抗器、７ｃ，７Ｆ…
第２の抵抗器、７Ｄ，７Ｇ…直列回路、Ｓ1 ，Ｓ2 …ス
イッチ、８…電源、１０…周波数検知部。1 ... Meter, 2 ... Open collector connected transistor, 3 ... Cable, 4 ... Receiver, 5, 6 ... Input terminal, 7
A ... Resistors, 7B, 7E ... First resistors, 7c, 7F ...
A second resistor, 7D, 7G ... series circuit, S 1, S 2 ... switch, 8 ... power, 10 ... frequency detecting unit.
─────────────────────────────────────────────────────
─────────────────────────────────────────────────── ───
【手続補正書】[Procedure amendment]
【提出日】平成５年５月２４日[Submission date] May 24, 1993
【手続補正１】[Procedure Amendment 1]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】請求項１[Name of item to be corrected] Claim 1
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【手続補正２】[Procedure Amendment 2]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００１４[Correction target item name] 0014
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００１４】前記目的を達成するために、請求項１の発
明は、オン・オフパルスを受信する入力端子（５），
（６）を備えた受信器（４）において、一方の入力端子
（６）と電源（８）の一端との間に設けた抵抗器（７
Ａ）の抵抗値を入力パルスの周波数又は間隔に応じて変
更するように構成して、入力パルスの周波数が大きくな
るか又は間隔が小さくなると前記抵抗値を小さくするよ
うに定めた。[0014] To achieve the above object, the invention of claim 1 has an input terminal for receiving on--OFF pulse (5),
In a receiver (4) including (6), a resistor (7) provided between one input terminal (6) and one end of a power supply (8).
The resistance value of A) is configured to be changed according to the frequency or interval of the input pulse, and the resistance value is set to be decreased when the frequency of the input pulse increases or the interval decreases.
Claims (3)
る受信器において、一方の入力端子と電源の一端との間
に設けた抵抗器の抵抗値を入力パルスの周波数又は間隔
に応じて変更するように構成して、入力パルスの周波数
が大きくなるか又は間隔が小さくなると前記抵抗値を小
さくするように定めたことを特徴とするパルス受信回
路。1. A receiver for receiving an on / off pulse between input terminals, wherein a resistance value of a resistor provided between one input terminal and one end of a power supply is changed according to a frequency or an interval of the input pulse. A pulse receiving circuit configured as described above, wherein the resistance value is reduced when the frequency of the input pulse increases or the interval decreases.
端に接続された第１の抵抗器（７Ｂ）と、入力パルスの
周波数が一定以上のとき又は入力パルスの間隔が一定以
下のときに信号を出す周波数検知部（１０）と、この周
波数検知部（１０）の信号で閉じるスイッチ（Ｓ1 ）と
第２の抵抗器（７ｃ）との直列回路（７Ｄ）とを具備
し、この直列回路（７Ｄ）を前記第１の抵抗器（７Ｂ）
と並列に接続したことを特徴とする請求項１のパルス受
信回路。2. A first resistor (7B) connected to one input terminal (6) and one end of a power supply (8), and when the frequency of the input pulse is above a certain level or the interval between the input pulses is below a certain level. And a series circuit (7D) including a switch (S 1 ) closed by the signal of the frequency detection unit (10) and a second resistor (7c). , This series circuit (7D) to the first resistor (7B)
The pulse receiving circuit according to claim 1, wherein the pulse receiving circuit is connected in parallel with the pulse receiving circuit.
端に接続された第１と第２の抵抗器（７Ｅ）（７Ｆ）の
直列回路（７Ｇ）と、第１と第２の抵抗器（７Ｅ）（７
Ｆ）のうち何れか一方の抵抗器（７Ｆ）又は（７Ｅ）に
並列に接続したスイッチ（Ｓ2 ）と、入力パルスの周波
数が一定以上のとき又は入力パルスの間隔が一定以下の
ときに前記スイッチ（Ｓ2 ）を閉じる周波数検知部（１
０）とを具備したことを特徴とする請求項１のパルス受
信回路。3. A series circuit (7G) of first and second resistors (7E) (7F) connected to one input terminal (6) and one end of a power supply (8), and first and second. Resistor (7E) (7
The switch (S 2 ) connected in parallel to one of the resistors (7F) or (7E) of F) and when the frequency of the input pulse is above a certain level or the interval between the input pulses is below a certain level. The frequency detector (1 to close the switch (S 2 )
0) and the pulse receiving circuit according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10920893A JP3295486B2 (en) | 1993-05-11 | 1993-05-11 | Pulse receiving circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10920893A JP3295486B2 (en) | 1993-05-11 | 1993-05-11 | Pulse receiving circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06325285A true JPH06325285A (en) | 1994-11-25 |
| JP3295486B2 JP3295486B2 (en) | 2002-06-24 |
Family
ID=14504343
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10920893A Expired - Fee Related JP3295486B2 (en) | 1993-05-11 | 1993-05-11 | Pulse receiving circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3295486B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015061103A (en) * | 2013-09-17 | 2015-03-30 | セイコーソリューションズ株式会社 | Pulse reception circuit |
-
1993
- 1993-05-11 JP JP10920893A patent/JP3295486B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015061103A (en) * | 2013-09-17 | 2015-03-30 | セイコーソリューションズ株式会社 | Pulse reception circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3295486B2 (en) | 2002-06-24 |
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