JPS6156506A - Signal output circuit - Google Patents

Signal output circuit

Info

Publication number
JPS6156506A
JPS6156506A JP59179131A JP17913184A JPS6156506A JP S6156506 A JPS6156506 A JP S6156506A JP 59179131 A JP59179131 A JP 59179131A JP 17913184 A JP17913184 A JP 17913184A JP S6156506 A JPS6156506 A JP S6156506A
Authority
JP
Japan
Prior art keywords
circuit
signal
output
drive circuit
switching element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59179131A
Other languages
Japanese (ja)
Inventor
Kenro Sugiura
杉浦 賢朗
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toyoda Koki KK
Original Assignee
Toyoda Koki KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyoda Koki KK filed Critical Toyoda Koki KK
Priority to JP59179131A priority Critical patent/JPS6156506A/en
Publication of JPS6156506A publication Critical patent/JPS6156506A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01Modifications for accelerating switching
    • H03K19/013Modifications for accelerating switching in bipolar transistor circuits
    • H03K19/0136Modifications for accelerating switching in bipolar transistor circuits by means of a pull-up or down element

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To reduce a delay of sigal transmission and to prevent te generation of head with an internal element of a drive circuit, by supplying the output of a 1-shot circuit to the control terminal of a switching element and putting the switching element under a conduction state while signals are delivered from the 1-shot circuit. CONSTITUTION:When a signal Sa to be trasmitted is changed to a low level from a high level, the pulse of the fixed time width (t) is delivered from a 1-shot circuit 12. Then a transistor TR1 is set ON for an extremely short time. Thus a large current is supplied to a trasmisson line L for a short time via a resistance R3 and the TR1. Then, the electrostatic capacity of the line L and a capacitor C1 are charged in a short time. As a result, the potential Vb of the input terminal of a buffer 11 is set at a high level with an extremely short time delay from the fall of the signal Sa. This can reduce greatly the transmission delay of signals and then decrease the power consumption of both the R3 and the TR1.

Description

【発明の詳細な説明】 〈産業上の利用分野〉 本発明は、伝送すべき信号を集積回路によって構成され
る駆動回路の入力端子に供給し、この駆動回路の出力端
子を伝送ラインに接続した信号出力回路に関するもので
ある。
[Detailed Description of the Invention] <Industrial Application Field> The present invention provides a system in which a signal to be transmitted is supplied to an input terminal of a drive circuit constituted by an integrated circuit, and an output terminal of this drive circuit is connected to a transmission line. This invention relates to a signal output circuit.

〈従来の技術〉 伝送ラインにデジタル信号を出力する従来の信号出力回
路は、第3図に示すように、伝送すべき信号を集積回路
からなる駆動回路10の入力端子10aに供給するとと
もに、この集積回路10の出力端子10bを伝送ライン
Lの一端に接続するようにしている。そして、伝送ライ
ンLの他端を信号受信用のバッファ1)の入力端子1)
aに接続するとともに、この他端側と電源ラインPLと
の間にプルアンプ抵抗R1を接続し、アースとの間にコ
ンデンサC1を接続した構成としている。
<Prior Art> As shown in FIG. 3, a conventional signal output circuit that outputs a digital signal to a transmission line supplies a signal to be transmitted to an input terminal 10a of a drive circuit 10 made of an integrated circuit, and The output terminal 10b of the integrated circuit 10 is connected to one end of the transmission line L. The other end of the transmission line L is connected to the input terminal 1) of a buffer 1) for signal reception.
a, a pull amplifier resistor R1 is connected between this other end and the power supply line PL, and a capacitor C1 is connected between the other end and the ground.

〈発明が解決しようとする問題点〉 かかる従来のものにおいては、雑音吸収等のために設け
られるコンデンサCIおよび伝送ラインLが持つ静電容
量の影響で、第4図+a)、 Tblに示すように入力
信号Saの立下がりに対してバンファllの入力端子に
おける電位vbの変化は遅れがあり、信号の伝達速度が
遅くなる問題がある。
<Problems to be Solved by the Invention> In such a conventional system, due to the influence of the capacitance of the capacitor CI provided for noise absorption and the transmission line L, as shown in Fig. 4+a) and Tbl. There is a delay in the change in the potential vb at the input terminal of the buffer 11 with respect to the fall of the input signal Sa, resulting in a problem that the signal transmission speed becomes slow.

このような問題をなくすためにはプルアンプ抵抗R1を
小さくして充電時定数を短くすればよいが、このように
すると、駆動回路10の出力端子10bがローレベルの
状態となった時、抵抗R1を介して流れる電流が増大し
、消費電力の増大を招くだけでなく、駆動回路10の内
部回路における発熱も上昇し、駆動退路10の寿命を短
くする恐れもある。
In order to eliminate this problem, the pull amplifier resistor R1 can be made smaller to shorten the charging time constant. However, if this is done, when the output terminal 10b of the drive circuit 10 is at a low level, the resistor R1 The current flowing through the drive circuit 10 increases, which not only causes an increase in power consumption, but also increases heat generation in the internal circuit of the drive circuit 10, which may shorten the life of the drive retreat path 10.

く問題点を解決するための手段〉 本発明は、駆動回路の出力端子と電源ラインとの間に、
抵抗と半導体スイッチング素子とを直列的に接続すると
ともに、前記駆動回路に入力される信号の状態変化に応
答し、駆動回路の出力がローレベルからハイレベルに変
化し始める時点から一定時間の間信号を出力するワンシ
ョット回路を設け、このワンショット回路の出力を前記
スイッチング素子の制御端子に供給して前記ワンショ・
ノド回路から信号が出力されている間前記スイッチング
素子を導通状態にするようにしたことを特徴とするもの
である。
Means for Solving the Problems> The present invention provides a means for solving the above problems.
A resistor and a semiconductor switching element are connected in series, and in response to a change in the state of a signal input to the drive circuit, a signal is generated for a certain period of time from the point at which the output of the drive circuit starts changing from a low level to a high level. A one-shot circuit is provided to output the one-shot circuit, and the output of the one-shot circuit is supplied to the control terminal of the switching element to output the one-shot circuit.
The present invention is characterized in that the switching element is kept conductive while a signal is being output from the node circuit.

く作用〉 駆動回路の出力がローレベルからハイレベルに変化する
方向に入力信号の状態が変化すると、これに応答してワ
ンショット回路から一定時間幅のパルスが出力され、こ
の一定時間の量率導体スイッチング素子が導通状態とな
る。これにより、伝送ラインの静電容量と受信回路側の
コンデンサが急速充電され、受信側における電位の立上
がり速度が速められ、信号の伝送遅れが減少する。
When the state of the input signal changes in the direction in which the output of the drive circuit changes from a low level to a high level, in response, a pulse with a fixed time width is output from the one-shot circuit, and the amount rate of this fixed time The conductor switching element becomes conductive. As a result, the capacitance of the transmission line and the capacitor on the receiving circuit side are rapidly charged, the rising speed of the potential on the receiving side is accelerated, and the delay in signal transmission is reduced.

〈実施例〉 以下本発明の実施例を図面に基づいて説明する。<Example> Embodiments of the present invention will be described below based on the drawings.

第1図において、従来と同一の回路部品については、第
3図と同一の符号が付してあり、10は反転形の駆動回
路、1)はバッファ、Lは伝送ライン、R1はプルアン
プ抵抗、C1はコンデンサを示す。
In FIG. 1, circuit components that are the same as the conventional ones are given the same reference numerals as in FIG. C1 indicates a capacitor.

本発明はかかる構成において、駆動回路10の出力端子
10bと電源ラインPLとの間に、抵抗R3と半導体ス
イッチング素子を構成するNPN形トランジスタとを直
列的に接続するとともに、駆動回路10の入力側に、駆
動回路10に入力される信号Saがハイレベルからロー
レベルに変化したことに応答して一定時間幅tのパルス
sbを出力するワンショット回路12を接続し、このワ
ンショット回路12の出力をトランジスタTRIのベー
スに供給するように構成したものである。
In this configuration, the present invention connects the resistor R3 and the NPN transistor constituting the semiconductor switching element in series between the output terminal 10b of the drive circuit 10 and the power supply line PL, and also connects the resistor R3 and the NPN transistor constituting the semiconductor switching element in series. A one-shot circuit 12 that outputs a pulse sb with a constant time width t in response to a change in the signal Sa input to the drive circuit 10 from high level to low level is connected to the drive circuit 10, and the output of this one-shot circuit 12 is is configured to be supplied to the base of the transistor TRI.

なお、抵抗R3の値はトランジスタTRIの容量等によ
って決められるが、抵抗R1に対して小さな抵抗値のも
のが選択される。
Note that the value of the resistor R3 is determined by the capacitance of the transistor TRI, etc., and a resistor R3 having a smaller resistance value than the resistor R1 is selected.

かかる構成の回路においては、伝送すべき信号Saの信
号状態が第2図(a)に示すように、ハイレベルの状態
からローレベルの状態に変化すると、これに応答してワ
ンショット回路12から第2図(b)に示すように一定
時間幅tのパルスが出力され、トランシタTR1が極く
短時間の間オン状態となる。これにより、伝送ラインL
には抵抗R3とトランジスタTRIを介して短時間に大
きな電流が供給され、伝送ラインLの静電容量とコンデ
ンサC1は短時間で充電される。この結果、バッファ1
)の入力端子における電位vbは第2図(C1に示すよ
うに、信号Saの立下がりから極(短い時間遅れでハイ
レベルの状態となり、信号の伝送遅れを大幅に短縮する
ことができる。
In a circuit having such a configuration, when the signal state of the signal Sa to be transmitted changes from a high level state to a low level state as shown in FIG. As shown in FIG. 2(b), a pulse with a constant time width t is output, and the transistor TR1 is turned on for a very short time. As a result, the transmission line L
A large current is supplied in a short time through the resistor R3 and the transistor TRI, and the capacitance of the transmission line L and the capacitor C1 are charged in a short time. As a result, buffer 1
As shown in FIG. 2 (C1), the potential Vb at the input terminal of the signal Sa becomes high level with a short time delay (as shown in C1 in FIG. 2), and the signal transmission delay can be greatly reduced.

またトランジスタTRIは信号3aがローレベルである
時常時オン状態となるのではなく、第2図(a)、 (
b)に示すように信号Saがハイレベルからローレベル
に変化した直後の一定時間tの間だけオン状態となるた
め、抵抗R3およびトランジスタTRIにおける消費電
力を小さくできる利点がある。
In addition, the transistor TRI is not always on when the signal 3a is at a low level;
As shown in b), since the signal Sa remains on for a certain period of time t immediately after changing from high level to low level, there is an advantage that the power consumption in the resistor R3 and the transistor TRI can be reduced.

なお半導体スイッチング素子として電界効果トランジス
等地の素子を用いても良い。
Note that an element such as a field effect transistor may be used as the semiconductor switching element.

〈発明の効果〉 以上述べたように本発明においては、集積回路によって
構成される駆動回路の出力端子と電源ラインとの間に抵
抗と半導体スイッチング素子とを直列的に接続するとと
もに、駆動回路の出力がローレベルからハイレベルに変
化するタイミングで一定時間幅のパルスを出力するワン
ショット回路を設け、このワンショット回路の出力で半
導体スイッチング素子を導通状態とするように構成した
ので、消貸電力を殆ど増加させることなしに伝送ライン
における信号の伝達遅れを大幅に減少でき、また駆動回
路の内部素子の発熱が増加することも防止できる利点が
ある。
<Effects of the Invention> As described above, in the present invention, a resistor and a semiconductor switching element are connected in series between the output terminal of a drive circuit constituted by an integrated circuit and a power supply line, and a A one-shot circuit is provided that outputs a pulse with a fixed time width at the timing when the output changes from low level to high level, and the semiconductor switching element is made conductive by the output of this one-shot circuit, thereby reducing power consumption. This method has the advantage that the signal transmission delay in the transmission line can be significantly reduced without increasing the signal speed, and the heat generation of the internal elements of the drive circuit can also be prevented from increasing.

【図面の簡単な説明】[Brief explanation of drawings]

第1図と第2図は本発明の実施例を示すもので、第1図
は信号伝送回路の全体構成図、第2図は第1図の回路の
動作を説明するためのタイミングチャート、第3図およ
び第4図は従来技術を示すもので、第3図は伝送回路の
全体構成図、第4図はその動作を示すタイムチャートで
ある。 10・・・駆動回路、1)・・・バッファ、12・・・
ワンジット回路、CI・・・コンデンサ、L・・・伝送
ライン、R1,R3・・・抵抗、TR1・・・トランジ
スタ。
1 and 2 show an embodiment of the present invention. FIG. 1 is an overall configuration diagram of a signal transmission circuit, FIG. 2 is a timing chart for explaining the operation of the circuit in FIG. 1, and FIG. 3 and 4 show the prior art. FIG. 3 is an overall configuration diagram of a transmission circuit, and FIG. 4 is a time chart showing its operation. 10...Drive circuit, 1)...Buffer, 12...
One-jit circuit, CI...capacitor, L...transmission line, R1, R3...resistor, TR1...transistor.

Claims (1)

【特許請求の範囲】[Claims] (1)伝送すべき信号を集積回路によって構成される駆
動回路の入力端子に供給し、この駆動回路の出力端子を
伝送ラインに接続した信号出力回路において、前記駆動
回路の出力端子と電源ラインとの間に、抵抗と半導体ス
イッチング素子とを直列的に接続するとともに、前記駆
動回路に入力される信号の状態変化に応答し、駆動回路
の出力がローレベルからハイレベルに変化し始める時点
から一定時間の間信号を出力するワンショット回路を設
け、このワンショット回路の出力を前記スイッチング素
子の制御端子に供給して前記ワンショット回路から信号
が出力されている間前記スイッチング素子を導通状態に
するようにしたことを特徴とする信号出力回路。
(1) In a signal output circuit in which a signal to be transmitted is supplied to an input terminal of a drive circuit constituted by an integrated circuit, and an output terminal of this drive circuit is connected to a transmission line, the output terminal of the drive circuit and a power supply line are connected. At the same time, a resistor and a semiconductor switching element are connected in series, and in response to changes in the state of the signal input to the drive circuit, the output of the drive circuit is constant from the point when the output starts to change from low level to high level. A one-shot circuit that outputs a signal for a period of time is provided, and the output of this one-shot circuit is supplied to a control terminal of the switching element to make the switching element conductive while the signal is output from the one-shot circuit. A signal output circuit characterized in that:
JP59179131A 1984-08-27 1984-08-27 Signal output circuit Pending JPS6156506A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59179131A JPS6156506A (en) 1984-08-27 1984-08-27 Signal output circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59179131A JPS6156506A (en) 1984-08-27 1984-08-27 Signal output circuit

Publications (1)

Publication Number Publication Date
JPS6156506A true JPS6156506A (en) 1986-03-22

Family

ID=16060524

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59179131A Pending JPS6156506A (en) 1984-08-27 1984-08-27 Signal output circuit

Country Status (1)

Country Link
JP (1) JPS6156506A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02970A (en) * 1988-03-31 1990-01-05 Asahi Chem Ind Co Ltd Novel letterpress printing plate
JPH0244916A (en) * 1988-08-05 1990-02-14 Nec Corp Buffer circuit
US6333134B1 (en) 1993-04-30 2001-12-25 Toyo Boseki Kabushiki Kaisha Multilayered photopolymer element including sensitivity controlling agents

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02970A (en) * 1988-03-31 1990-01-05 Asahi Chem Ind Co Ltd Novel letterpress printing plate
JPH0244916A (en) * 1988-08-05 1990-02-14 Nec Corp Buffer circuit
US6333134B1 (en) 1993-04-30 2001-12-25 Toyo Boseki Kabushiki Kaisha Multilayered photopolymer element including sensitivity controlling agents

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