JPH06324898A - Information processor - Google Patents

Abstract

PURPOSE:To perform the operatin of a device successively by without stopping the operation of the device instructing the holding of a software visible register at an exception processing part, or instructing the redoing of pre-fetch to an instruction fetch part and an operand fetch part by replacing a value within exception processing when an intermittent fault occurs in a control storage part. CONSTITUTION:A fault discrimination part 12 sends out a signal to the exception processing part 20 when a next instructin to an instruction in which a fault occurs is the one to use computing element 15b while the output signal of a fault detecting part 9a is inputted, and when the instruction is an executing state. The exception processing part 20, when inputting the signal, instructs the holding of the software visible register. A history register is provided for the software visible register for which the holding is not in time, and the value is replaced in the exception processing. The exception processing part 20 instructs the redoing of pre-fetch to the instruction fetch part 1 and the operand fetch part 3 simultaneously with the above mentioned operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, and more particularly to a retry function of its control storage unit.

[0002]

2. Description of the Related Art When a control storage unit of an information processing device fails,
There are correctable failures (intermittent failures) and uncorrectable failures (fixed failures). In the case of an intermittent failure, by rewriting the correct data in the control storage unit, the information processing apparatus can be continuously operated without being stopped. When a failure occurs in one control storage unit, it is difficult to stop the operations of all control storage units and arithmetic units at the same timing. Therefore, when a failure occurs in one control storage unit, the timing at which the operation of the other control storage unit and the operation unit is stopped is later than the operation stop timing of the control storage unit in which the failure has occurred and the operation unit related thereto. It will be the timing. Therefore, an instruction that should not be executed (an instruction next to an instruction in which a failure has occurred in the control storage unit) may be executed. If you continue the operation in that state, the pipeline will be disturbed and the operation result will be incorrect, so conventionally,
The operation of the information processing device is stopped.

FIG. 3 is a block diagram showing an example of the conventional information processing apparatus as described above, and FIG. 4 is a timing chart showing the operation of the example of FIG.

In FIG. 3, the instruction fetch unit 1 prefetches an instruction. The instruction register (IFR) 2 receives an instruction prefetched by the instruction fetch unit 1.

The operand fetch unit 3 prefetches operands. The operand register (DFR) 4 receives the operand prefetched by the operand fetch unit 3.

The decoder (IDEC) 5 decodes the instruction received by the instruction register (IFR) 2 and identifies the type of the instruction.

Address registers (CSA) 6a and 6
b holds the addresses of the control storage units (CS) 7a and 7b, respectively. Control storage units (CS) 7a and 7b
Are address registers (CSA) 6a and 6 respectively.
It stores a microprogram that is indexed using the value held by b as an address. Control storage register (CS
R) 8a and 8b are control storage units (CS) 7 respectively.
It receives the values of a and 7b.

Fault detectors 9a and 9b detect the presence / absence of a fault in control storage units (CS) 7a and 7b from the output values of control storage registers (CSR) 8a and 8b, respectively. When the faults detected by the fault detecting units 9a and 9b are correctable faults, the fault correcting units 10a and 10b correct the corresponding control storage units (CS) 7a and 7b.

Fault report registers (EH) 11a and 1
1b, when a failure occurs in the control storage units (CS) 7a and 7b, respectively, the corresponding failure detection units 9a and 9b.
The signal from b is input and the value is held until the correction of the failure of the control storage unit (CS) 7a or 7b is completed.

The failure determination section 32 determines whether or not to stop the information processing apparatus based on the outputs of the failure detection sections 9a and 9b, and outputs a stop signal 41.

The data registers 13a to 13d receive and hold the output of the operand register (DFR) 4.

Decoders (CCNT) 14a and 14b
Are control storage registers (CSR) 8a and 8 respectively.
The type of operation is determined by the output of b. Calculator 15a
And 15b are decoders (CCNT) 14a, respectively.
And 14b to perform various calculations.

The selector 16 includes arithmetic units 15a and 15a.
Switch the output signal of b. Result register (RXR)
Reference numeral 17 denotes an arithmetic unit 15 switched by the selector 16.
Hold the output value of a or 15b.

CS mode register (CMCDE) 18
Indicates which arithmetic unit value is to be selected in the selector 16 by the output of the decoder (IDEC) 5. The register (CREG) 19 holds the output value of the CS mode register (CMCDE) 18.

The exception processing unit 40 is provided with the arithmetic units 15a and 1a.
Exception processing is performed by signals from 5b, the instruction fetch unit 1, and the operand fetch unit 3.

The information processing apparatus configured as described above is
It works as follows.

First, the instruction fetch unit 1 prefetches an instruction. The instruction fetched by the instruction fetch unit 1 is held in the instruction register (IFR) 2. The instruction held in the instruction register (IFR) 2 is
The EC) 5 determines which of the arithmetic units 15a and 15b is used for the instruction.

When the arithmetic unit to be used is designated by the decoder (IDEC) 5, an address is given to the control storage unit (CS) 7a or 7b for controlling the arithmetic unit. That is, the address data is set in the address register (CSA) 6a or 6b.

Here, it is an instruction to use the arithmetic unit 15a, and the following description will be continued assuming that the address data is set in the address register (CSA) 6a.

At this time, at the same time, the decoder (IDEC) 5
Is set in the CS mode register (CMCDE) 18. CS mode register (CMCDE) 18
Output value of the register (CREG) 1 at the next timing
Set to 9.

The control storage section (CS) 7a is indexed by using the value of the address register (CSA) 6a as an address, and the result (microprogram) is held in the control storage register (CSR) 8a. Control storage register (CS
The value of R) 8a is decoded by the decoder (CCNT) 14a.

On the other hand, in the operand fetch unit 3,
Operands are prefetched. The prefetched operand is set in the operand register (DFR) 4, and the value of the operand register (DFR) 4 is set in the data registers 13a and 13b.

The arithmetic unit 15a inputs the data registers 13a and 13b and performs the arithmetic operation instructed by the decoder (CCNT) 14a. The selector 16 selects the arithmetic unit 15a according to the output signal of the register (CREG) 19 and outputs the calculation result of the arithmetic unit 15a to the result register (R
XR) 17 is set and the operation of the instruction is completed. At this time, if there is an exception (for example, overflow) in the calculation result of the arithmetic unit 15a, a signal is sent from the arithmetic unit 15a to the exception processing unit 40, and the exception processing unit 40 performs exception processing.

The value of the control storage register (CSR) 8a is also sent to the failure detector 9a to detect the presence or absence of a failure. If a failure is detected by the failure detection unit 9a and it is a correctable failure, the result is the failure correction unit 10a.
A is notified, and the failure correction unit 10a creates a signal for correcting the failure.

At this time, the control storage section (CS) 7a is held by the output signal of the failure detection section 9a, and the failure report register (EH) 11a is set. Further, the control storage unit (CS) 7b is held by the output signal of the failure report register (EH) 11a. The failure correction unit 10a sends a correction instruction to the defective word in the control storage unit (CS) 7a.

The output signal of the failure detecting section 9a is also sent to the failure determining section 32 at the same time. In the failure determining section 32, the next instruction having a failure is an instruction to use the arithmetic unit 15b, and the instruction is It is checked whether it is in the running state. The next instruction is an instruction to use the arithmetic unit 15b, and when the instruction is in the execution state, the failure determination unit 32 sends a stop signal 41 for stopping the operation of the information processing device. A few seconds after this, the stop signal 41 is distributed throughout the information processing apparatus, and the operation of the information processing apparatus is stopped.

FIG. 4 is a timing chart showing the above operation.

As shown in FIG. 4, first, the instruction 50 using the arithmetic unit 15a is executed, and then the instruction 51 using the arithmetic unit 15b is executed.

The instruction 50 is received by the instruction register (IFR) 2 in the C cycle, and the address is set in the address register (CSA) 6a in the T cycle.
Next, in the E cycle, the control storage unit (CS) 7a is indexed, and the result (microprogram) is set in the control storage register (CSR) 8a.

Also in the T cycle, the operand of the instruction 50 is set in the operand register (DFR) 4, and the value of the operand register (DFR) 4 is set in the data registers 13a and 13b in the E cycle.

When a correctable failure has occurred in the output signal of the control storage register (CSR) 8a and the failure detection unit 9a detects this in the E cycle, the failure report register (EH) 11a is set, At the same time, it is reported to the failure correction unit 10a.

In the W cycle, the operation result of the values of the data registers 13a and 13b in the arithmetic unit 15a is to be stored in the result register (RXR) 17,
Update of the result register (RXR) 17 is suppressed by the output signal of the failure detection unit 9a. The operation of the instruction 51 in the C cycle, the T cycle, and the E cycle is executed normally, and only the operation of the W cycle is suppressed by the failure report register (EH) 11a.

Therefore, the instruction 51 also includes the result register (R
XR) 17 is in a completed state except for the update. Even if an attempt is made to execute the instruction 50 again by correcting the failure of the control storage unit (CS) 7a in this state, the operation result of the instruction 51 remains in the operation unit 15b.
It will be an invalid value.

[0034]

As described above, in the conventional information processing apparatus, when a correctable failure occurs when the operation by one control storage unit shifts to the operation by another control storage unit, Since it is not possible to stop the instruction next to the one that caused a failure and the result of correcting the failure and re-executing the instruction will be an incorrect value, even if a correctable failure occurs, There is a problem that the operation has to be stopped.

[0035]

An information processing apparatus according to the present invention is an information processing apparatus that has an instruction fetch unit for prefetching an instruction and an operand fetch unit for prefetching an operand and performs a pipeline operation. A first control storage unit that stores a program; a second control storage unit that stores a microprogram that performs an exclusive operation with respect to the operation of the first control storage unit; A first arithmetic unit controlled by the control storage unit, a second arithmetic unit controlled by the second control storage unit, and a first failure detection for detecting a failure of the first control storage unit. Section, a second failure detection section for detecting a failure of the second control storage section, a failure detected by the first failure detection section and the second failure detection section, and the first control storage Section from the second control note From the second control storage unit to the first control storage unit to determine whether it occurs when the operation is transferred to the first control storage unit, and from the failure determination unit And a signal from the first and second arithmetic units, and an exception processing unit that performs exception processing with the signals from the instruction fetch unit and the operand fetch unit, and uses the first control storage unit. When the correctable failure occurs in the first control storage unit at the same time as the execution instruction of the command that uses the second control storage unit is transmitted after the execution of the instruction, or the second control storage unit. When a correctable fault occurs in the second control storage unit at the same time when an instruction to execute the instruction using the first control storage unit is transmitted after executing the instruction using the correctable fault, the correctable fault is corrected. Shi After that, it includes restarting the instruction fetch unit and the operand fetch unit by a signal from the exception processing unit, and in particular, the priority of the exception processing from the failure determination unit with respect to the exception processing unit, The priority is set to be lower than the priority of the processing of exceptions from the first and second arithmetic units and the processing of exceptions from the instruction fetch unit and the operand fetch unit.

[0036]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a timing chart showing the operation of the embodiment of FIG.

The configuration of the embodiment shown in FIG. 1 is the same as that of the conventional example shown in FIG. 3, except for the failure determination unit 12 and the exception processing unit 20.

The failure determination unit 12 determines whether or not to stop the information processing device based on the outputs of the failure detection units 9a and 9b, and sends the result to the exception processing unit 20.

The exception processing unit 20 includes the arithmetic units 15a and 1a.
Exception processing is performed by signals from 5b, the instruction fetch unit 1, the operand fetch unit 3, and the failure determination unit 12.

The information processing apparatus configured as described above is
It works as follows.

The operations of the respective parts other than the failure determination part 12 and the exception processing part 20 are the same as the operations of the corresponding parts of the above-mentioned conventional example, and therefore a detailed description thereof will be omitted.

When the output signal of the failure detection section 9a is input to the failure determination section 12, the next instruction that has a failure is given to the arithmetic unit 15
It is an instruction using b, and it is checked whether or not the instruction is in the execution state. The next instruction is an instruction to use the arithmetic unit 15b, and when the instruction is in the execution state, the failure determination unit 12 sends a signal to the exception processing unit 20.

The exceptions sent at this time are the arithmetic unit 1
The priority is set lower than the exceptions from 5a and the exceptions from the instruction fetch unit 1 and the operand fetch unit 3. The reason is that when other fatal exceptions occur, the intermittent failure in the control memory becomes insignificant, and the exception resulting from the operation result is the same exception when the instruction is restarted. This is because the error occurs, and at that time, the control storage unit may be corrected.

When the exception processing section 20 receives a signal from the failure determination section 12, it instructs the software visible register to be held. If the software visible register cannot be held in time, it has a history register and replaces the value during exception processing.

At the same time, the exception processing unit 20 instructs the instruction fetch unit 1 and the operand fetch unit 3 to redo the prefetch.

The control storage unit (C
When the correction of the failure of (S) 7a is completed, the failure report register (EH) 11a is set. Further, the failure report registers (EH) 11a and 11b are reset, the instruction interrupted by the instruction fetch unit 1 is sent again, and the instruction is re-executed. In this way, when an intermittent failure occurs in the control storage unit, the information processing device does not need to stop its operation and can continue to operate.

FIG. 2 is a timing chart showing the above operation.

In FIG. 2, the operations other than the exception processing unit 20 are the same as those in FIG. 4, and therefore detailed description will be omitted.

The exception processing section 20 is activated by the output signal (not shown in FIG. 2) of the failure determination section 12.
As a result, the exception processing unit 20 sends an activation signal to the instruction fetch unit 1 and the operand fetch unit 3. The instruction fetch unit 1 and the operand fetch unit 3, when receiving the activation signal from the exception processing unit 20, start their prefetching.

[0051]

As described above, in the information processing apparatus of the present invention, when an intermittent failure occurs in the control storage section, the next instruction having the failure uses another computing unit in the failure determination section. The exception processing unit determines whether the instruction is in the execution state and sends a signal to the exception processing unit, and instructs the exception processing unit to hold the software visible register, or By replacing the value in the middle and at the same time instructing the instruction fetch unit and the operand fetch unit to redo the prefetching, it is possible to continuously operate the information processing device without stopping the operation. is there.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the embodiment shown in FIG.

FIG. 3 is a block diagram showing an example of a conventional information processing apparatus.

FIG. 4 is a timing chart showing the operation of the example of FIG.

[Explanation of symbols]

 1 instruction fetch unit 2 instruction register (IFR) 3 operand fetch unit 4 operand register (DFR) 5 decoder (IDEC) 6a / 6b address register (CSA) 7a / 7b control storage unit (CS) 8a / 8b control storage register (CSR) ) 9a / 9b Failure detection section 10a / 10b Failure correction section 11a / 11b Failure report register (EH) 12/32 Failure determination section 13a / 13b / 13c / 13d Data register 14a / 14b Decoder (CCNT) 15a / 15b Operation unit 16 Selector 17 Result register (RXR) 18 CS mode register (CMCDE) 19 Register (CREG) 20/40 Exception processing unit 40 41 Stop signal 50/51 instruction

Claims (2)

[Claims] 1. An information processing apparatus having an instruction fetch unit for prefetching an instruction and an operand fetch unit for prefetching an operand, which performs a pipeline operation, wherein a first control storage unit stores a microprogram. A second control storage unit that stores a microprogram that performs an exclusive operation with respect to the operation of the first control storage unit; and a first operation controlled by the first control storage unit. Section, a second computing section controlled by the second control storage section, a first failure detection section for detecting a failure of the first control storage section, and a failure of the second control storage section. A second failure detection unit for detecting the failure, the failure detected by the first failure detection unit and the second failure detection unit operates from the first control storage unit to the second control storage unit. Bites that occurred when migrating Is a failure determination unit that determines whether an operation occurs when the operation is transferred from the second control storage unit to the first control storage unit, a signal from the failure determination unit, and the first and second calculations Unit and an exception processing unit that performs exception processing by signals from the instruction fetch unit and the operand fetch unit, the second control after executing an instruction using the first control storage unit When a correctable failure occurs in the first control storage unit at the same time when an instruction to execute a storage unit use instruction is sent, or the first control storage unit is used after the instruction using the second control storage unit is executed. When a correctable failure occurs in the second control storage section at the same time when an instruction to execute an instruction that uses the control storage section is sent, after correcting the correctable failure, a signal from the exception handling section is used. Previous An information processing apparatus comprising: reactivating an instruction fetch unit and the operand fetch unit. 2. The priority of the exception processing from the failure determination unit with respect to the exception processing unit is set to the exception processing from the first and second arithmetic units and the exception processing from the instruction fetch unit and the operand fetch unit. The information processing apparatus according to claim 1, further comprising setting the processing priority lower than the priority.