JPH06324666A - Character generating device - Google Patents

Abstract

PURPOSE:To obtain a character generating device which is suitable to power consumption reduction of a system and LSI-implementation by composing the device of plural modules and stopping the functions of modules which do not operate in accordance with modes. CONSTITUTION:A module 1 (13) is a vector block and a module 2 (14) is a raster block. For example, when mode information written in a mode register 11 indicates a mode wherein the process of the vector block is not performed for outline font data inputted to the character generating device, a block supply control circuit 12 does not supply a clock CLK1 to the vector block. A necessary irreducible clock, however, is supplied for transfer from a font input FIFO to an FIFO through the vector block. A mode wherein the process of the raster block is not performed is the same. Thus, the functions of the modules 13 and 14 which do not operate to perform conversion specified by the modes are stopped.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a character / graphics generator in the field of computer graphics, and more particularly to a character / graphics generator for converting contour data of a character / graphic represented in a vector format into raster format data.

[0002]

2. Description of the Related Art As a method of outputting characters of a plurality of sizes and characters such as rotation and italics, there is a device for converting outline font data composed of character outline information into dot font data. The outline font data is composed of data in which the points on the outline of the character are represented by coordinate values, flag data indicating the attributes of the data, and the like. Use this outline font data as a character font
The coordinate conversion operation called affine transformation is performed according to the specified output size in the OM or the external storage device, and in order to output the curve of the character beautifully, the coordinate conversion operation is performed on the coordinate data on the curve by curve interpolation. Output. Further, there is a character generator that generates a line with dots between coordinate-converted coordinate data, fills the outline of the generated character, converts it into a dot font, and outputs it.

FIG. 8 shows a Japanese Patent Application No. 2 filed by the applicant earlier.
No. 19052, “Character generator”, it is an internal block configuration example of an outline font processor (OFP) 80, which is a character generation LSI for performing a series of processes for converting the outline font data into dot font data.

The OFP 80 is a host interface 81 and a font input FIFO inside the host interface.
82, block 83 including affine transformation block and line width correction block, FIFO 84, curve interpolation block 85, FI
It comprises a FO 86, a line generation block 87, a dot memory 88, a fill BitBLT block 89, and a page memory interface 90. The host interface 81 outputs an address bus, a data bus, and a control signal group connected to the system bus on the system side. The internal data bus 91 is connected to the system data bus. Further, a data bus 92 is connected from the font input FIFO 82 to a block 83 composed of an affine transformation block and a line width correction block. Also, the page memory interface 90 outputs an address bus, a data bus, and a control signal group connected to the page memory controller on the system side.

[0005]

In the above-mentioned conventional character generator, the functions necessary for the series of processing for converting the outline font data into the dot font data are performed in module units. In this example of the character generator, as a module, a block 83 consisting of an affine transformation block and a line width correction block, a curve interpolation block 85, a line generation block 87, and a fill BitB
It is composed of four modules of the LT block 89.

Therefore, for example, in this character generator, in a mode in which affine conversion and line width correction are not executed, the input outline font data passes from the font input FIFO 82 through the affine conversion block and line width correction block 83. Are transferred to the FIFO 84. At this time, the host interface 81 always supplies a clock to the non-functioning affine transformation block and line width correction block 83. In addition, even in a mode in which other functions are not executed, the clock is always supplied to the non-functioning module.

Further, when the above-mentioned one module is composed of a plurality of modules, some modules do not function depending on the mode. For example, in the curve interpolation block 85, there are a fixed mode in which the number of coordinate points generated on the curve is constant and a determination mode in which the optimum number of coordinate points generated on the curve is determined by the shape and length of the curve. , When the fixed mode is specified, the module that operates in the judgment mode does not work. At this time, the curve interpolation module constantly supplies the clock to the module operating in the non-functioning determination mode.

Further, a clock is always supplied to each module until valid data is input to the character generator or after the valid data that has been input is processed. is doing.

Further, even when data is transferred between modules, a clock is always supplied to each module even when the modules are in a waiting state.

Therefore, since the character generator constantly supplies the clock to the module that does not function depending on the mode or the processing state, the power consumption of the entire character generator is high and the character generator is relatively low in price. In a system aiming at low power consumption, the cost of the character generator occupying the entire system is high.

Therefore, in the character generator in the above system, there is a module that does not function depending on the mode, and it has been noted that the ratio is large in terms of power consumption. That is, by stopping the supply of the clock to the non-functioning module, the power consumption of the entire character generating device can be reduced.

It is an object of the present invention to provide a character generator for converting outline font data composed of character contour information into dot font data, which is suitable for low power consumption of the system. .

Another object of the present invention is to provide the above character generator suitable for LSI.

Another object of the present invention is not limited to the above character generator, but is to provide a data processor suitable for lowering the power consumption of the system in a data processor having the same architecture as above. Is.

[0015]

In order to achieve the above object, a character generator according to the present invention uses a plurality of modes when converting outline font data composed of character outline information into dot font data. In order to execute the conversion specified by the mode, the function of the module which is composed of a plurality of modules and does not operate depending on the mode is stopped.

In the above character generator, the mode information to be converted is stored in the register inside the character generator, and the function of the module which does not operate depending on the mode is stopped based on the mode information.

In the above-mentioned character generator, a plurality of standby terminals are provided for the mode information to be converted as a signal from the outside of the character generator, and the function of the module which does not operate depending on the mode is stopped based on the mode information. is there.

The above character generator is provided with means for determining whether the input data is valid data to be processed, and the function of each module is stopped until the valid data is input, and the valid data is obtained. The function of each module is activated when data is input, and the function of each module is stopped again when the processing of valid data is completed.

In the above character generator, the data transfer between the modules is performed by one module and a FIFO connected between the modules, and when the module on the transfer side writes data to the FIFO, FI
When the FO is full and cannot be written, or when the receiving module reads data from the FIFO,
When the FIFO cannot be read because it is empty, it is provided with a judging means for stopping the function of the module.

[0020]

According to the above means, in the character generator for converting the outline font data composed of the character outline information into the dot font data, a plurality of conversion modes are provided, and the conversion designated by the mode is executed. To
Since the function of the module which is composed of a plurality of modules and does not operate depending on the mode is stopped, the power consumption of the character generator can be remarkably reduced.

According to the above means, the mode information to be converted is stored in the register inside the character generator, and the function of the module which does not operate depending on the mode is stopped by the mode information. Therefore, the user saves power. It is possible to reduce the power consumption of the detail module inside the character generation device without being aware of it.

According to the above means, the mode information to be converted is used as a signal from the outside of the character generator, a plurality of standby terminals are provided, and the function of the module that does not operate depending on the mode is stopped by the mode information. It is possible to intentionally save a large amount of power, and in particular, it is possible to reduce the power consumption for a large module inside the character generator.

According to the above means, there is provided means for judging whether the input data is valid data to be processed,
The function of each module is stopped until valid data is input. When the valid data is input, the function of each module is activated, and when the valid data is processed, the function of each module is stopped again. Therefore, power saving can be automatically realized for the character generator depending on the presence or absence of valid data, and the power consumption of the entire system including the character generator can be reduced.

According to the above means, the data transfer between the modules is performed by one module and the FIFO connected between the one module, and when the module on the transfer side writes the data to the FIFO, When the FIFO is full and cannot be written, or when the receiving module reads data from the FIFO, the FIFO
If a device cannot read due to its empty status, it is equipped with a means to judge it, and the function of the module is stopped, so that power saving can be realized even during the period when data processing is being performed, and the power consumption of the character generator can be reduced. You can

[0025]

EXAMPLES Examples of the present invention will be described in detail below.

FIG. 7 shows a system configuration example using a character generator for converting outline font data composed of character contour information into dot font data. A system bus 77 including an address bus, a data bus, and a control signal group includes a CPU 71, a system memory 72, a character generator 1, a font memory 73, a printer 74, and a keyboard 7.
5 and the display 76 are connected. This system is mainly used for low-priced word processors, CRT systems, personal information devices, and the like. For example, CP
U 1 reads out outline font data from the font memory 73 and writes it in the character generator 1. The character generator 1 sequentially converts the written outline font data into dot font data and expands it in a built-in dot memory. CPU71 is a character generator
The dot font data expanded in the dot memory 1 is read out, transferred to the printer 74 or the display 76, and printed or displayed.

FIG. 2 shows a character generator 1 to which the present invention is applied.
It is a block diagram of. Note that the present device is not limited to this, and may be a single element integrated into an LSI or a systemized device as a microcomputer and a microcomputer peripheral device.

Here, the character generator 1 includes a CPU interface 2 and a font input FIFO 3, a vector block 4 and a FIFO inside the CPU interface 2.
It consists of 5, raster block 6, and dot memory 7. This character generator is roughly divided by function,
It consists of two modules, vector block 4 and raster block 6. An address bus, a data bus, and a control signal group connected to the system bus are input and output from the CPU interface 2. In addition, the control signal group includes a standby terminal STBY1 for transmitting some mode information for converting outline font data to dot font data to the character generator.
There are N and STBY2N.

In this character generator 1, the data bus D0
The outline font data input from ~ D15 is
Font input FIFO 3 and local data bus C
It is sent to the vector block 4 via D0 to CD15. The data processed in Vector Block 4 is FIF
It is sent to raster block 6 via O 5. The data processed by the raster block 6 is expanded in the dot memory 7 as dot font data. The processing executed in the vector block 4 and the raster block 6 will be described later.

Next, the operation of the character generator according to the present invention will be described.

FIG. 1 shows the inside of the character generator from the mode information written in the n-bit mode register 11 inside the character generator via the clock CLK supplied to the character generator 1 and the data buses D1 to D15. 3 is a block diagram showing a method of controlling a clock supplied to the module of FIG.
Reference numeral 12 is a clock supply control circuit that controls a clock supplied to the module based on CLK and the mode information 11. Clocks CLK1 and CLK2 are supplied from the clock supply control circuit 12 to each module.

First, the module 1 13 described below
2 is vector block 4 in FIG. 2 and is module 2
14 is the raster block 6 in FIG. For example, if the mode information written in the mode register 11 is a mode in which the processing of the vector block 4 is not performed on the outline font data input to the character generator, the clock supply control circuit 12 causes the vector block 4 to operate.
Does not supply the clock CLK1. However, the minimum clock required to transfer from the font input FIFO 3 to the FIFO 5 via the vector block 4 is supplied. The same applies to the mode in which the raster block 6 is not processed.

Next, an example in which the clock supply control method described in FIG. 1 is further applied inside the vector block 4 or inside the raster block 6 will be described.

FIG. 3 is a block diagram for controlling the clock supplied to the module inside the vector block from the clock CLK1 supplied to the vector block 4 and the mode information 11 of n bits. 31 is CLK1 and mode information
11 is a clock supply control circuit for controlling the clock supplied to the module. Clock supply control circuit
From 31 to each module clock CLKA, CLK
B, CLKC, and CLKD are supplied. Modules in vector blocks are
An affine transformation module 32 that performs coordinate transformation such as rotation,
Line width correction module 33 that corrects the width of all the lines that make up a character according to the size of the output character, curve interpolation module 34 that generates a curve with a short vector for curve data, and outline font data The address calculation module 35 calculates the address of the dot memory 7 when the head data of the loop is expanded on the dot memory 7. Further, these four modules share the arithmetic unit (execution unit) 36 including an adder / subtractor, a multiplier, a register file, etc. to convert data.

FIG. 4 is a block diagram for controlling the clock supplied to the module inside the raster block from the clock CLK2 supplied to the raster block 6 and the mode information 11 of n bits. 41 is CLK2 and mode information
11 is a clock supply control circuit for controlling the clock supplied to the module. Clock supply control circuit
Clocks CLKE and CLK for each module from 41
F and CLKG are supplied. The module in the raster block is a line generation module 42 that generates a line with dots between coordinate data, a filling module 43 that fills the inside of the outline of the character generated by the line generation module, and a dot memory control that expands the character. A dot memory control / clear module 44 for clearing the dot memory. In addition, these three modules share the execution unit 45 composed of an adder / subtractor, a register file, etc., and convert data.

Here, for example, in FIG. 3, when the mode information 11 is a mode in which the line width correction is not performed on the data input to the vector block, the clock supply control circuit 31 causes the line width correction module 31 to The clock CLKB is not supplied to 33. The same applies to other modules and the module in FIG.

Next, referring to FIG. 2, STBY1N and STBY2 input as the input terminals of the character generator 1 are input.
An example in which the supply of the clock is controlled by the N signal will be described. In this example, the clock supply is controlled for the relatively large module described above. The modules are vector block 4 and raster block 6, and the clock supply control circuit is CPU interface 2
It is supposed to be inside.

Table 1 shows the conversion mode information STBY1N and STBY2 when converting outline font data into dot font data in the character generator 1.
The figure shows the internal state of the character generator when input as an N signal and its processing contents.

[0039]

[Table 1]

When STBY1N = 1 and STBY2N = 1, the CPU interface 2 uses the vector block 4
Clock is supplied to both the raster block 6 and the raster block 6 to bring them into operation. The processing contents of the character generator 1 at this time execute normal processing in which both blocks function. When STBY1N = 0 and STBY2N = 1, the CPU interface 2 stops the clock supply to the vector block 4 and supplies the clock to the raster block. Therefore, the vector block is stopped and the raster block is operated. The processing contents of the character generator 1 at this time execute vector block transfer mode processing in which the vector block does not function. Also, STBY1N = 1, STBY2N =
When it is 0, the CPU interface 2 supplies the clock to the vector block 4, and the raster block 6
To stop the clock supply. Therefore, the vector block is in the operating state and the raster block is in the stopped state. The processing contents of the character generator 1 at this time are
Raster block does not work Perform raster block transfer mode processing. However, it supplies the minimum clock required for transfer. Also, STBY1N = 0, STBY
When 2N = 0, the CPU interface 2 stops the supply of clocks to both the vector block 4 and the raster block 6 and puts them in a stopped state. At this time, the processing content of the character generator 1 is in a standby state in which the functions of both blocks are stopped.

Next, in the character generator 1 shown in FIG. 2, the clock supply control until the valid data is input, during the valid data processing period, and after the processing is completed will be described. FIG. 5 shows a clock CLK supplied to the character generator 1 and input outline font data.
FIG. 3 is a block diagram showing a method of controlling a clock supplied from 51 to a module inside a character generation device. 52
Is a clock supply control circuit for controlling the clock CLK and the clock supplied to each module from the valid data 51 to be processed of the outline font data. The clock CLK1 and the clock CLK2 are supplied from the clock supply control circuit 52 to the module 1 53 and the module 254. Here, module 1 53 is vector block 4 and module 2 54 is raster block 6 as previously described.
The clock supply control circuit 52 is assumed to be inside the CPU interface 2. Here, the clock supply control circuit 52
When the valid outline data 51 to be processed of the input outline font data is detected, cancels the supply of the clock to the vector block 4 and the raster block 6 until then and supplies the clock. The vector block 4 and the raster block 6 sequentially process the input data, and after processing valid data,
The clock supply control circuit 52 stops the clock supply to the vector block 4 and the raster block 6. Further, the clock supply control method shown in FIG.
The same can be applied to the vector block and raster block shown in FIG. Furthermore, fine control is possible. For example, when the clock supply control circuit 31 shown in FIG. 3 detects the curve data of the input outline font data, it cancels the supply of the clock to the curve interpolation module 34 until then and supplies the clock. To do. When the curve data processing is completed, the clock supply is stopped again.

Finally, FIG. 6 shows the character generator shown in FIG.
Vector block 4 and raster block 6 in 1
FIG. 3 is a diagram for explaining a clock supply control method when data is transferred by a FIFO 5 connected between the two.

The data processed by the vector block 4 is written to the FIFO 5. At this time, the data is sequentially written by the write signal WRITE from the vector block 4. Therefore, when the FIFO 5 becomes full (full state), the FIFO 5 activates the write disable signal WRITE BUSY. This W
Receiving RITE BUSY, clock supply control circuit 61
Stops the supply of the clock CLKV to the vector block 4. When WRITE BUSY becomes inactive due to the reading of data from the FIFO 5, the clock supply is restarted.

Raster block 6 reads data from FIFO 5. At this time, the data is sequentially read by the read signal READ from the raster block 6. Therefore, when the FIFO 5 becomes empty (empty state), the FIFO 5 reads the read disable signal READ.
Activate BUSY. This READ BUS
Upon receiving Y, the clock supply control circuit 62 stops the supply of the clock CLKR to the raster block 6. Also, by writing data to FIFO 5, READ
When BUSY becomes inactive, clock supply is restarted.

[0045]

According to the present invention, in a character generator for converting outline font data composed of character contour information into dot font data, the power consumption of the character generator can be remarkably reduced.

Furthermore, the power consumption of the entire system using the character generator can be reduced.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a clock supply control system.

FIG. 2 is a block diagram of a character generator.

FIG. 3 is an explanatory diagram of a clock supply system in a vector block.

FIG. 4 is an explanatory diagram of a clock supply system in a raster block.

FIG. 5 is an explanatory diagram of a clock supply control method.

FIG. 6 is an explanatory diagram of a clock supply control system.

FIG. 7 is a system configuration diagram using a character generation device.

FIG. 8 is a block diagram of a character generator.

[Explanation of symbols]

1 ... Character generator, 2 ... CPU interface, 3 ... Font input FIFO, 4 ... Vector block, 5 ... FI
FO, 6 ... Raster block, 7 ... Dot memory, 12
… Clock supply control circuit.

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Kazuko Hasegawa 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa, Ltd. Microelectronics Devices Development Laboratory, Hitachi, Ltd. (72) Hiroshi Wada 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa House number Hitachi, Ltd. Microelectronics equipment development laboratory (72) Inventor Yuko Sato 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Prefecture Household number Hitachi Ltd. Microelectronics equipment development laboratory (72) Inventor Hiroaki Shirane Totsuka Yokohama, Kanagawa Prefecture 292 Yoshida-cho, Tokyo Stock company Hitachi Image Information Systems (72) Inventor Kazuhisa Nishimoto 292 Yoshida-cho, Totsuka-ku, Yokohama City, Kanagawa Stock company Hitachi Image Information Systems (72) Inventor Shigeo Hayashi Kamimizumoto-cho, Kodaira-shi, Tokyo 5 chome No. 20-1 Stock Company Hitachi Ltd. Semiconductor Division

Claims (5)

[Claims] 1. A character generator for converting outline font data composed of character contour information into dot font data, comprising a plurality of conversion modes, and a plurality of modules for executing the conversion designated by the mode. A character generation device configured to stop the function of a module that does not operate depending on the mode. 2. The character generator according to claim 1, wherein the mode information to be converted is stored in a register inside the character generator, and the function of the module that does not operate depending on the mode is stopped based on the mode information. Character generator. 3. The character generator according to claim 1 or 2, further comprising a plurality of standby terminals for converting mode information as a signal from the outside of the character generator, and stopping the function of the module which does not operate depending on the mode information. A character generator characterized by being. 4. The character generator according to claim 1, further comprising means for determining whether the input data is valid data to be processed, and valid data is input. Until, stop the function of each module,
A character generator characterized in that when valid data is input, the function of each module is activated, and when the processing of valid data is completed, the function of each module is stopped again. 5. The character generator according to claim 1, wherein data is transferred between the modules by a FIFO connected between the modules. The passing module is FI
When writing data to the FO, if the FIFO is full and cannot be written, or if the receiving module is F
When reading data from an IFO, if the FIFO cannot be read due to an empty state, a character generator is provided with a judging means for stopping the function of the module.