JPH0830251A - Vector character processor - Google Patents

Abstract

PURPOSE:To increase the efficiency of expansion processing of the vector character processor which sequentially expands the vector font of character information to be displayed and printed as to an information equipment which is applied with the vector font. CONSTITUTION:The vector character processor is equipped with an interface means 11 which stores characters inputted in dot form and supplies them to an output device for displaying or printing the characters, a processing means 13 which generates the vector font representing the individual characters constituting the character string to be displayed or printed, an expanding means 15 which performs expansion into the vector font generated by the processing means 13 and outputs the characters in dot form, and a read control means 17 which sequentially inputs the characters outputted by the expanding means 15 and supplies them to the interface means 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vector character processing apparatus for sequentially developing a vector font of character information to be displayed or printed in an information device to which a vector font is applied.

[0002]

2. Description of the Related Art In recent years, workstations, personal computers,
The spread of information devices such as word processors, electronic notebooks, etc.
The realization of a multi-font environment capable of displaying and printing various character information in arbitrary typefaces and sizes in response to various requests from users is being realized.

Conventionally, in an information device to which a dot font is applied, it is necessary to mount a memory in which a font corresponding to a size and a font of a character to be displayed or printed is stored in advance. It was not possible to realize a multi-font environment with sufficient quality because it could not meet the demand for power consumption and when the characters were enlarged, the outline of the typeface had large irregularities.

Therefore, in the information processing equipment that requires such a multi-font environment, a vector font indicating the vector indicating the direction of the line indicating the outline of each character and the coordinates indicating the position of the inflection point is stored in advance. By doing so, the amount of font information is suppressed, and a vector character processing device for developing such a vector font into characters having a desired dot number (point number) at the time of displaying or printing is installed.

FIG. 10 is a diagram showing a configuration example of a conventional vector character processing device. In the figure, the processor (CP
U) 71 is connected to the main memory 72, the display memory 73 and the print memory 74 via the first bus, and the vector character expansion circuit (hereinafter simply referred to as “expansion circuit”) via the second bus. It is connected to input / output of 75. Further, the display memory 73 is connected to the display device 76, and the print memory 74 is connected to the printer 77.

In the vector character processing device having such a configuration, the processor 71 determines the character to be displayed or printed based on the processing procedure of the application, etc., and enlarges, reduces or transforms the character as necessary. After performing the processing process described above, the data is stored in a buffer area pre-allocated in the storage area of the main memory 72 (FIG. 11). Further, the processor 71 reads the characters thus stored in the buffer area and gives them to the expansion circuit 75 (FIG. 11). The expansion circuit 75 has a FIFO at its input end.
In order to avoid such overflow of the input buffer and the output buffer, the expansion circuit has an input buffer of the method and an output buffer which can be randomly accessed from the outside, and the processor 71 in the above process. By monitoring the ready signal output to
A handshake is performed.

On the other hand, the expansion circuit 75, when the characters given by the processor 71 are accumulated in the input buffer as described above, expands them into dots and stores them in the output buffer based on predetermined addressing. Notify the processor 71 using an interrupt signal or the like (see FIG. 11).
).

When the processor 71 recognizes such a notification, it reads the dot-formed characters stored in the output buffer as described above and stores them in the display memory 73 (or the print memory 74) (FIG. 11). Further, the subsequent character to be displayed or printed is determined and stored in the buffer area on the main memory 72 (FIG. 11 ').

The expansion circuit 75 and the processor 71 will be described below.
For each character that makes up such a string,
The same processing (FIG. 11 ',', ...) Is repeated to complete the expansion processing relating to the desired character string.

Further, a display memory 73 and a print memory 74
The characters stored in are output to the corresponding display device 76 or printer 77.

[0011]

By the way, in such a conventional vector character processing device, the processor 71 is
As described above, the characters to be expanded are determined one by one based on the software, and after being subjected to the above-mentioned processing as needed, the expansion circuit 75 gives the characters which are further converted into dots by the expansion circuit. Was read and stored in the display memory 73 or the print memory 74. Further, the information amount of the characters dot-formed by the expanding circuit 75 was larger than the information amount of the character information given to the expanding circuit.

Therefore, the load on the processor 71 becomes large and the expansion circuit 75 waits until a subsequent character is given. Further, the processor 71 waits until the expansion circuit 75 completes the expansion process for the preceding character. There was no choice but to decrease the processing efficiency.

As a method of suppressing such a decrease in processing efficiency, there is a method in which a FIFO is provided at the output end of the expansion circuit 75 or built in. However, such a method
In order to read the dot characters while avoiding the overflow of the FIFO, hardware to detect the overflow is added, and the sequential processing is interrupted according to the interrupt signal output from the hardware. Since it is necessary to start priority processing, the hardware and software configurations are often complicated and cannot be applied.

An object of the present invention is to provide a vector character processing device which improves the efficiency of expansion processing.

[0015]

FIG. 1 is a block diagram showing the principle of the invention described in claim 1. In FIG. According to the first aspect of the present invention, the interface means 11 for accumulating the characters input in dot form and giving them to the output device for displaying or printing the characters, and the character string to be displayed or printed are configured. For each character, processing means 13 for generating a vector font indicating the character and expansion processing are performed on the vector font generated by the processing means 13,
It is characterized in that it is provided with a developing means 15 for outputting a dot-shaped character, and a reading control means 17 for successively taking in the characters outputted by the expanding means 15 and giving them to the interface means 11.

FIG. 2 is a block diagram showing the principle of the invention described in claim 2. The invention according to claim 2 is an interface means 11 for accumulating input characters which are dot-formed and giving them to an output device for displaying or printing the characters,
A process for accumulating a memory 21 and a vector font indicating each character constituting a character string to be displayed or printed in the memory 21, and outputting a command individually requesting the reading of these vector fonts. A means 23, a transfer means 25 for reading out a vector font stored in the memory 21 according to an instruction output by the processing means 23 and DMA-transferring it, and taking in the vector font DMA-transferred by the transfer means 25 and expanding the vector font. Expanding means 2 for outputting and dot-printed characters
7 and a read control means 29 for sequentially fetching the characters output by the developing means 27 and giving them to the interface means 11.

FIG. 3 is a block diagram showing the principle of the invention described in claim 3. According to a third aspect of the present invention, interface means 11 is provided for accumulating input characters which are dot-formed and which is provided to an output device for displaying or printing the characters,
With respect to the expansion means 31 that takes in a vector font input by the DMA transfer method, performs expansion processing, and outputs a dot-formed character, the memory 21, and individual characters that form a character string to be displayed or printed. , A vector font indicating the character is generated and stored in the memory 21, a command for individually requesting the reading of these vector fonts is output, and the characters output by the expansion means 31 are sequentially fetched and the interface means 11 is output.
And a transfer means 35 for reading out the vector font stored in the memory 21 according to a command output by the processing means 33 and supplying the vector font to the expanding means 31 by the DMA transfer method. .

[0018]

In the vector character processing device according to the invention described in claim 1, the processing means 13 generates a vector font indicating each character included in the character string, and the expanding means 15 individually outputs such a vector font. Outputs a dot-formed character after expansion processing. Further, the read control means 17 sequentially takes in the characters thus output and supplies them to the interface means 11, and the interface means 11 accumulates the characters and supplies them to an output device for displaying or printing the characters.

That is, for each character forming the above character string, a vector font is generated, the vector font is subjected to expansion processing, and further, the character dot-formed by the expansion processing is read and given to the output device. Since a series of processing is distributed to the processing means 13, the expansion means 15, the read control means 17 and the interface means 11 and is performed in parallel, these series of processing are serially performed under the control of a single processing means. The efficiency of the expansion process is improved as compared with the conventional example that has been performed.

In the vector character processing device according to the second aspect of the present invention, the processing means 23 generates a vector font showing each character included in the character string and generates the memory 21.
And outputs a command requesting individual reading of these vector fonts. The transfer means 25 reads the vector fonts stored in the memory 21 and DMA-transfers them in response to such a command, and the expansion means 27 takes in the vector fonts DMA-transferred in this way and individually expands them. Output dotted characters.
Further, the read control means 29 sequentially takes in the characters thus output and gives them to the interface means 11, and the interface means 11 gives the characters to the output device for displaying or printing the characters.

That is, for each character forming the above-mentioned character string, a vector font is generated, the vector font is subjected to expansion processing, and the dot-formed characters are read out and given to the output device by the expansion processing. Since a series of processing is distributed to the processing means 23, the transfer means 25, the expansion means 27, the read control means 29 and the interface means 11 and is performed in parallel, these series of processing are performed under the control of a single processing means. The efficiency of the expansion process is improved as compared with the conventional example in which the processes are performed in series.

In the vector character processing device according to the third aspect of the present invention, the processing means 33 generates the vector font showing the individual characters included in the character string to generate the memory 21.
And outputs a command requesting individual reading of these vector fonts. The transfer means 35 reads the vector font stored in the memory 21 in accordance with such an instruction and DMA-transfers it, and the expanding means 31 takes in the vector font DMA-transferred in this way and individually expands it. Output dotted characters.
Further, the processing means 33 sequentially takes in the characters thus output and supplies them to the interface means 11, and the interface means 11 accumulates the characters and supplies them to an output device for displaying or printing the characters.

That is, a process of generating a vector font for each character forming the above character string,
The process of reading the characters dot-shaped by the expansion process applied to the vector font is multiplexed by the processing means 33. In addition to these processes, the expansion process and the dot-shaped characters are output by the output device. Since a series of processing given to the above is distributed to the processing means 33, the transfer means 35, the expansion means 31, and the interface means 11 and performed in parallel, these series of processing are serially performed under the control of a single processing means. The efficiency of the expansion processing can be improved as compared with the conventional example that has been performed.

[0024]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 4 is a diagram showing an embodiment corresponding to the invention described in claim 1.

In the figure, parts having the same functions and configurations as those shown in FIG. 10 are designated by the same reference numerals, and the description thereof will be omitted here. This embodiment and FIG.
The difference in the configuration from the conventional example shown in FIG.
5 inputs. The output of the expansion circuit 75 is connected to an input / output bus formed separately from the first bus via a transfer circuit (bit built circuit) 42, and the input of the display memory 73 and the print memory 74 is input to the input / output bus. Are connected. The control output of the expansion circuit 75 is the sequencer circuit 43.
Is connected to the control input of the transfer circuit 42 via.

Regarding the correspondence between this embodiment and the block diagram shown in FIG. 1, the display memory 73 and the print memory 74 correspond to the interface means 11, and the processor 41 and the main memory 72 correspond to the processing means 13. ,
The expansion circuit 75 corresponds to the expansion means 15, and the transfer circuit 42 and the sequencer circuit 43 correspond to the read control means 17.

FIG. 5 is a diagram for explaining the operation of this embodiment. The operation of this embodiment will be described below with reference to FIGS. The processor 41 determines a character to be displayed or printed based on a processing procedure of an application, etc., and performs a processing process of enlarging, reducing, or transforming the character as necessary, and then, a storage area of the main memory 72. The data is stored in the buffer area previously allocated above (FIG. 5). Further, the processor 41 reads the characters thus stored in the buffer area and gives them to the expansion circuit 75 (FIG. 5). Note that the handshake performed between the processor 41 and the expansion circuit 75 in such a process is the same as in the conventional example, and therefore its description is omitted here.

When the characters provided by the processor 41 are accumulated in the input buffer in this way, the expanding circuit 75 develops them into dots and stores them in an internal output buffer based on predetermined addressing. Then (FIG. 5), a completion signal is transmitted (FIG. 5).

When the sequencer circuit 43 receives such a completion signal, it starts the transfer circuit 42 at a predetermined timing, and the transfer circuit 42 gives an address to the output buffer of the expansion circuit 75 based on the addressing described above. , The character stored in the output buffer is read and stored in the display memory 73 (or the print memory 74) (FIG. 5).

On the other hand, the processor 41 sequentially determines the subsequent characters to be displayed or printed while each stage from the expansion circuit 75 to the display memory 73 or the print memory 74 is performing the above-mentioned operation. The above-described processing is performed as necessary and stored in the buffer area allocated on the main memory 72 (FIG. 5 '), and subsequently given to the expansion circuit 75 based on the above handshaking procedure (FIG. 5'). .

Furthermore, the expansion circuit 75, the transfer circuit 42, the sequencer circuit 43, and the processor 41 perform the same processing (FIG. 5) on each character forming a desired character string.
The expansion processing is completed by a pipeline method in which ′ to ′, ...) Is repeated.

The display device 76 displays the vector characters stored in the display memory 73 based on the expansion processing as described above, and the printer 77 similarly prints and outputs the vector characters stored in the print memory 74.

As described above, according to this embodiment, the expansion circuit 7
The process of giving a character to be processed in 5 to the expansion process and the process of reading the character dot-formed by the expansion circuit and storing it in the display memory 73 or the print memory 74 are distributed to the processor 41 and the transfer circuit 42. Is performed in parallel, the load on the processor is reduced.

Therefore, as compared with the conventional example in which these processes are performed in series on the time axis, the time during which the expansion circuit 75 has to wait until the subsequent character to be expanded is given. Significantly shortened, the efficiency of the deployment process is improved.

FIG. 6 is a diagram showing an embodiment corresponding to the invention described in claim 2. In FIG. In the figure, parts having the same functions and configurations as those shown in FIG. 4 are designated by the same reference numerals, and the description thereof will be omitted here.

The difference between the present embodiment and the embodiment shown in FIG. 4 is that a DMA controller (DMAC) 51 is provided in place of the processor 41, and the DMA controller 51, together with the main memory 72, forms a first bus. A dedicated memory 53 is added to the output of the expansion circuit 75 and is connected in parallel between the dedicated memory 53 and the display memory 73 and the print memory 74 in place of the transfer circuit 42. Circuits 54 ₁ and 54 ₂ are provided, and the control output of the expansion circuit 75 and these transfer circuits 5 are provided.
4 _1, the sequencer circuit 43 is provided between the 54 _second control input
The sequencer circuit 55 in place of the above is provided.

Regarding the correspondence between this embodiment and the block diagram shown in FIG. 2, the display memory 73 and the print memory 74 correspond to the interface means 11, the main memory 72 corresponds to the memory 21, and the DMA controller 51.
Corresponds to the transfer means 25, and the processor 52 corresponds to the processing means 2
3, the expansion circuit 75 and the dedicated memory 53 correspond to the expansion means 27, and the transfer circuits 54 ₁ and 54 ₂ and the sequencer circuit 55 correspond to the read control means 29.

FIG. 7 is a diagram for explaining the operation of this embodiment. The operation of this embodiment will be described below with reference to FIGS. 6 and 7. The processor 52 determines a character to be displayed or printed on the basis of a processing procedure of an application, etc., and performs a processing process of enlarging, reducing, or transforming the character as necessary, and then, a storage area of the main memory 72. The data is stored in the buffer area previously allocated above (FIG. 7). Further, the processor 52 activates the DMA controller 51 by designating the address of such a buffer area (FIG. 7).

When activated in this manner, the DMA controller 51 temporarily occupies the first bus in place of the processor 52, autonomously reads the characters stored in the above-mentioned buffer area, and expands the circuit 75. (Fig. 7
). Note that the handshake performed between the DMA controller 51 and the expansion circuit 75 in such a process is the same as the conventional example, and therefore the description thereof is omitted here.

When the character thus provided is accumulated in the input buffer, the expanding circuit 75 expands it to form dots and store it in the dedicated memory 53 (FIG. 7), and sends a completion signal. (Fig. 7).

When such a completion signal is given, the sequencer circuit 55 transfers the transfer circuits 54 ₁ , 5 at a predetermined timing.
4 ₂ is activated, and the transfer circuit activated in this manner reads out the characters stored in the dedicated memory 53 while giving an address to the dedicated memory 53 based on a predetermined addressing, and displays it in the display memory 73. (Or stored in the print memory 74) (FIG. 7).

On the other hand, the processor 52 performs subsequent operations to be displayed or printed while each stage from the DMA controller 51 to the display memory 73 or the print memory 74 via the expansion circuit 75 is performing the above-described operation. The characters are sequentially determined, and the above-described processing is performed as necessary and stored in the buffer area (FIG. 7 ') to activate the DMA controller 51 (FIG. 7').

Further, the DMA controller 51, the expansion circuit 75, the dedicated memory 53, the transfer circuit 54 ₁ (54 ₂ ), the sequencer circuit 55, and the processor 52 perform the same processing (for each character forming the desired character string). Figure 7 '
The expansion processing is completed by a pipeline method in which ~ ', ...) are repeatedly performed.

The display device 76 displays the vector characters stored in the display memory 73 based on the expansion processing as described above, and the printer 77 similarly prints and outputs the vector characters stored in the print memory 74.

As described above, according to the present embodiment, the processing for determining the character to be expanded, the processing for giving the character to the expansion circuit 75, and the vector character dot-formed by the expansion circuit are The process of reading and storing in the display memory 73 or the print memory 74 is distributed to the processor 52, the DMA controller 51, and the transfer circuit 54 ₁ (54 ₂ ) and is performed in parallel, so that the embodiment shown in FIG. In comparison, the process of giving the expansion circuit 75 a character to be expanded is performed more efficiently.

Therefore, the time during which the expansion circuit 75 has to wait until a subsequent character to be expanded is given is greatly shortened, and the efficiency of the expansion process is improved. Further, in the processor 52, the expansion circuit 75
On the other hand, since the transfer processing for giving the character to be the expansion processing is performed by the DMA controller 51, the calculation for realizing such transfer processing is omitted and the software configuration is simplified.

In the above-described embodiment, for the plurality of transfer circuits 54 ₁ and 54 ₂ , for example, the display memory 73 is used.
When the dot-printed characters are given to the print memory 74 in parallel, they are individually assigned. However, since they are not directly related to the present application, the description thereof will be omitted here.

FIG. 8 is a diagram showing an embodiment corresponding to the invention described in claim 3. In FIG. In the figure, parts having the same functions and configurations as those shown in FIG. 6 are designated by the same reference numerals, and the description thereof will be omitted here.

The difference between the present embodiment and the embodiment shown in FIG. 6 is that the input / output bus is merged with the first bus, a processor 61 is provided instead of the processor 52, and the expansion circuit 7 is provided.
5 output and control output are dedicated memory 53, transfer circuit 5
It is connected to the input of the processor 61 without going through 4 ₁ , 54 ₂ and the sequencer circuit 55. Note that the display memory 73 and the print memory 74 are assigned addresses different from those of the main memory 72 in the address space.

Regarding the correspondence relationship between this embodiment and the block diagram shown in FIG. 3, the display memory 73 and the print memory 74 correspond to the interface means 11, and the expansion circuit 7 is provided.
Reference numeral 5 corresponds to the expansion means 31, main memory 72 corresponds to the memory 21, processor 61 corresponds to the processing means 33, and DMA controller 51 corresponds to the transfer means 35.

FIG. 9 is a diagram for explaining the operation of this embodiment. The operation of this embodiment will be described below with reference to FIGS. The processor 61 determines a character to be displayed or printed based on a processing procedure of an application, etc., and performs a processing process of enlarging, reducing, or transforming the character as necessary, and then, a storage area of the main memory 72. The data is stored in the buffer area previously allocated above (FIG. 9). Further, the processor 61 activates the DMA controller 51 by designating the address of such a buffer area (FIG. 9).

When activated in this manner, the DMA controller 51 temporarily occupies the first bus in place of the processor 61, autonomously reads the characters stored in the above-mentioned buffer area, and expands the circuit 75. (Fig. 9
). The handshake performed between the DMA controller 51 and the expansion circuit 75 in such a process is the same as that of the embodiment shown in FIG. 4, and therefore its explanation is omitted here.

When the character thus given is accumulated in the input buffer, the expanding circuit 75 develops it into dots, and stores it in a built-in output buffer based on predetermined addressing. (FIG. 9) Send a completion signal (FIG. 9).

The processor 61 recognizes such a completion signal as an interrupt factor, and specifies the input / output address assigned to the output buffer to the expansion circuit 75 in the process of priority processing activated by the interrupt factor. Meanwhile, the characters dot-stored in the output buffer are read out and stored in the display memory 73 (or the print memory 74) (FIG. 9).

On the other hand, the processor 61 itself reads the vector characters stored in the output buffer in the dot format as described above, while the DMA controller 51 and the expansion circuit 75 perform the above-described operation. The subsequent characters to be displayed or printed are sequentially determined during the period during which the process is performed, and the above-described processing is performed as necessary and stored in the buffer area on the main memory 72 (FIG. 9 '). The DMA controller 51 is activated (FIG. 9 ').

Further, the DMA controller 51, the expansion circuit 75, and the processor 61 perform the same processing (FIGS. 9'- ', FIG. 9'-', on each character forming a desired character string).
The expansion process is completed by a pipeline method that is repeatedly performed.

As described above, according to this embodiment, the character to be expanded is determined, the vector character dot-formed by the expansion circuit 75 is read and stored in the display memory 73 or the print memory 74, and The character is expanded circuit 7
5 is distributed to the processor 61 and the DMA controller 51 and is executed in parallel.
The process of giving the character to be the subject of the expansion process to 5 is performed more efficiently than in the conventional example.

Therefore, the hardware structure is simplified as compared with the embodiment shown in FIG. 6, and it is necessary to wait until the expansion circuit 75 gives a subsequent character to be expanded as compared with the conventional example. Time has been significantly reduced,
The efficiency of the expansion process is improved.

In the embodiment described above, the expansion circuit 75
Is connected to the input / output bus of the processor 61, but the present invention is not limited to such a configuration, and the processor 61 may be connected to the main memory 72, the display memory 73 and the print memory 7.
4 can be connected by disconnecting the first bus as in the case of these memories as long as it can be identified and referenced with certainty.

In each of the above-mentioned embodiments, the expansion circuit 7
In FIG. 5, characters to be expanded are given in units of coordinates indicating a vector font. However, the present invention is not limited to such a configuration, and expansion may be normally performed inside the expansion circuit 75. If it is guaranteed, for example, when the DMA controller 51 is used, either the burst transfer mode or the block transfer mode may be applied, and the information indicating such characters may be given in any order.

Further, in each of the above-described embodiments, the processors 41, 52, 61 are constituted by a single microprocessor, but the present invention is not limited to such a constitution.
For example, a multiprocessor configured based on the load distribution method or the function distribution method may be used.

[0062]

As described above, according to the first aspect of the invention, a vector font is generated for each character that constitutes a character string to be displayed or printed, and the vector font is expanded. Furthermore, a series of processes for reading out the characters dot-formed by the expansion process and giving them to the output device are distributed to the processing means, the expansion means, the read control means, and the interface means, and performed in parallel.

According to the second aspect of the invention, the series of processes described above are distributed to the processing means, the transfer means, the expansion means, the read control means and the interface means and are performed in parallel.

Further, in the invention described in claim 3, the processing means multiplexes the processing for generating the vector font and the processing for reading out the characters dot-formed by the expansion processing applied to the vector font. However, a series of processes including these processes are distributed to the processing means, the transfer means, the expansion means, and the interface means, and are performed in parallel.

Therefore, in these inventions, as compared with the conventional example in which the series of processes described above are performed in series under the control of a single processing means, the efficiency of the expansion process is improved and display or printing is performed. In addition, in the information processing device to which the present invention is applied, the efficiency of the man-machine interface is improved and the operation efficiency and performance are improved.

[Brief description of drawings]

FIG. 1 is a principle block diagram of the invention according to claim 1.

FIG. 2 is a principle block diagram of the invention described in claim 2.

FIG. 3 is a principle block diagram of the invention according to claim 3;

FIG. 4 is a diagram showing an embodiment corresponding to the invention described in claim 1.

FIG. 5 is a diagram for explaining the operation of this embodiment.

FIG. 6 is a diagram showing an embodiment corresponding to the invention described in claim 2.

FIG. 7 is a diagram for explaining the operation of this embodiment.

FIG. 8 is a diagram showing an embodiment corresponding to the invention described in claim 3;

FIG. 9 is a diagram for explaining the operation of this embodiment.

FIG. 10 is a diagram showing a configuration example of a conventional vector character processing device.

FIG. 11 is a diagram illustrating an operation of a conventional vector character processing device.

[Explanation of symbols]

 11 Interface Means 13, 23, 33 Processing Means 15, 27, 31 Development Means 17, 29 Read Control Means 21 Memory 25, 35 Transfer Means 41, 52, 61, 71 Processor (CPU) 42, 54 Transfer Circuits 43, 55 Sequencer Circuit 51 DMA controller (DMAC) 53 Dedicated memory 72 Main memory 73 Display memory 74 Printing memory 75 Vector character expansion circuit 76 Display device 77 Printer

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display area // G06F 17/21

Claims (3)

[Claims] 1. Interface means for accumulating dot-input characters and providing them to an output device for displaying or printing the characters, and individual characters constituting a character string to be displayed or printed. A processing means for generating a vector font indicating the character, a developing means for performing a developing process on the vector font generated by the processing means, and outputting a dot-formed character; and a character output by the developing means. And a read control means for sequentially fetching and supplying the interface means to the interface means. 2. An interface means for accumulating dot-input characters and giving them to an output device for displaying or printing the characters, a memory, and a character string to be displayed or printed. For each character, a vector font indicating the character is stored in the memory, and processing means for outputting a command individually requesting the reading of these vector fonts, and the memory according to the command output by the processing means Transfer means for reading out the vector font stored in the memory and performing DMA transfer, expanding means for taking in the vector font DMA-transferred by the transfer means, performing expansion processing, and outputting dot characters, A read control hand that sequentially captures the output characters and gives them to the interface means. Vector character processing apparatus characterized by comprising and. 3. Interface means for accumulating dot-formed input characters and giving them to an output device for displaying or printing the characters, and taking in vector fonts input by a DMA transfer method and performing expansion processing, A developing unit for outputting a dot-shaped character, a memory, and for each character constituting the character string to be displayed or printed, a vector font indicating the character is generated and stored in the memory, In addition to outputting a command individually requesting the reading of these vector fonts, a processing unit that sequentially captures the characters output by the expansion unit and gives them to the interface unit, and the processing unit according to the command output by the processing unit The vector font stored in the memory is read out and the DMA transfer method is applied to the expansion means. Vector character processing apparatus characterized by comprising a transfer means for providing a.