JPH06318394A - Memory control device - Google Patents

Abstract

PURPOSE:To obtain a memory control device which can reduce current consumption of a DRAM by preventing useless current consumption of a DRAM, at the time of initialization of both power supplies of a DRAM and a control circuit. CONSTITUTION:A control circuit 2 and a logic gate circuit 5 set a RAS/CAS signal to an active state at the time of cut off of a power supply of a VCC (power supply for control) 4. The logic gate circuit 5 sets the RAS/CAS signal to a non-active state in a period from a point of time of initialization of a BVCC (backup power supply) 3 to turning on of power supply of the VCC 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a self-refresh type dynamic R used in a computer system.
The present invention relates to an AM, and particularly to a memory control device having a function of executing a control operation at the time of backup.

[0002]

2. Description of the Related Art Conventionally, for example, a computer system such as a personal computer has an I such as a random access memory (RAM) or a read only memory (ROM).
A large amount of C memory is used. In particular, a dynamic RAM (DRAM) is an important IC memory used as a main memory that requires a large storage capacity.

DRAM is a static RAM (SRA).
Unlike M), refreshing which is a rewriting operation is necessary. As a refresh method, a self-refresh method that is effective for backup that occurs when the main power supply is cut off is well known.

In the self-refresh system, the RAS / CAS signal from the control circuit is activated so that the DRAM automatically refreshes. Here, the RAS / CAS signal is in the active state at the logic level "L" as shown in FIG. Also,
The self-refresh method uses a CAS before RAS refresh cycle. That is, this is a method in which the CAS signal is activated before the RAS signal.

By the way, when the DRAM is backed up, the backup power supply (BVCC) is supplied to the DRAM and the control power supply (VCC) of the control circuit is cut off. The control circuit sets the RAS / CAS signal to the active state when VCC is cut off. As a result, the DRAM can carry out self-refresh and hold the written data as described above. At this time, the control circuit maintains the active state of the RAS / CAS signal until the self-refresh is released even if VCC is applied.

In such a backup control system, B
When performing both VCC and VCC power supply initialization,
Even if the DRAM is not in the self-refresh state, the control circuit sets the RAS / CAS signal to the active state. Here, the initialization of the power source is an operation of bringing the power source from the cut-off state to the closed state.

[0007]

Conventionally, in the backup control of the DRAM of the self-refresh type, when the power supplies of both BVCC and VCC are initialized, the RAS /
The CAS signal is set to the active state. For this reason,
The DRAM executes a circuit operation corresponding to self-refresh, resulting in useless current consumption.

An object of the present invention is to provide a memory control device capable of reducing the current consumption of the DRAM by preventing wasteful current consumption of the DRAM at the time of initializing the power supplies of both the DRAM and the control circuit. Especially.

[0009]

According to the present invention, in a memory control device for controlling a self-refresh type DRAM, backup power supply means for supplying backup power to the DRAM, timing generation means for generating a RAS / CAS signal, The apparatus is provided with a control power supply means for supplying power to the timing generation means and a control means for controlling the RAS / CAS signal.

[0010]

According to the present invention, the control means sets the RAS / CAS signal to the active state when the control power supply means is shut off, and during the period from the initialization of the backup power supply means to the turning on of the control power supply means. Set the RAS / CAS signal to the inactive state.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. 1 is a block diagram showing a main part of a DRAM memory control device according to the embodiment, and FIG. 2 is a block diagram showing a concrete circuit configuration of a control circuit 2 and a logic gate circuit 5 according to the embodiment. .

This apparatus comprises a DRAM device 1, a control circuit 2, a backup power supply (BVCC) 3, and a control power supply (V
CC) 4 and a logic gate circuit 5. The DRAM device 1 is a self-refresh type DRAM,
At the time of backup, self refresh is executed by the power supply of BVCC3.

The control circuit 2 is a circuit for controlling the operation of the DRAM device 1, and is an R required for self refresh.
Outputs AS / CAS signal. The control circuit 2 is VCC4.
It is operated by the power supply of, and the power supply is cut off during backup. The logic gate circuit 5 is a circuit for controlling the RAS / CAS signal from the control circuit 2 during backup control.

The control circuit 2, as shown in FIG.
Timing generation circuit 10 for generating / CAS signal
Have. The logic gate circuit 5 includes the VCC voltage detection circuit 1
1a, 11b, BVCC voltage detection circuit 12, flip-flop 13 and NAND circuits 14-17.

The VCC voltage detection circuit 11a outputs a detection signal of logic level "L" when the voltage of VCC4 drops below a reference value. The VCC voltage detection circuit 11a has V
This is a circuit for controlling hazards by controlling the gates of the NAND circuits 14 and 15 when CC4 is cut off. On the other hand, V
The CC voltage detection circuit 11b is a circuit that outputs the reset signal R of the flip-flop 13 when the power of the VCC4 exceeds the reference value and the power is turned on. BVCC voltage detection circuit 1
2 is a flip-flop 13 when the power of BVCC3 is turned on.
Is a circuit for outputting the set signal S of. The flip-flop 13 includes NAND circuits 13a and 13b, and outputs an inverted signal (Q bar) for controlling the gates of the NAND circuits 16 and 17.

Next, the operation of the embodiment will be described. First,
At the time of backup, the DRAM device 1 is BVCC3
Power is supplied from. At this time, the power supply of VCC4 is in the cutoff state. When the power of VCC4 is cut off, the VCC voltage detection circuit 11a outputs a detection signal of logic level "L". Further, the timing generation circuit 10 sets the RAS / CAS signal to the active state (logic level “L”) when the power of the VCC4 is cut off.

The flip-flop 13 has BVCC3 and V
When both CC4 are turned on, the BVCC voltage detection circuit 12
Since the output signals of the logic level "L" are input from both the Vcc voltage detection circuit 11b and the VCC voltage detection circuit 11b,
The output signal (Q bar) is output. After this, BVC
Since the respective output signals of the C voltage detection circuit 12 and the VCC voltage detection circuit 11b become the logic level "H", the output signal (Q bar) of the logic level "H" of the flip-flop 13 does not change.

Therefore, at the time of backup, the NAND circuits 16 and 17 activate the RAS / CAS in the active state.
Signals are supplied to the DRAM device 1. As a result, the DRAM device 1 executes the self-refresh at the time of backup and holds the written data.

Here, both BVCC3 and VCC4 are initialized. That is, the power supplies of BVCC3 and VCC4 are switched from the cut-off state to the turned-on state. By shutting off the power supply of BVCC3, the DRAM device 1 is in a state where self refresh is not executed.

In this state, when the power of the BVCC 3 is turned on, the BVCC voltage detection circuit 12 detects that the power is turned on,
A set signal S, which is an output signal of logic level "L", is output. Therefore, in the flip-flop 13, the output signal (Q bar) changes to the logic level "L". As a result, the NAND circuits 16 and 17 make the RAS / CAS signal inactive at the logic level "H".

When the power of VCC4 is turned on,
The VCC voltage detection circuit 11b detects power-on and outputs a reset signal R which is an output signal of logic level "L". Therefore, in the flip-flop 13, the output signal (Q bar) changes to the logic level "H". As a result, the NAND circuits 16 and 17 make the RAS / CAS signal active at the logic level "L".

In this way, during normal backup, the DRAM device 1 carries out self-refreshing by the power supply of BVCC3 and the RAS / CAS signal in the active state, and holds the written data. On the other hand, when both BVCC3 and VCC4 are initialized, VC is started from the time of initialization of BVCC3 (when the power is turned on).
Until the power of C4 is turned on, the RAS / CAS signal is the output signal (Q
Bar) forces it to become inactive.

Therefore, at the time of initializing BVCC3 and VCC4, the DRAM device 1 has the R in the active state.
Since the AS / CAS signal is not supplied, useless current consumption does not occur without executing self refresh.

[0024]

As described above in detail, according to the present invention, the RAS / CAS signal is forced when the power supply is initialized for both BVCC and VCC during the backup control of the self-refresh type DRAM. Can be set to inactive state. Therefore, it is possible to prevent unnecessary current consumption due to unnecessary self-refresh at the time of initialization, and consequently reduce the current consumption of the DRAM.

[Brief description of drawings]

FIG. 1 is a block diagram showing a main part of a DRAM memory control device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a specific circuit configuration of a control circuit 2 and a logic gate circuit 5 according to the same embodiment.

FIG. 3 is a timing chart for explaining a self-refresh system of a conventional DRAM.

[Explanation of symbols]

1 ... DRAM device, 2 ... Control circuit, 3 ... Backup power supply (BVCC), 4 ... Control power supply (VCC), 5 ...
Logic gate circuit, 10 ... Timing generation circuit, 11a,
11b ... VCC voltage detection circuit, 12 ... BVCC voltage detection circuit, 13 ... Flip-flop, 14-17 ... NAND circuit.

Claims (2)

[Claims] 1. A memory control device for controlling a dynamic RAM of a self-refresh type, wherein a backup power supply means for supplying a backup power supply to the dynamic RAM and a RAS / CAS for executing a self-refresh operation of the dynamic RAM. Timing generation means for generating a signal, control power supply means for supplying power to the timing generation means, and the RAS / CAS signal is set to an active state when the control power supply means is shut off, and the backup power supply means is set. A memory control device comprising: a control unit that sets the RAS / CAS signal to an inactive state during a period from the time of initialization to the time when the control power supply unit is turned on. 2. A memory control device for controlling a dynamic RAM of a self-refresh type, comprising: backup power supply means for supplying backup power to the dynamic RAM; and RAS / CAS for executing a self-refresh operation of the dynamic RAM. Timing generation means for generating a signal, control power supply means for supplying power to the timing generation means, and first power-on detection for the backup power supply means
Power source detecting means, second power source detecting means for detecting power-on of the control power source means, and the control power source means when the control power source is shut off based on the detection results of the first and second power source detecting means. Control means for setting the RAS / CAS signal to an active state and setting the RAS / CAS signal to an inactive state during a period from the time when the backup power supply means is initialized to the time when the control power supply means is turned on; A memory control device comprising: