JPH06315270A - Output circuit for pwm inverter - Google Patents

Abstract

PURPOSE:To reduce the control error and power consumption of the output circuit by constituting a first and second IGBTs in such a way that the IGBTs are not substantially turned on at the same time and their safety can be secured, and then, the floating time can substantially become '0'. CONSTITUTION:The gate of a first N-channel IGBT l is connected to the emitter of a second P-channel IGBT 2 so that the potential difference between a gate signal voltage 50 and motor winding terminal voltage 51 can fall within a fixed range and no shortcircuit state can be generated between the (+) and (-) terminals of a main DC power source due to simultaneous flow of electric currents to the IGBTs 1 and 2. When a motor releasing signal 156 instructs a low level, NAND means 106 and 107 become high in level irrespective of a switching command signal 42 and the base signals 123 and 29 of a PNP transistor 119 and transistor 29 respectively become high and low in level. As a result, the gate signal voltage of the IGBTs 1 and 2 becomes the same potential as the terminal voltage 51 through a resistor 105 and the IGBTs 1 and 2 are set to freely running states. When the signal 156 instructs a high level, the IGBTs 1 and 2 are shifted to another states.

Description

Detailed Description of the Invention

[0001]

The present invention relates to the coil voltage of an electric motor,
The present invention relates to a power circuit of a PWM inverter for WM control. PWM is a Pulse Width Mod
It is an abbreviation for "Ulation" and is a technique widely used in the field of motor control.

[0002]

2. Description of the Related Art In recent years, PWM inverters have rapidly spread and are widely used for motor control.

FIG. 18 is a schematic diagram showing the structure of a general PWM inverter, and shows a three-phase PWM inverter as an example. Generally, in the PWM inverter, the number of output circuits 53 for the PWM inverter differs depending on the number of phases of the motor used, but the basic operation is the same.

The structure of a general three-phase PWM inverter will be described with reference to FIG. First, the frequency voltage setting means 58
The basic frequency and the effective voltage value of the three-phase AC voltage waveform supplied to the electric motor 60 are set at. Next, the PWM control circuit 59
Generates a three-phase PWM signal internally based on the information set in the frequency voltage setting means 58 and outputs it as switching command signals 42, 61 and 62. The switching command signals 42, 61 and 62 are applied to the motor winding terminal 5
It is a binary signal for instructing whether 2, 63 and 64 are connected to the positive terminal or the negative terminal of the DC main power supply 14, respectively. The frequency of the switching command signal 42, 61, or 62 is called the PWM carrier frequency, and takes a value 10 times or more the basic frequency of the three-phase AC voltage waveform normally supplied to the electric motor 60.

Generally, the three-phase AC voltage waveform supplied to the motor has a fundamental frequency of about 0 Hz to 200 Hz and a PWM carrier frequency of about 2 kHz to 20 kHz. The electric motor release signal 156 is a binary signal that gives an instruction as to whether or not the electric motor should be in the free-run state. The free-run state is a state in which all of the motor winding terminals 52, 63 and 64 are not connected to either the positive terminal or the negative terminal of the DC main power supply 14, and when some trouble occurs, this state is set, and the motor and the control are controlled. It is common to protect the device.

The PWM inverter output circuit 53 is a semiconductor switch circuit for controlling connection of the motor winding terminal 52, 63 or 64 to the plus or minus terminal of the DC main power supply 14 according to the switching command signal 42, 61 or 62. . Also, the motor release signal 15
6 is instructing the free running state, the motor winding terminal 52 or 63 or 64 is connected to the DC main power source 1 regardless of the switching command signal 42, 61 or 62.
It is configured so as not to be connected to the positive terminal or the negative terminal of No. 4. Generally, the main DC power supply is a DC140V rectified and smoothed AC100V or AC200V.
Most of them are DC 280V that is rectified and smoothed.

A conventional output circuit for a PWM inverter will be described below. FIG. 19 shows a configuration of a conventional PWM inverter output circuit.

In FIG. 19, a logic inverting means 65 inverts the positive / negative logic of the switching command signal 42 and outputs an inverted switching signal 80. 157 and 158 are AND means, which are the motor release signal 156 and the switching command signal 4
The result of logical product of 2 is the upper arm switching signal 1
59, and the result of taking the logical product of the motor release signal 156 and the inverted switching signal 80 is output as the lower arm switching signal 160.

Reference numerals 66 and 67 denote on-delay circuits, which output the upper arm control signal 81 or the lower arm control signal 82 by delaying the rising edges of the upper arm switching signal 159 and the lower arm switching signal 160 respectively by the on delay time TD. 68 and 69 are base drive circuits, 68 is for turning on or off the power transistor 70 in response to the upper arm control signal 81, and 69 is for turning on or off the power transistor 71 in response to the lower arm control signal 82. It is configured.

That is, the upper arm control signal 81 is "H".
When the level becomes high, the output transistor of the photocoupler 72 becomes O.
N, which turns on the transistor 74, which turns off the transistor 76, turning on the power transistor 70. On the contrary, when the upper arm control signal 81 becomes the “L” level, the output transistor of the photocoupler 72 is turned off, which turns off the transistor 74.
Then, the transistor 76 is turned on, and the power transistor 70 is turned off.

[0011] This base drive circuit is also used in the actual development 5
There are those described in Japanese Patent Application Laid-Open No. 7-42589 and Japanese Patent Application Laid-Open No. 59-178980, but basically the same operation as the base drive circuits 68 and 69 shown in FIG.

The operation of the PWM inverter output circuit configured as described above will be described below.

First, considering the case where the motor release signal 156 is instructing the "L" level, that is, the free-run state, the power transistor 70 and the power transistor 70 are in both the "L" level and the "H" level of the switching command signal 42. It can be seen that 71 is in the OFF state.

Hereinafter, the case where the motor release signal 156 is instructing the "H" level, that is, the state in which the motor is not free running will be described.

FIG. 20 is a diagram showing signals inside the output circuit for the PWM inverter shown in FIG. 19. First, when the switching command signal 42 changes from the'L 'level to the'H' level, the on-delay circuit 66 turns on-delay. The upper arm control signal 81 is changed from “L” level to “H” with a delay of time TD.
Change to a level. When the upper arm control signal 81 is set to the “H” level, the power transistor 70 is turned on, but there is an operation delay time TX1 of the base drive circuit 68 and the power transistor 70 between them. The operation delay time TX1 changes depending on the temperature of the power transistor 70 and the change of the current value flowing through the collector, and also changes due to variations and secular changes of the components forming the base drive circuit and the power transistor.

Further, the switching command signal 42 is "L".
When the level changes to the'H 'level, the inverted switching signal 80 changes from the'H' level to the'L 'level,
The on-delay circuit 67 sets the lower arm control signal 82 to the'L 'level with almost no time delay. When the lower arm control signal 82 is set to the “L” level, the power transistor 71
Is turned off, but there is an operation delay time TY2 of the base drive circuit 69 and the power transistor 71 in the meantime. This operation delay time TY2 depends on the power transistor 71.
Fluctuates due to changes in the temperature of the
It also changes due to variations and aging of the components that make up the base drive circuit and power transistors.

Next, when the switching command signal 42 changes from the "H" level to the "L" level, the on-delay circuit 66 sets the upper arm control signal 81 to the "L" level with almost no time delay, and the power transistor 70 is turned off. However, there is an operation delay time TY1 of the base drive circuit 68 and the power transistor 70 between them.

Further, the switching command signal 42 is "H".
When the level changes to the'L 'level, the inverted switching signal 80 changes from the'L' level to the'H 'level,
The on-delay circuit 67 changes the lower arm control signal 82 from the “L” level to the “H” level with a delay of the on-delay time TD. When the lower arm control signal 82 is set to the'H 'level, the power transistor 71 is turned on, but there is an operation delay time TX2 between the base drive circuit 69 and the power transistor 71 in the meantime.

When the operation delay time TX1 or the operation delay time TX2 is compared with the operation delay time TY1 or the operation delay time TY2, the operation delay time TY1 or TY2 is generally longer than the operation delay time TX1 or TX2. Tend. The shortest value of the operation delay time TX1 and the operation delay time TX2 considering the worst condition is TXW, and the operation delay time TY1 and the operation delay time T are set.
When the longest value of Y2 in consideration of the worst condition is TYW, the normal on-delay time TD is set to a value obtained by subtracting TXW from TYW with some margin.

Usually, the on-delay time TD is 10 to 5 for a bipolar type power transistor.
The time is set to about 0 microseconds, the one using an IGBT is set to about 5 to 30 microseconds, and the one using a MOS type power MOS-FET is set to about 2 to 10 microseconds. As a result, when the switching command signal 42 changes from the “H” level to the “L” level or from the “L” level to the “H” level, the power transistor 70 and the power transistor 71 are turned on at the same time. The positive terminal and the negative terminal of the main power supply 14 are prevented from being short-circuited.

From the above, considering the switching command signal 42 and the state of the motor winding terminal voltage 51,
First, when the switching command signal 42 is fixed at the “L” level, the power transistor 70 is in the OFF state and the power transistor 71 is in the ON state, so the motor winding terminal 52 is connected to the negative terminal of the DC main power supply 14. In addition, when the switching command signal 42 is fixed at the "H" level, the power transistor 7
Since 0 is ON and the power transistor 71 is OFF, the motor winding terminal 52 is connected to the positive terminal of the DC main power supply 14.

[0022]

However, in the above-mentioned conventional configuration, when the motor release signal 156 is instructing the "H" level, that is, the state in which the motor is not free running, the switching command signal 42 changes from the "L" level to the "L" level. When the H'level is changed or the'H 'level is changed to the'L' level, both the power transistor 70 and the power transistor 71 are turned off for a certain period of time, which causes voltage control of the motor winding terminal 52. Control error. This control error has a problem in that it causes fluctuations in torque and rotational speed of the electric motor, and also increases noise and vibration of the electric motor.

This will be described in more detail. 19 and 20, the switching command signal 42 is'L '.
When the level changes to the “H” level or when the “H” level changes to the “L” level, the power transistor that has been turned on is first turned off and then the power transistor that has been turned off is turned on. Therefore, both the power transistor 70 and the power transistor 71 are turned off for a certain period of time. This state is called a floating state, and this time is called a floating time TZ. Generally, the floating time TZ is often about 1/2 to 2/3 of the on-delay time TD.

Generally, the PWM control of an electric motor is essentially such that the electric motor winding terminals are alternately connected to the positive terminal and the negative terminal of the DC main power supply, and the ratio of the time of connecting to the positive terminal to the time of connecting to the negative terminal is set. Accordingly, the average voltage of the motor winding terminals is controlled. Therefore,
It is ideal that the average voltage of the motor winding terminal 52 can be uniquely controlled according to the time ratio of the “H” level and the “L” level of the switching command signal 42 when the voltage of the DC main power supply 14 is constant. Is.

However, in the conventional output circuit for the PWM inverter, since the floating state exists, the average voltage of the motor winding terminal varies depending on the direction of the current flowing through the motor winding terminal. That is, the motor winding terminal 5
The diode 78 becomes conductive when the current is flowing in the direction in which the current flows into the PWM inverter output circuit 53 from 2 and the motor winding terminal 52 is connected to the positive terminal of the DC main power supply 14. Becomes
This state is shown by the motor winding terminal voltage 51A in FIG.

On the contrary, in the floating state, PWM
When current flows from the inverter output circuit 53 to the electric motor winding terminal 52, the diode 79 conducts and the electric motor winding terminal 52 is connected to the negative terminal of the DC main power supply 14. This state is shown in the motor winding terminal voltage 51B of FIG. Further, in the floating state, when no current flows in the motor winding terminal 52, the voltage of the motor winding terminal 52 becomes a voltage determined by the induced voltage generated inside the motor 60.

As described above, the switching command signal 42 and the motor winding terminal 52 are present because of the floating state.
The average voltage of is not uniquely determined and causes a control error. Normally, the current flowing through the motor winding terminal 52 is an alternating current, and the direction of the current changes. Therefore, the control error also changes accordingly, and the torque generated or the rotation speed of the motor 60 fluctuates. Although this problem can be solved by eliminating the floating state and setting the floating time to 0, in the conventional output circuit for the PWM inverter, a short-circuited state between the plus terminal and the minus terminal of the DC main power supply 14 occurs, which is actually impossible. is there.

Further, electric noise is generated when the power transistor is turned on or off, and particularly in applications where it is desired to reduce it, the switching speed is slowed by connecting a capacitor between the base and emitter of the power transistor. There are cases. However, this causes the operation delay times TX1, TX2, TY1 and TY2.
The fluctuations of the above will become so large that the floating time must be increased further. Therefore, the control error becomes large, and as a result, the switching speed cannot be reduced so much.

Further, the output circuit for the conventional PWM inverter of the type in which the power transistor 70 and the power transistor 71 in FIG. 19 are replaced with IGBTs respectively, and FIG.
There is also a conventional PWM inverter output circuit in which the power transistor 70 and the power transistor 71 are replaced with power MOS-FETs, but the operation is exactly the same as that of the PWM inverter output circuit shown in FIG. 19 and has a floating state. .

An object of the present invention is to solve the above problems. The floating state is essentially eliminated, the floating time is zero, and the switching command signal and the average voltage of the motor winding terminals are uniquely determined. Accordingly, it is an object of the present invention to provide a PWM inverter output circuit that does not cause a control error and consumes less power at low cost.

[0031]

In order to achieve this object, a PWM inverter output circuit according to the present invention comprises an N-channel type first IGBT, a P-channel type second IGBT, a first and a second IGBT. 2, a current control means 1 having a current output terminal for controlling a current flowing out from the current output terminal, and a current control means 2 having a current input terminal for controlling a current flowing in from the current input terminal.
And a DC main power supply, and connecting the collector of the first IGBT, the cathode of the first diode and the positive terminal of the DC main power supply, and the collector of the second IGBT, the anode of the second diode and the DC The negative terminal of the main power source is connected, the emitter of the first IGBT, the anode of the first diode, the emitter of the second IGBT and the cathode of the second diode are connected, and the gate of the first IGBT and the second IGBT are connected.
The gate of the IGBT, the current output terminal of the current control means 1 and the current input terminal of the current control means 2 are connected,
Alternatively, a resistor and a voltage limiter having a Zener phenomenon for positive and negative bidirectional voltages are connected in parallel between the gate and the emitter of the second IGBT.

[0032]

With this structure, the first and second IGBTs are essentially safe because they are not simultaneously turned on, and the floating time is essentially 0, so that the control error is very small and the power consumption is low. A PWM inverter output circuit with less power consumption can be realized.

[0033]

【Example】

(Embodiment 1) An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, 1 is an N-channel type IGBT, 2 is a P-channel type IGBT, 5 and 6 are diodes, 125 and 126 are current control means, 109 is a signal processing means, 14 is a DC main power supply, and 15 Reference numerals 16 and 16 denote a DC power source, reference numeral 105 denotes a resistor, reference numeral 97 denotes a voltage limiter, which is composed of Zener diodes 95 and 96.

The operation of the PWM inverter output circuit configured as described above will be described.

Reference numeral 65 is a logic inverting means, which inverts the result of logically inverting the switching command signal 42.
Output as 0. Reference numerals 106 and 107 denote logical product negating means, 106 outputs a result of taking the logical product negation of the motor release signal 156 and the inverted switching signal 80, and 107 takes the logical product negation of the motor release signal 156 and the switching command signal 42. Output the result.

To simplify the explanation, all the cases in which the motor release signal 156 commands the "H" level, that is, the state where the motor is not free running, will be described. Finally, the motor release signal 156 will be "L". I will add a description of the case where the level, that is, the free-run state is commanded.

First, the operation of the current control means 125 and the current control means 126 will be described in detail with reference to FIG.

The base signal 123 of the PNP type transistor 119 generates the switching command signal 42 through the logical product negating means 107, the photocoupler 115 and the logical inverting means 111. The base signal 123 has, for example, the same potential as the plus terminal of the DC power supply 15 when the switching command signal 42 is at the “L” level, and has a potential 5 V lower than the plus terminal of the DC power supply 15 when at the “H” level.

Next, a P-channel type MOS-FE
The gate signal 124 of T120 is the switching command signal 4
2 is generated through the logical product negating means 107, the photocoupler 115, the logical inverting means 112 and 113, and the signal delay means 114. This gate signal 124 is obtained by delaying the switching command signal 42 by the delay time TA, and is'L '.
The level is set to a voltage that can sufficiently turn on the MOS-FET 120, and the “H” level is set to the MOS-FET 12
The voltage is set so that 0 can be sufficiently turned off.

The transistor 119 has an emitter follower type circuit configuration, and the potential of the base signal 123 is the DC power source 1.
When it becomes lower than the potential of the positive terminal of No. 5 by about 0.7 V or more, a current determined by the value of the resistor connected to the emitter and the voltage applied thereto flows as a collector current 49, and the potential of the base signal 123 and the DC power supply 15 are reduced. When the difference from the positive terminal potential is about 0.7 V or less, the collector current 49 becomes zero.

The MOS-FET 120 is the transistor 11
When the MOS-FET 120 is turned on in the state where the potential of the base signal of the transistor 119 is lower than the potential of the plus terminal of the DC power source 15 by about 0.7 V or more, it functions to switch the value of the resistor connected to the emitter of the transistor 9. It has the effect of increasing the collector current 49 of the transistor 119.

Considering the relationship between the switching command signal 42 and the collector current 49, the collector current 49 is 0 when the switching command signal 42 is at the “L” level.
Then, next, the collector current 49 has a relatively large current value until the delay time TA elapses after the switching command signal 42 changes to the “H” level, and then has a relatively small current value. Becomes "L" level, the collector current 49 becomes zero.

Further, the base signal 45 of the NPN type transistor 29 causes the switching command signal 42 to be generated through the logical inversion means 65 and 23 and the logical product negation means 106. The base signal 45 is substantially the same as the signal obtained by logically inverting the switching command signal 42, and the value of the'L 'level is 0V and the value of the'H' level is 5V, for example.

Next, N-channel type MOS-FE
The gate signal 46 of T31 converts the switching command signal 42 to the logical inversion means 65, 24 and 25 and the logical product negation means 1.
06 through the signal delay means 27.

The gate signal 46 is obtained by delaying the switching command signal 42 by the delay time TB. The "L" level is set to a voltage that can sufficiently turn off the MOS-FET 31, and the "H" level is set to the MOS-FET 31. It should be a voltage that can be sufficiently turned on.

The transistor 29 has an emitter follower type circuit configuration, and when the base signal 45 becomes about 0.7 V or more, a collector current 48 determined by the voltage of the base signal 45 and the value of the resistance connected to the emitter flows, and the base signal 45. Is about 0.7 V or less, the collector current 48 becomes zero. The MOS-FET 31 has a function of switching the value of the resistor connected to the emitter of the transistor 29. When the base signal of the transistor 29 is about 0.7 V or more, the MOS-FET 31 is a MOS.
When the FET 31 is turned on, it has the effect of increasing the collector current 48 of the transistor 29.

Considering the relationship between the switching command signal 42 and the collector current 48, the collector current 48 is 0 when the switching command signal 42 is at the “H” level.
Then, until the delay time TB elapses after the switching command signal 42 changes to the “L” level, the collector current 4
8 has a relatively large current value, and then has a relatively small current value. When the switching command signal 42 reaches the'H 'level, the collector current 48 becomes zero.

In summary, in accordance with the switching command signal 42, the collector current 49 has the first current value 164 and the collector current 48 has the seventh current value 170, and the collector current 49 has the second state. Current value of 16
5 and the collector current 48 has the eighth current value 171 in the second state, and the collector current 49 has the fifth current value 168 and the collector current 48 has the third current value 166 in the third state. It can be seen that there is a fourth state in which the current 49 has the sixth current value 169 and the collector current 48 has the fourth current value 167, and the fourth state is repeatedly realized in order from the first state. However, in this embodiment,
The fifth current value 168, the sixth current value 169, the seventh current value 170, and the eighth current value 171 are set to 0.

The above is the description of the operation of the current control means 125 and 126. Next, the voltage limiting means 9
Describe the function of 7.

The voltage limiting means 97 composed of the Zener diodes 95 and 96 prevents the transistor 119 of the current control means 125 from being saturated.
It acts to limit the upper limit of the collector voltage of 19 and at the same time acts to limit the upper limit of the gate voltage of the IGBTs 1 and 2. Further, the voltage limiting means 97 composed of the Zener diodes 95 and 96 functions to limit the lower limit of the collector voltage of the transistor 29 of the current control means 126 so that the transistor 29 of the current control means 126 is not saturated, and at the same time, the IGBTs 1 and 2 have the same structure. It works to limit the lower limit of the gate voltage.

Here, the upper limits of the gate voltages of the IGBTs 1 and 2 are such that the IGBT 1 can be sufficiently turned on, and the IGBT 2 can be sufficiently turned off, and the IGBT is
It is necessary to use a value that does not exceed the breakdown voltage between the gate and the emitter of T1 and T2. The lower limit of the gate voltage of the IGBT1 and the IGBT2 is a voltage at which the IGBT2 can be sufficiently turned on,
And a voltage at which the IGBT 1 can be turned off sufficiently, and I
It is necessary to use a value that does not exceed the breakdown voltage between the gate and emitter of the GBTs 1 and 2.

Generally, the breakdown voltage between the gate and the emitter of an N-channel type IGBT is often ± 20 V to ± 30 V, and the gate voltage threshold for starting the conduction between the collector and the emitter is based on the emitter voltage. + 1V ~
Many are about + 5V. On the other hand, P channel type I
The breakdown voltage between the gate and emitter of GBT is ± 20V to ± 30
Most of them are about V, and the gate voltage threshold for starting conduction between the collector and the emitter is often about -1V to -5V based on the emitter voltage.

Here, the relationship between the switching command signal 42 and the gate signal voltage 50 based on the negative terminal of the DC main power supply 14 is shown in FIG.

First, the switching command signal 42 is "L".
When the level changes to'H 'level, transistor 1
The collector current 49 of 19 flows, the gate signal voltage 50 suddenly rises, and the voltage is fixed when the Zener diodes 95 and 96 become conductive. The rising time TR required for the gate signal voltage 50 to rise is determined by the relationship between the capacitances contained in the IGBTs 1 and 2, the Zener diodes 95 and 96, and the collector current 49. Further, in the state where the Zener diodes 95 and 96 are conducting, since the gate signal voltage 50 does not change significantly, the collector current 49 can be maintained at that voltage even if it is a very small current. The above settings are sufficient. Therefore, the signal delay means 114
If the delay time TA is set to be slightly larger than the rising time TR, the rising time TR can be reduced and the power loss of the transistor 119, the resistor 122, etc. can be minimized.

Next, the switching command signal 42 is "H".
When the level changes to'L 'level, transistor 2
The collector current 48 of 9 flows and the gate signal voltage 50 suddenly drops, and the voltage is fixed when the Zener diodes 95 and 96 become conductive. The time TF required for the gate signal voltage 50 to fall is determined by the relationship between the capacitances contained in the IGBTs 1 and 2, the Zener diodes 95 and 96, and the collector current 48.

Further, Zener diodes 95 and 96
Since the gate signal voltage 50 does not change significantly in the state where the current is conducting, even if the collector current 48 is set to a very small current, the voltage can be maintained, and in reality, the resistor 105
It suffices to set it to a value equal to or higher than the current value flowing through. Therefore, if the delay time TB of the signal delay means 27 is set to be slightly larger than the fall time TF, the fall time TF can be reduced, and the power loss of the transistor 29, the resistor 35, etc. can be minimized.

Next, the operation of the IGBTs 1 and 2 will be described. Since the gates and the emitters of the IGBTs 1 and 2 are commonly connected to each other, when the gate signal voltage 50 becomes higher than the motor winding terminal voltage 51 by the gate voltage threshold value of the IGBT 1 or more, the IGBT 1 causes a current to flow from the collector to the emitter. On the contrary, when the gate signal voltage 50 becomes lower than the motor winding terminal voltage 51 by the gate voltage threshold value of the IGBT 2 or more, the IGBT 2 starts to flow current from the emitter to the collector. Therefore, the potential difference between the gate signal voltage 50 and the motor winding terminal voltage 51 is always within a certain range, and the IGBTs 1 and 2 simultaneously pass currents to short-circuit the positive and negative terminals of the DC main power supply 14. Is essentially impossible.

Next, the functions of the diodes 5 and 6 will be described. Generally, a simple equivalent circuit of a motor winding is expressed as a resistance, an inductance, and a voltage source corresponding to an induced voltage connected in series. Therefore, unlike the pure resistance load, the direction of the current flowing through the motor winding terminal 52 is not uniquely determined by the voltage applied to the motor winding terminal 52, and the IGBT1 is ON and the IGBT2 is OFF and the motor winding terminal 52 is A is flowing from the motor to the motor
State, IGBT1 is ON and IGBT2 is OFF
And the state of B in which the electric current is flowing from the electric motor to the electric motor winding terminal 52, and the IGBT1 is OFF and the IGBT2 is
Is ON, the current is flowing from the motor to the motor winding terminal 52, and the IGBT 1 is OFF and the IG
It has four states, that is, the state in which the BT2 is ON and the current flows from the motor winding terminal 52 to the motor.

First, in the state A, it can be seen that the current flowing through the motor winding terminal 52 flows through the IGBT 1.
Further, it can be seen that in the state of C, the current flowing through the motor winding terminal 52 flows through the IGBT 2. Further, regarding the state B and the state D, it can be seen that the current flowing through the motor winding terminal 52 flows through the diode 5 and the diode 6, respectively.

Here, it can be seen that the motor winding terminal voltage 51 in the state B rises due to the current flowing through the motor winding terminal 52 and is fixed when the diode 5 becomes conductive. If the reverse recovery time trr of the diode 5 is long, switching loss increases.
It is preferable to select one having a short reverse recovery time.

Similarly, the motor winding terminal voltage 51 in the D state is lowered by the current flowing through the motor winding terminal 52, and is fixed when the diode 6 becomes conductive. If the reverse recovery time trr of the diode 6 is long, switching loss increases. Therefore, it is preferable to select the diode 6 having a short reverse recovery time as much as possible.

From the above description, the switching command signal 4
It can be seen that when 2 is set to the'H 'level, the motor winding terminal 52 is connected to the plus terminal of the DC main power supply 14. Further, when the switching command signal 42 is set to the “L” level, the motor winding terminal 52 is connected to the negative terminal of the DC main power supply 14, and when the switching command signal 42 is changed from the “H” level to the “L” level, It can be seen that the floating time is essentially 0 even when the level is changed from the “L” level to the “H” level.

Further, by changing the current values of the collector current 49 of the transistor 119 and the collector current 48 of the transistor 29, the rise time T of the gate signal voltage 50 is increased.
R and the fall time TF can be freely set within a certain range, and accordingly, the rise time and the fall time of the motor winding terminal voltage 51 can be freely set within a certain range. Normally, the motor winding terminal voltage is 5
The smaller the rise time and fall time of 1, the IGBT
1 and the IGBT 2 and the like can reduce power loss, which is preferable, but there is a drawback that electric noise increases. Therefore, it is necessary to increase the rising time and the falling time of the motor winding terminal voltage 51 for the purpose of reducing the electrical noise, and the configuration can easily cope with this.

Needless to say, by connecting a capacitor between the gates and emitters of the IGBTs 1 and 2 in FIG. 1, the rise time and fall time of the motor winding terminal voltage 51 can be made much longer.

The above is the description of the operation of the current control means 125 and 126 when the electric motor release signal 156 is in the "H" level, that is, when it is not in the free run state. Finally, the electric motor release signal 156 is " L '
A description will be added to the operation of the current control means 125 and 126 when the level, that is, the free-run state is commanded.

When the motor release signal 156 is at the "L" level, that is, when the free running state is commanded, the output signals of the AND gates 106 and 107 are both at the "H" level regardless of the switching command signal 42. Therefore, the base signal 123 of the PNP type transistor 119 becomes the “H” level and the base signal 45 of the transistor 29 becomes the “L” level.

This state is the so-called fifth state, which is the ninth current value and is the collector current 49 and the collector current 48.
Are both 0.

In the fifth state, the IGBTs 1 and 2 are
The gate signal voltage 50 of 1 becomes almost the same potential as the motor winding terminal voltage 51 by the resistor 105. Therefore, the IGBT
Both 1 and 2 are in the OFF state, and the free-run state can be realized. The fifth state is mainly used to interrupt the operation of the electric motor and protect the electric motor and the control device when some trouble occurs.

The transition to the fifth state is made according to the first state,
It is possible from any of the second state, the third state, and the fourth state, and shifts at the moment when the motor release signal 156 changes to the'L 'level. On the contrary, the fifth state is configured to shift to the first state or the third state at the moment when the electric motor release signal 156 changes to the “H” level. This is because the transition time from the fifth state to the second state or the fourth state requires a very long time to increase or decrease the gate signal voltage 50, and is a preventive measure for causing excessive heat generation in the IGBTs 1 and 2. Is.

However, the transition from the fifth state to another state is mainly for the purpose of restarting the operation of the motor which has been interrupted. In this case, the frequency is at most once every few seconds. IGBTs 1 and 2 are very low
It is possible to adopt a configuration in which the fifth state can be shifted to all other states as long as the withstand capability of the above is sufficient.

The current control means 125 and 126 of this embodiment have the fifth current value 168 and the sixth current value 16 respectively.
9, the seventh current value 170 and the eighth current value 171 to 0
However, the first current value 164 is equal to the seventh current value 17
The current value is larger than 0, and the second current value 165 is the eighth value.
Current value 171 is larger than the current value 171 and the third current value 166 is larger than the fifth current value 168.
The fourth current value 167 is set to a larger current value than the sixth current value 169, and the first current value 164 and the seventh current value 170
Is larger than the difference between the second current value 165 and the eighth current value 171 and the third current value 166 and the fifth current value 168 are
Is larger than the difference between the fourth current value 167 and the sixth current value 169, the fifth current value 168 and the sixth current value 1
It goes without saying that the 69, the seventh current value 170, and the eighth current value 171 can be values other than zero. Figure 2 (b)
An example is shown in.

Further, the current control means 125 and 126 of this embodiment also set the ninth current value in the fifth state to 0, but it goes without saying that the ninth current value can be a value other than zero. That is, if the collector current 49 of the transistor 119 and the collector current 48 of the transistor 29 have the same current value, they can be values other than zero.

(Second Embodiment) A second embodiment of the present invention will be described below with reference to the drawings.

In FIG. 4, 1 is an N-channel type IGBT, 2 is a P-channel type IGBT, 5 and 6 are diodes, 126 is a current control means, 109 is a signal processing means, 14 is a DC main power supply, and 15 and 16 1 is a DC power source, 105 is a resistor, 97 is a voltage limiting means composed of Zener diodes 95 and 96, and the above is shown in FIG.
The configuration is the same as that of. The difference from the configuration of FIG. 1 is that
The current control means 125 is composed of the current mirror means 98 and the current control means 127.

The operations of the current mirror means 98 and the current control means 127, which are different from the configuration of FIG. 1, in the output circuit for the PWM inverter configured as described above will be described.

In order to simplify the explanation, the case where the electric motor release signal 156 is instructing the "H" level, that is, the state where the motor is not free running, will be described.
Finally, a description will be added to the case where the motor release signal 156 commands the “L” level, that is, the free-run state.

First, the operation of the current control means 127 will be described in detail with reference to FIG. NPN type transistor 2
The base signal 43 of 8 causes the switching command signal 42 to be generated through the logical product negating means 107 and the logical inverting means 20. The base signal 43 is substantially the same as the switching command signal 42, and it is assumed that the'L 'level takes a value of 0V and the'H' level takes a value of 5V, for example.

Next, N-channel type MOS-FE
The gate signal 44 of T30 causes the switching command signal 42 to be generated through the logical inversion means 21 and 22, the logical product negation means 107, and the signal delay means 26. The gate signal 44 is a signal obtained by logically inverting the switching command signal 42 and delayed by the delay time TA.
The voltage is set so that the OS-FET 30 can be turned off sufficiently, and the “H” level is set to the O-FET 30 sufficiently set to O.
The voltage is set to N.

The transistor 28 has an emitter follower type circuit configuration, and when the base signal 43 becomes about 0.7 V or more, a collector current 47 which is determined by the voltage of the base signal 43 and the value of the resistance connected to the emitter flows, and the base signal 43. Is about 0.7 V or less, the collector current 47 becomes zero.

The MOS-FET 30 has a function of switching the value of the resistance connected to the emitter of the transistor 28. When the base signal of the transistor 28 is about 0.7 V or more and the MOS-FET 30 is turned on, the collector current 47 of the transistor 28 is increased. Has the effect of increasing.

Considering the relationship between the switching command signal 42 and the collector current 47, the collector current 47 is 0 when the switching command signal 42 is at the “L” level.
Then, until the delay time TA elapses after the switching command signal 42 changes to the “H” level, the collector current 4
7 has a relatively large current value, and then has a relatively small current value. When the switching command signal 42 becomes the'L 'level, the collector current 47 becomes zero.

The above is the description of the operation of the current control means 127. Next, the function of the current mirror means 98 will be described.

The resistors 11 and 12 and the transistors 9 and 10 have a current mirror configuration with each other, and serve to make the collector current 49 of the transistor 9 a current corresponding to the collector current 47 of the transistor 28 in a range where the transistor 9 is not saturated. . Here, if the collector voltage of the transistor 9 rises too much and the transistor 9 saturates and becomes an ON state, the proportional relationship between the collector current 47 and the collector current 49 is broken, and the next OFF operation of the transistor 9 is delayed. Therefore, the transistor 9
It is necessary to operate without saturating. Therefore,
The upper limit of the collector voltage of the transistor 9 is restricted by the voltage limiting means 97 composed of the Zener diodes 95 and 96 so that the transistor 9 is not saturated.

Considering the relationship between the switching command signal 42 and the collector current 49 of the transistor 9, the collector current 49 is 0 when the switching command signal 42 is at the “L” level, and the switching command signal 42 is next at the “H” level. The collector current 49 has a relatively large current value and then a relatively small current value until the delay time TA elapses after the level is changed to the level, and the switching command signal 42
Becomes "L" level, the collector current 49 becomes zero.

The above is the description of the operations of the current control means 127 and the current mirror means 98 when the electric motor release signal 156 is in the "H" level, that is, the state where the motor is not free running. 1
The operation of the current control means 127 and the current mirror means 98 when 56 is commanding the “L” level, that is, the free-run state is added.

When the motor release signal 156 is at the'L 'level, that is, when the free run state is instructed, the output signal of the logical product denial means 107 becomes the'H' level regardless of the switching command signal 42, and therefore the NPN. The base signal 43 of the transistor 28 of the type becomes the “L” level. In this state, the collector current 47 is 0 and the collector current 49 of the transistor 9 is also 0. This is the so-called fifth state.

As described above, it is understood that the current mirror means 98 and the current control means 127 perform the same operations as the current control means 125.

Also in FIG. 4, FIG. 6 and FIG.
It goes without saying that by connecting a capacitor between the gates and emitters of the GBTs 1 and 2, the rise time and fall time of the motor winding terminal voltage 51 can be made much longer.

It goes without saying that the PNP type transistor 10 in FIG. 4 may be expressed as a diode.

(Third Embodiment) A third embodiment of the present invention will be described below with reference to the drawings.

In FIG. 6, 1 is an N-channel type IGBT, 2 is a P-channel type IGBT, 5 and 6 are diodes, 126 and 127 are current control means, 109 is signal processing means, 14 is a DC main power supply, and 15 Reference numerals 16 and 16 denote a DC power source, reference numeral 105 denotes a resistor, reference numeral 97 denotes a voltage limiting means composed of Zener diodes 95 and 96, and the above is the same as the configuration of FIG.

The difference from the configuration of FIG. 4 is that the current mirror means 98, which was composed of the PNP type transistors 9 and 10 and the resistors 11 and 12, is simply replaced by the PNP type transistor 9 and the resistors 11 and 12. This is the point that constitutes the means.

Since the current mirror means in FIG. 6 is inferior to the current mirror means in FIG. 4 in accuracy and temperature characteristics, it is necessary to raise the voltage of the DC power supply 15, but if it is allowed, there is no practical problem. Absent.

(Embodiment 4) A fourth embodiment of the present invention will be described below with reference to the drawings.

In FIG. 7, 1 is an N-channel type IGBT, 2 is a P-channel type IGBT, 5 and 6 are diodes, 126 and 127 are current control means, 109 is signal processing means, 14 is a DC main power supply, and 15 Reference numerals 16 and 16 denote a DC power source, reference numeral 105 denotes a resistor, reference numeral 97 denotes a voltage limiting means composed of Zener diodes 95 and 96, and the above is the same as the configuration of FIG.

The difference from the configuration of FIG. 4 is that the current mirror means 98, which was composed of the PNP type transistors 9 and 10 and the resistors 11 and 12, is the PNP type transistor 9, the NPN type transistor 128, the diode 129 and the resistor. 11 and 130 constitute a current mirror means.

In the current mirror means shown in FIG. 4, P
When the collector voltage of the NP transistor 9 drops, PN
The base voltage of the P-transistor 9 is the collector output capacitance Co
It is lowered by the current flowing through b and turns on the PNP transistor 9. Therefore, a current leaks to the collector of the PNP transistor 9, and the gate signal voltage 5
The fall time of 0 becomes long and the switching loss of the IGBT increases. Therefore, to prevent this, PN
It is necessary to select the P-type transistor 9 having a very small collector output capacitance Cob.

On the other hand, in the current mirror means in FIG. 7, when the collector voltage of the PNP transistor 9 drops, the current flowing through the collector output capacitance Cob is NP.
Since it is compensated by the emitter current of the N-transistor 128, the base voltage of the PNP transistor 9 can be prevented from lowering, and the PNP-type transistor 9 is configured to have a small switching loss even if a collector output capacitance Cob having a relatively large value is selected. be able to.

(Embodiment 5) A fifth embodiment of the present invention will be described below with reference to the drawings.

In FIG. 8, 1 is an N-channel type IGBT, 2 is a P-channel type IGBT, 5 and 6 are diodes, 109 is a signal processing means, 14 is a DC main power supply, 15 and 16 are DC power supplies, and 105 is Resistance, 9
Reference numeral 7 is a voltage limiting means composed of Zener diodes 95 and 96, and the above is the same as the structure of FIG.

The difference from the configuration of FIG. 1 is that the current control means 1
26 is a current mirror means 132 and a current control means 131
And the current control means 125 are connected to the current control means 16
3 points.

The operations of the current mirror means 132 and the current control means 131 different from those of FIG. 1 in the output circuit for the PWM inverter configured as described above will be described.
Here, for the sake of simplicity, all the cases where the motor release signal 156 commands the “H” level, that is, the state where the motor is not free running are described, and finally the motor release signal 156 is the “L” level, that is, I will add the explanation about the case of commanding the free-run state.

First, the operation of the current control means 131 will be described in detail with reference to FIG. PNP type transistor 1
The base signal 148 of 37 causes the switching command signal 42 to be generated through the logical product negating means 106 and the logical inverting means 65, 161, and 139. The base signal 148 has the same potential as the plus terminal of the DC power supply 15 when the switching command signal 42 is at the “H” level, and has a potential 5 V lower than the plus terminal of the DC power supply 15 when the switching command signal 42 is at the “L” level.

Next, a P-channel type MOS-FE
The gate signal 149 of T138 is the switching command signal 4
2 is generated through the logical inversion means 65, 161, 140 and 141, the logical product negation means 106 and the signal delay means 142. This gate signal 149 is obtained by logically inverting the switching command signal 42 and delaying it by the delay time TB, and sets the “L” level to sufficiently turn on the MOS-FET 138.
Voltage that can be applied to the MOS-
The voltage is set so that the FET 138 can be sufficiently turned off.

The transistor 137 has an emitter follower type circuit configuration, and the potential of the base signal 148 is the DC power supply 1
When it becomes lower than the potential of the positive terminal of No. 5 by about 0.7 V or more, a current determined by the value of the resistor connected to the emitter and the voltage applied thereto flows as a collector current 150, and the potential of the base signal 148 and the DC power supply 15 are reduced. If the difference from the positive terminal potential is about 0.7 V or less, collector current 15
0 becomes 0.

The MOS-FET 138 is the transistor 13
When the MOS-FET 138 is turned on in the state where the potential of the base signal of the transistor 137 is lower than the potential of the plus terminal of the DC power source 15 by about 0.7V or more, it functions to switch the value of the resistor connected to the emitter of the transistor 7. It has the effect of increasing the collector current 150 of the transistor 137.

Considering the relationship between the switching command signal 42 and the collector current 150, the collector current 150 is 0 when the switching command signal 42 is at the “H” level, and then the switching command signal 42 is at the “L” level. The collector current 150 has a relatively large current value and then has a relatively small current value until the delay time TB elapses after the change to, and the collector current 150 becomes 0 when the switching command signal 42 becomes the “H” level. .

The above is the description of the operation of the current control means 131. Next, the function of the current mirror means 132 will be described.

Resistors 135 and 136 and transistor 1
33 and 134 have a current mirror configuration with each other,
In the range where the transistor 133 is not saturated, the collector current 48 of the transistor 133 is set to the transistor 137.
Of the collector current 150. Here, when the collector voltage of the transistor 133 drops too much and the transistor 133 is saturated and turned on, the proportional relationship between the collector current 150 and the collector current 48 is broken, and the next OFF operation of the transistor 133 is delayed. Therefore, it is necessary to operate the transistor 133 without saturating it. Therefore, the lower limit of the collector voltage of the transistor 133 is limited by the voltage limiting means 97 composed of the Zener diodes 95 and 96 so that the transistor 133 is not saturated.

Considering the relationship between the switching command signal 42 and the collector current 48 of the transistor 133, the collector current 48 is 0 when the switching command signal 42 is at the “H” level, and the switching command signal 4 is next.
The collector current 48 has a relatively large current value until the delay time TB elapses after 2 changes to the'L 'level.
Next, when the switching command signal 42 becomes relatively high and the switching command signal 42 becomes the “H” level, the collector current 48 becomes zero.

The above is the current control means 131 and the current mirror means 132 in the case where the motor release signal 156 indicates the "H" level, that is, the state where the motor is not free running.
Finally, the operation of the current control means 131 and the current mirror means 132 when the electric motor release signal 156 is commanding the “L” level, that is, the free-run state is added.

When the motor release signal 156 is in the "L" level, that is, when the free running state is instructed, the output signal of the logical product denial means 106 becomes the "H" level regardless of the switching instruction signal 42, and thus the PNP. The base signal 148 of the type transistor 137 becomes the “H” level. In this state, the collector current 150 is 0 and the collector current 48 of the transistor 133 is also 0.
This is the so-called fifth state.

As described above, the current mirror means 132
It can be seen that the current control means 131 and the current control means 131 operate in the same manner as the current control means 126.

Further, the current control means 1 different from the configuration of FIG.
63 is that the photocoupler 115 of the current control means 125 is the logic inverting means 162. This is because it is not necessary to consider insulation by operating the logic elements of the current control means 163 and 131 and the signal processing means 109 by a common power source, and the operation of the current control means 162 is equivalent to that of the current control means 125. be able to.

Also in FIGS. 8, 10 and 11, by connecting a capacitor between the gates and the emitters of the IGBTs 1 and 2, the motor winding terminal voltage 5 is further increased.
It goes without saying that the rise time and fall time of 1 can be significantly lengthened.

It goes without saying that the NPN type transistor 134 in FIG. 8 may be expressed as a diode.

(Embodiment 6) A sixth embodiment of the present invention will be described below with reference to the drawings.

In FIG. 10, 1 is an N-channel type IGBT, 2 is a P-channel type IGBT, 5 and 6 are diodes, 131 and 163 are current control means, 109 is signal processing means, 14 is a DC main power supply, and 15 Reference numerals 16 and 16 denote a DC power source, 105 a resistor, 97 a voltage limiting means composed of Zener diodes 95 and 96, and the above is the same as the configuration of FIG.

The difference from the configuration of FIG. 8 is that NPN type transistors 133 and 134 and resistors 135 and 1 are used.
The current mirror means 132 composed of
Type transistor 133 and resistors 135 and 136
That is, the current mirror means is simply configured. Since the current mirror means in FIG. 10 is inferior in accuracy and temperature characteristics to the current mirror means in FIG. 8, it is necessary to increase the voltage of the DC power supply 16, but if it is allowed, there is no practical problem.

(Embodiment 7) Hereinafter, a seventh embodiment of the present invention will be described with reference to the drawings.

In FIG. 11, 1 is an N-channel type IGBT, 2 is a P-channel type IGBT, 5 and 6 are diodes, 131 and 163 are current control means, 109 is a signal processing means, 14 is a DC main power supply, and 15 Reference numerals 16 and 16 denote a DC power source, 105 a resistor, 97 a voltage limiting means composed of Zener diodes 95 and 96, and the above is the same as the configuration of FIG.

The difference from the configuration of FIG. 8 is that NPN type transistors 133 and 134 and resistors 135 and 1 are used.
The current mirror means 132 composed of
Type transistor 133, PNP type transistor 152, diode 153 and resistors 135 and 15
4 is that the current mirror means is configured.

In the current mirror means shown in FIG.
When the collector voltage of the PN transistor 133 rises,
The base voltage of the NPN transistor 133 rises due to the current flowing through the collector output capacitance Cob, turning on the NPN transistor 133. Therefore, the current leaks to the collector of the NPN transistor 133,
The rise time of the gate signal voltage 50 becomes long, and the switching loss of the IGBT increases. Therefore, in order to prevent this, it is necessary to select the NPN type transistor 133 having a very small collector output capacitance Cob.

On the other hand, in the current mirror means shown in FIG. 11, when the collector voltage of the NPN transistor 133 rises, the current flowing through the collector output capacitance Cob can be removed by the emitter current of the PNP transistor 152, and the NPN transistor 133 can be removed. It is possible to prevent the rise of the base voltage of 133, and NPN type transistor 1
Even if 33 having a relatively large collector output capacitance Cob is selected, the switching loss can be reduced.

In the case of constructing a three-phase PWM inverter as shown in FIG. 18, generally, a DC main power supply is commonly connected to arrange three output circuits for PWM inverters. It goes without saying that the DC power supplies 15 and 16 in the first, second, third, fourth, fifth, sixth and seventh embodiments can also be commonly connected in the inverter output circuit.

(Embodiment 8) An eighth embodiment of the present invention will be described below with reference to the drawings.

In FIG. 12, 1 is an N-channel type IGBT, 2 is a P-channel type IGBT, 5 and 6 are diodes, 98 is a current mirror means, 14
Is a DC main power supply, 15 and 16 are DC power supplies, and 97 is a voltage limiting means composed of Zener diodes 95 and 96.

The difference from the configuration of FIG. 4 is that the resistor 105 is omitted and the current control means 126 and 127 and the signal processing means 10 are omitted.
9 is constituted by the current control means 13.

When it is not necessary to put the electric motor in the free run state, the structure shown in FIG. 12 can be adopted.

Also in FIGS. 12, 13 and 14, by connecting a capacitor between the gates and the emitters of the IGBTs 1 and 2, it is possible to significantly lengthen the rise time and fall time of the motor winding terminal voltage 51. Needless to say.

It goes without saying that the PNP type transistor 10 in FIG. 12 may be expressed as a diode.

(Ninth Embodiment) A ninth embodiment of the present invention will be described below with reference to the drawings.

In FIG. 13, 1 is an N-channel type IGBT, 2 is a P-channel type IGBT, 5 and 6 are diodes, 13 is a current control means, 14 is a DC main power supply, 15 and 16 are DC power supplies, and 97 is The voltage limiting means is composed of the Zener diodes 95 and 96, and the above is the same as the structure of FIG.

The difference from the configuration of FIG. 12 is that the current mirror means 98, which was composed of the PNP type transistors 9 and 10 and the resistors 11 and 12, is simply replaced by the current mirror means 98 by the PNP type transistor 9 and the resistors 11 and 12. This is the point that constitutes the means. The current mirror means shown in FIG. 13 is inferior to the current mirror means shown in FIG. 12 in accuracy and temperature characteristics, so that the voltage of the DC power supply 15 needs to be increased, but if it is allowed, there is no practical problem.

(Tenth Embodiment) The tenth embodiment of the present invention will be described below with reference to the drawings.

In FIG. 14, 1 is an N-channel type IGBT, 2 is a P-channel type IGBT, 5 and 6 are diodes, 13 is a current control means, 14 is a DC main power supply, 15 and 16 are DC power supplies, and 97 is The voltage limiting means is composed of the Zener diodes 95 and 96, and the above is the same as the structure of FIG.

The difference from the configuration of FIG. 12 is that the current mirror means 98, which is composed of the PNP type transistors 9 and 10 and the resistors 11 and 12, is the PNP type transistor 9, the NPN type transistor 128, the diode 129 and the resistor. 11 and 130 constitute a current mirror means.

In the current mirror means shown in FIG. 12,
When the collector voltage of the PNP transistor 9 drops, P
The base voltage of the NP transistor 9 is the collector output capacitance C
PNP transistor 9 which is lowered by the current flowing through ob
Turns on. As a result, a current leaks to the collector of the PNP transistor 9, the fall time of the gate signal voltage 50 becomes long, and the switching loss of the IGBT increases. Therefore, to prevent this, P
The NP type transistor 9 has a collector output capacitance Cob.
Has to be very small.

On the other hand, in the current mirror means shown in FIG. 14, when the collector voltage of the PNP transistor 9 drops, the current flowing through the collector output capacitance Cob becomes N.
Since it is compensated by the emitter current of the PN transistor 128, the base voltage of the PNP transistor 9 can be prevented from lowering, and the PNP type transistor 9 is configured to have a small switching loss even if a collector output capacitance Cob having a relatively large value is selected. be able to.

(Eleventh Embodiment) The eleventh embodiment of the present invention will be described below with reference to the drawings.

In FIG. 15, 1 is an N-channel type IGBT, 2 is a P-channel type IGBT, 5 and 6 are diodes, 132 is a current mirror means, 1
Reference numeral 4 is a DC main power supply, 15 and 16 are DC power supplies, and 97 is a voltage limiting means composed of Zener diodes 95 and 96.

The difference from the configuration of FIG. 8 is that the resistor 105 is omitted and the current control means 131 and 163 and the signal processing means 10 are omitted.
9 is constituted by the signal processing means 155.

When it is not necessary to put the electric motor in the free run state, the configuration shown in FIG. 15 can be used.

Also in FIGS. 15, 16 and 17, it is possible to significantly increase the rise time and fall time of the motor winding terminal voltage 51 by connecting a capacitor between the gates and emitters of the IGBTs 1 and 2. Needless to say.

It goes without saying that the NPN type transistor 134 in FIG. 15 may be expressed as a diode.

(Embodiment 12) A twelfth embodiment of the present invention will be described below with reference to the drawings.

In FIG. 16, 1 is an N-channel type IGBT, 2 is a P-channel type IGBT, 5 and 6 are diodes, 155 is a current control means, 14 is a DC main power supply, 15 and 16 are DC power supplies, and 97 is The voltage limiting means is composed of the Zener diodes 95 and 96, and the above is the same as the configuration of FIG.

The difference from the configuration of FIG. 15 is that the current mirror means 132 formed of NPN type transistors 133 and 134 and resistors 135 and 136 is NP.
N-type transistor 133 and resistors 135 and 13
6 is that the current mirror means is simply configured.
Since the current mirror means in FIG. 16 is inferior in accuracy and temperature characteristics to the current mirror means in FIG. 15, it is necessary to increase the voltage of the DC power supply 16, but if it is allowed, there is no practical problem.

(Thirteenth Embodiment) The thirteenth embodiment of the present invention will be described below with reference to the drawings.

In FIG. 17, 1 is an N-channel type IGBT, 2 is a P-channel type IGBT, 5 and 6 are diodes, 155 is a current control means, 14 is a DC main power supply, 15 and 16 are DC power supplies, and 97 is The voltage limiting means is composed of the Zener diodes 95 and 96, and the above is the same as the configuration of FIG.

The difference from the configuration of FIG. 15 is that the current mirror means 132 formed of NPN type transistors 133 and 134 and resistors 135 and 136 is NP.
N-type transistor 133, PNP-type transistor 152, diode 153, resistors 135 and 1
This is the point that the current mirror means is constituted by 54.

In the current mirror means shown in FIG. 15,
When the collector voltage of the NPN transistor 133 rises, the base voltage of the NPN transistor 133 rises due to the current flowing through the collector output capacitance Cob, turning on the NPN transistor 133. As a result, a current leaks to the collector of the NPN transistor 133, and the rise time of the gate signal voltage 50 becomes long, so that the IGBT
Will increase the switching loss. Therefore, in order to prevent this, it is necessary to select the NPN type transistor 133 having a very small collector output capacitance Cob.

On the other hand, in the current mirror means in FIG. 17, when the collector voltage of the NPN transistor 133 rises, the current flowing through the collector output capacitance Cob can be removed by the emitter current of the PNP transistor 152, and the NPN transistor 152 can be removed. It is possible to prevent the rise of the base voltage of 133, and NPN type transistor 1
Even if 33 having a relatively large collector output capacitance Cob is selected, the switching loss can be reduced.

In the case of constructing a three-phase PWM inverter as shown in FIG. 18, generally, a DC main power source is commonly connected to dispose three PWM inverter output circuits. It goes without saying that the DC power supplies 15 and 16 in the eighth, ninth, tenth, eleventh, twelfth and thirteenth embodiments can also be commonly connected in the inverter output circuit.

[0156]

As described above, the present invention has the N-channel type first IGBT, the P-channel type second IGBT, the first and second diodes, and the current output terminal. The first IGBT includes a current control unit 1 for controlling a current flowing out from the output terminal, a current control unit 2 having a current input terminal for controlling a current flowing in from the current input terminal, and a DC main power supply. A collector, a cathode of the first diode, and a positive terminal of the DC main power supply are connected, and a collector of the second IGBT, an anode of the second diode, and a negative terminal of the DC main power supply are connected,
The emitter of the first IGBT is connected to the anode of the first diode, the emitter of the second IGBT is connected to the cathode of the second diode, and the gate of the first IGBT and the second IG are connected.
The gate of the BT, the current output terminal of the current control means 1 and the current input terminal of the current control means 2 are connected to each other, and a resistance and a positive and negative bidirectional voltage are provided between the gate and the emitter of the first or second IGBT. On the other hand, by adopting a configuration in which voltage limiting means having a Zener phenomenon are connected in parallel, the switching command signal and the average voltage of the motor winding terminal are uniquely determined when the floating time is zero and there is essentially no floating state. Control error is very small,
Moreover, it is possible to provide an excellent PWM inverter output circuit with low power consumption at low cost. Furthermore, if necessary, an excellent PW with very little generation of electrical noise
The output circuit for the M inverter can be provided at low cost.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a PWM inverter output circuit according to a first embodiment of the present invention.

FIG. 2A is a diagram showing the operation of the current control means of the PWM inverter output circuit according to the first embodiment of the present invention. FIG. 2B is the current control of the PWM inverter output circuit according to the first embodiment of the present invention. The figure which shows the other operation of the means

FIG. 3 is a diagram showing the operation of the PWM inverter output circuit according to the first embodiment of the present invention.

FIG. 4 is a configuration diagram of a PWM inverter output circuit according to a second embodiment of the present invention.

FIG. 5 is a diagram showing the operation of the current control means of the PWM inverter output circuit according to the second embodiment of the present invention.

FIG. 6 is a configuration diagram of a PWM inverter output circuit according to a third embodiment of the present invention.

FIG. 7 is a configuration diagram of a PWM inverter output circuit according to a fourth embodiment of the present invention.

FIG. 8 is a configuration diagram of a PWM inverter output circuit according to a fifth embodiment of the present invention.

FIG. 9 is a diagram showing the operation of the current control means of the PWM inverter output circuit according to the fifth embodiment of the present invention.

FIG. 10 is a configuration diagram of a PWM inverter output circuit according to a sixth embodiment of the present invention.

FIG. 11 is a configuration diagram of a PWM inverter output circuit according to a seventh embodiment of the present invention.

FIG. 12 is a configuration diagram of a PWM inverter output circuit according to an eighth embodiment of the present invention.

FIG. 13 is a configuration diagram of a PWM inverter output circuit according to a ninth embodiment of the present invention.

FIG. 14 is a configuration diagram of a PWM inverter output circuit according to a tenth embodiment of the present invention.

FIG. 15 is a configuration diagram of an output circuit for a PWM inverter according to an eleventh embodiment of the present invention.

FIG. 16 is a configuration diagram of an output circuit for a PWM inverter according to a twelfth embodiment of the present invention.

FIG. 17 is a configuration diagram of a PWM inverter output circuit according to a thirteenth embodiment of the present invention.

FIG. 18 is a schematic diagram showing a configuration of a general PWM inverter.

FIG. 19 is a configuration diagram of a conventional PWM inverter output circuit.

FIG. 20 is a diagram showing an operation of a conventional PWM inverter output circuit.

[Explanation of symbols]

1 N-channel type IGBT 2 P-channel type IGBT 5, 6, 78, 79, 129, 153 Diode 9, 10, 119, 137, 152 PNP type transistor 11, 12, 32, 33, 34, 35, 83 , 84, 8
5,86,87,88,89,90,91,92,10
5,116,117,121,122,130,13
5, 136, 146, 147, 154 Resistance 13, 125, 126, 127, 131, 155, 16
3 Current Control Means 14 DC Main Power Supply 15, 16, 93, 94, 118 DC Power Supply 20, 21, 22, 23, 24, 25, 65, 111,
112, 113, 139, 140, 141, 161, 1
62 logic inversion means 26, 27, 114, 142 signal delay means 28, 29, 74, 75, 76, 77, 128, 13
3,134 NPN type transistor 30,31 N channel type MOS-FET 42,61,62 Switching command signal 52,63,64 Motor winding terminal 53 PWM inverter output circuit 54 First state 55 Second state 56 Third state 57 Fourth state 58 Frequency voltage setting means 59 PWM control circuit 60 Electric motor 66,67 On-delay circuit 68,69 Base drive circuit 70,71 Power transistor 72,73,115 Photocoupler 95,96 Zener diode 97 Voltage limiting means 98,132 Current mirror means 106,107 Logical product negating means 109 Signal processing means 120,138 P-channel type MOS-FET 157,158 Logical product means

Claims (26)

[Claims] 1. An N-channel type first IGBT,
P-channel type second IGBT, first and second diodes, current control means 1 having a current output terminal for controlling a current flowing out from the current output terminal, and the current having a current input terminal A current control means 2 for controlling a current flowing from the input terminal and a DC main power supply are provided, and the collector of the first IGBT, the cathode of the first diode, and the positive terminal of the DC main power supply are connected to each other. The collector of the IGBT, the anode of the second diode, and the negative terminal of the DC main power supply are connected, and the emitter of the first IGBT, the anode of the first diode, the emitter of the second IGBT, and the cathode of the second diode are connected. The gate of the first IGBT, the gate of the second IGBT, the current output terminal of the current control means 1 and the current control means 2 are connected to each other.
Of the first or second IGBT, and a resistor and a voltage limiting means having a Zener phenomenon for positive and negative bidirectional voltages are connected in parallel between the gate and the emitter of the first or second IGBT. The current control unit 1 and the current control unit 2 set a current flowing out from the current output terminal of the current control unit 1 as a first current value and a current flowing in from a current input terminal of the current control unit 2 as a seventh current value. And a current flowing out from the current output terminal of the current control means 1 as a second current value and a current flowing in from the current input terminal of the current control means 2 as an eighth current value. And a second state in which the current flowing out from the current output terminal of the current control means 1 is a fifth current value and the current flowing in from the current input terminal of the current control means 2 is a third current value State 3 A fourth state in which a current flowing out from the current output terminal of the current control means 1 is a sixth current value and a current flowing in from the current input terminal of the current control means 2 is a fourth current value, and the current control There is a fifth state in which a current flowing out from the current output terminal of the means 1 is a ninth current value and a current flowing in from the current input terminal of the current control means 2 is also a ninth current value. The current value is larger than the seventh current value, the second current value is larger than the eighth current value, and the third current value is larger than the fifth current value. Also has a larger current value, the fourth current value has a larger current value than the sixth current value, and the difference between the first current value and the seventh current value is the second current value and the second current value. A difference between the eighth current value and a difference between the third current value and the fifth current value. It is set to be larger than the difference between the fourth current value and the sixth current value so that only the second state and the fifth state can be shifted from the first state, and the third state can be changed from the second state. And 5th state only, from 3rd state to 4th state and 5th state only, from 4th state to 1st state and 5th state only An output circuit for a PWM inverter, which is configured to be capable of shifting from the fifth state to at least the first state and the third state. 2. An N-channel type first IGBT,
A second P-channel type IGBT, first and second diodes, a current inflow terminal, first and second current outflow terminals, and a current corresponding to the current flowing out from the second current outflow terminal. Current mirror means 1 which functions to flow out from the first current outflow terminal; current control means 3 which has a current input terminal and controls a current flowing in from the current input terminal; A current control means 2 for controlling a current flowing from an input terminal, a DC main power supply, and a first DC power supply in which a minus terminal is connected to a plus terminal of the DC main power supply are provided, and a collector of the first IGBT and a first IGBT are provided. The cathode of the first diode is connected to the positive terminal of the DC main power supply, and the collector of the second IGBT is connected to the anode of the second diode and the negative terminal of the DC main power supply. Connecting the emitter of the first IGBT and the anode of the first diode, the emitter of the second IGBT and the cathode of the second diode, the gate of the first IGBT, the gate of the second IGBT and the current mirror means. The first current outflow terminal of No. 1 and the current input terminal of the current control means 2 are connected, and the second current outflow terminal of the current mirror means 1 and the current control means 3 are connected.
Current input terminal of the first DC power supply and the current inflow terminal of the current mirror means 1 are connected to each other, and a resistance and both positive and negative are provided between the gate and the emitter of the first or second IGBT. It has a configuration in which voltage limiting means having a Zener phenomenon with respect to a forward voltage is connected in parallel, and the current mirror means 1 and the current control means 2 are provided.
A first current value is a current flowing out from a first current outflow terminal of the current mirror means 1 and a seventh current value is a current flowing in from a current input terminal of the current control means 2.
And a current flowing out from the first current outflow terminal of the current mirror means 1 as a second current value and a current flowing in from the current input terminal of the current control means 2 as an eighth current value
And a current flowing out from the first current outflow terminal of the current mirror means 1 as a fifth current value and a current flowing in from the current input terminal of the current control means 2 as a third current value.
And a current flowing out from the first current outflow terminal of the current mirror means 1 as a sixth current value and a current flowing in from the current input terminal of the current control means 2 as a fourth current value
And a current flowing out from the first current outflow terminal of the current mirror means 1 as a ninth current value and a current flowing in from the current input terminal of the current control means 2 as a ninth current value.
And the first current value is a current value greater than the seventh current value, the second current value is a current value greater than the eighth current value, the third current value The current value is a current value greater than the fifth current value, the fourth current value is a current value greater than the sixth current value, the first current value and the seventh current value of The difference is greater than the difference between the second current value and the eighth current value, and the difference between the third current value and the fifth current value is the fourth current value and the sixth current value. The second state and the fifth state from the first state, and the third state and the fifth state from the second state. It is possible to move only from the 4th state to the 5th state, and from the 4th state to only the 1st state and the 5th state. An output circuit for a PWM inverter configured to be able to shift from the fifth state to at least the first state and the third state. 3. The current mirror means 1 has third and fourth PNP type transistors, the collector of the third transistor being the first current outflow terminal, and the base of the fourth transistor. The second current outflow terminal is formed by connecting the collector and the base of the third transistor, and the current inflow terminal is formed by connecting the emitters of the third and fourth transistors via resistors. The output circuit for the PWM inverter described. 4. The current mirror means 1 has a PNP-type third transistor, the collector of the third transistor is a first current outflow terminal, and the base of the third transistor is a second current outflow terminal. 3. The output circuit for a PWM inverter according to claim 2, wherein the current outflow terminal is used, and the current inflow terminal is connected to the base and emitter of the third transistor via a resistor. 5. The current mirror means 1 has a PNP type third transistor, an NPN type fifth transistor and a fifth diode, and a collector of the third transistor is a first current outflow terminal. The base of the fifth transistor and the cathode of the fifth diode are connected to form a second current outflow terminal, and the base of the third transistor, the emitter of the fifth transistor, and the fifth One in which the anode of the diode is connected, the base of the fifth transistor and the cathode of the fifth diode are connected, and one in which the emitter of the third transistor is connected via a resistor, respectively.
3. The PWM inverter output circuit according to claim 2, wherein a current inflow terminal is formed by connecting the collectors of the fifth transistors. 6. An N-channel type first IGBT,
P-channel type second IGBT, first and second diodes, current control means 1 having a current output terminal for controlling a current flowing out from the current output terminal, current outflow terminal, first and second A current mirror means 2 having two current inflow terminals and having a function of causing a current corresponding to the current flowing in from the second current inflow terminal to flow in from the first current inflow terminal; The current control means 4 for controlling the current flowing out from the output terminal, the direct current main power source, and the second direct current power source in which the positive terminal is connected to the negative terminal of the direct current main power source are provided, and the collector of the first IGBT and the first The cathode of the first diode is connected to the positive terminal of the DC main power supply, and the collector of the second IGBT is connected to the anode of the second diode and the negative terminal of the DC main power supply. Then, the emitter of the first IGBT, the anode of the first diode, the emitter of the second IGBT, and the cathode of the second diode are connected, and the gate of the first IGBT, the gate of the second IGBT, and the current control are connected. The current output terminal of the means 1 and the first current inflow terminal of the current mirror means 2 are connected, and the current output terminal of the current control means 4 and the second of the current mirror means 2 are connected.
Current inflow terminal is connected, the negative terminal of the second DC power supply is connected to the current outflow terminal of the current mirror means 2, and a resistance and both positive and negative are provided between the gate and emitter of the first or second IGBT. It has a configuration in which voltage limiting means having a Zener phenomenon with respect to a forward voltage is connected in parallel, and the current control means 1 and the current mirror means 2 are provided.
A first current value is a current flowing out from the current output terminal of the current control means 1 and a seventh current value is a current flowing in from the first current inflow terminal of the current mirror means 2.
And a current flowing out from the current output terminal of the current control means 1 as a second current value and a current flowing in from the first current inflow terminal of the current mirror means 2 as an eighth current value.
And a current flowing out from the current output terminal of the current control means 1 as a fifth current value and a current flowing in from the first current inflow terminal of the current mirror means 2 as a third current value.
And a current flowing out from the current output terminal of the current control means 1 as a sixth current value and a current flowing into the first current inflow terminal of the current mirror means 2 as a fourth current value. And the current flowing out from the current output terminal of the current control means 1 is the ninth current value, and the current flowing in from the first current inflow terminal of the current mirror means 2 is also the ninth current value.
And the first current value is a current value greater than the seventh current value, the second current value is a current value greater than the eighth current value, the third current value The current value is a current value greater than the fifth current value, the fourth current value is a current value greater than the sixth current value, the first current value and the seventh current value of The difference is greater than the difference between the second current value and the eighth current value, and the difference between the third current value and the fifth current value is the fourth current value and the sixth current value. The second state and the fifth state from the first state, and the third state and the fifth state from the second state. It is possible to move only from the 4th state to the 5th state, and from the 4th state to only the 1st state and the 5th state. An output circuit for a PWM inverter configured to be able to shift from the fifth state to at least the first state and the third state. 7. The current mirror means 2 has NPN-type sixth and seventh transistors, the collector of the sixth transistor serving as a first current inflow terminal, and the base of the seventh transistor. 7. The second current inflow terminal is formed by connecting the collector and the base of the sixth transistor, and the current outflow terminal is formed by connecting to the emitters of the sixth and seventh transistors through resistors. The output circuit for the PWM inverter described. 8. The current mirror means 2 has a sixth transistor of NPN type, the collector of the sixth transistor serves as a first current inflow terminal, and the base of the sixth transistor serves as a second transistor. 7. The output circuit for a PWM inverter according to claim 6, wherein a current inflow terminal is used, and the base and the emitter of the sixth transistor are respectively connected via a resistor as a current outflow terminal. 9. The current mirror means 2 has an NPN type sixth transistor, a PNP type eighth transistor and a sixth diode, and the collector of the sixth transistor is a first current inflow terminal. The base of the eighth transistor and the anode of the sixth diode are connected to form a second current inflow terminal, and the base of the sixth transistor, the emitter of the eighth transistor, and the sixth transistor A diode connected to the cathode, a base connected to the eighth transistor and an anode to the sixth diode, and a diode connected to the emitter of the sixth transistor via a resistor, respectively.
7. The PWM inverter output circuit according to claim 6, wherein a current output terminal is formed by connecting the collector of the eighth transistor. 10. The method according to claim 1, wherein the fifth current value, the sixth current value, the seventh current value, the eighth current value or the ninth current value is set to 0. An output circuit for a PWM inverter according to claim 1. 11. The voltage limiting means having a Zener phenomenon for positive and negative bidirectional voltages is a Zener diode in which anodes or cathodes of the two are connected in common and in series. P described in
Output circuit for WM inverter. 12. An N-channel type first IGBT.
, P-channel type second IGBT, first and second diodes, current inflow terminal and first and second
Current mirror means 1 which has a current outflow terminal and has a function of causing a current proportional to the current flowing out from the second current outflow terminal to flow out from the first current outflow terminal; a current output terminal; Current control means 5 which has a current input terminal and is capable of independently varying the current value flowing into the first and second current input terminals in three stages including 0.
A direct current main power supply, a first direct current power supply in which a negative terminal is connected to a positive terminal of the direct current main power supply, and a second direct current power supply in which a positive terminal is connected to a negative terminal of the direct current main power supply, The collector of the first IGBT and the cathode of the first diode are connected to the positive terminal of the DC main power supply, and the second IG
The collector of the BT, the anode of the second diode, and the negative terminal of the DC main power supply are connected to each other, and the emitter of the first IGBT, the anode of the first diode, and the second IGBT are connected.
Is connected to the cathode of the second diode, the gate of the first IGBT, the gate of the second IGBT, the first current outflow terminal of the current mirror means 1 and the first current of the current control means 5. The input terminal is connected, the positive terminal of the first DC power source and the current inflow terminal of the current mirror means 1 are connected, the second current outflow terminal of the current mirror means 1 and the second current control means 5 are connected. The current input terminal is connected, and the current output terminal of the current control means 5 is connected to the negative terminal of the second DC power source, and the first or second I
The current control means 5 has a structure in which a voltage limiting means having a Zener phenomenon for positive and negative bidirectional voltages is connected between the gate and the emitter of the GBT, and the current control means 5 supplies a current flowing into the first current input terminal. Is 0 and the current flowing into the second current input terminal is the first
And a second state in which the current flowing into the first current input terminal is 0 and the current flowing into the second current input terminal is smaller than the first current value. And a third state in which the current flowing into the second current input terminal is 0 and the current flowing into the first current input terminal is the third current value, and the second current input terminal The current flowing into the first current input terminal is set to 0
Has a fourth state in which a fourth current value is smaller than the current value of, and sequentially transits from the first state to the fourth state and then to the first state after the fourth state. An output circuit for a PWM inverter, which is configured to repeatedly transit from a state 1 to a fourth state. 13. The current mirror means 1 has third and fourth PNP type transistors, and the third
The collector of the transistor is used as the first current outflow terminal,
The base and collector of the fourth transistor and the third transistor
13. The PWM inverter according to claim 12, wherein the one to which the base of the transistor is connected is the second current outflow terminal, and the one to which the emitters of the third and fourth transistors are respectively connected through the resistors is the current inflow terminal. Output circuit. 14. The current mirror means 1 has a PNP-type third transistor, the collector of the third transistor serves as a first current outflow terminal, and the base of the third transistor serves as a second current output terminal. 13. A current outflow terminal, and a current inflow terminal connected to the base and emitter of the third transistor via a resistor, respectively.
The output circuit for the PWM inverter described. 15. The current mirror means 1 has a third transistor of PNP type, a fifth transistor of NPN type and a fifth diode, and a collector of the third transistor is a first current outflow terminal. The base of the fifth transistor and the cathode of the fifth diode are connected to form a second current outflow terminal, and the base of the third transistor, the emitter of the fifth transistor, and the fifth One in which the anode of the diode is connected, the base of the fifth transistor and the cathode of the fifth diode are connected, and one in which the emitter of the third transistor is connected via a resistor, respectively.
13. The output circuit for a PWM inverter according to claim 12, wherein the collector of the fifth transistor is connected to serve as a current inflow terminal. 16. An N-channel type first IGBT.
, P-channel type second IGBT, first and second diodes, current outflow terminal and first and second
Current mirror means 2 which has a current inflow terminal and has a function of causing a current proportional to the current flowing in from the second current inflow terminal to flow in from the first current inflow terminal, and a current input terminal and first and second current input terminals. With the current output terminal of the first
And the current control means 6 capable of independently varying the current value flowing out from the second current output terminal in three steps including 0.
A direct current main power supply, a first direct current power supply in which a negative terminal is connected to a positive terminal of the direct current main power supply, and a second direct current power supply in which a positive terminal is connected to a negative terminal of the direct current main power supply, The collector of the first IGBT and the cathode of the first diode are connected to the positive terminal of the DC main power supply, and the second IG
The collector of the BT, the anode of the second diode, and the negative terminal of the DC main power supply are connected to each other, and the emitter of the first IGBT, the anode of the first diode, and the second IGBT are connected.
Is connected to the cathode of the second diode, the gate of the first IGBT, the gate of the second IGBT, the first current inflow terminal of the current mirror means 2, and the first current of the current control means 6. The output terminal is connected, the positive terminal of the first DC power source is connected to the current input terminal of the current control means 6, and the second current inflow terminal of the current mirror means 2 and the second current control means 6 are connected. The current output terminal is connected, the current outflow terminal of the current mirror means 2 is connected to the negative terminal of the second DC power source, and the first or second I
The current control means 6 has a structure in which a voltage limiting means having a Zener phenomenon with respect to positive and negative bidirectional voltages is connected between the gate and the emitter of the GBT, and the current control means 6 outputs a current flowing from the first current output terminal. Is 0 and the current flowing out from the second current output terminal is the first current value, and the current flowing out from the first current output terminal is 0 and the current flowing out from the second current output terminal is 0. Is a second current value smaller than the first current value, and a current flowing out from the second current output terminal is 0, and a current flowing out from the first current output terminal is a third state. A third state in which a current value is set, and a current flowing out from the second current output terminal is set to 0, and a current flowing out from the first current output terminal is set to a fourth current value smaller than the third current value. Has a fourth state, and a fourth state in order from the first state. To the first state and then to the first state after the fourth state.
An output circuit for a PWM inverter, which is configured to sequentially and repeatedly shift from the above state to the fourth state. 17. The current mirror means 2 has NPN type sixth and seventh transistors, and
The collector of the transistor is used as the first current inflow terminal,
The base and collector of the seventh transistor and the sixth transistor
17. The PWM inverter according to claim 16, wherein the one to which the base of the transistor is connected is the second current inflow terminal, and the one to which the emitters of the sixth and seventh transistors are respectively connected through the resistors is the current outflow terminal. Output circuit. 18. The current mirror means 2 has a sixth transistor of NPN type, the collector of the sixth transistor serves as a first current inflow terminal, and the base of the sixth transistor serves as a second current inflow terminal. 17. A current outflow terminal, and a current outflow terminal connected to the base and emitter of the sixth transistor via a resistor, respectively.
The output circuit for the PWM inverter described. 19. The current mirror means 2 has a sixth transistor of NPN type, an eighth transistor of PNP type and a sixth diode, and a collector of the sixth transistor is a first current inflow terminal. The base of the eighth transistor and the anode of the sixth diode are connected to form a second current inflow terminal, and the base of the sixth transistor, the emitter of the eighth transistor, and the sixth transistor A diode connected to the cathode, a base connected to the eighth transistor and an anode to the sixth diode, and a diode connected to the emitter of the sixth transistor via a resistor, respectively.
17. The output circuit for a PWM inverter according to claim 16, wherein a current output terminal is formed by connecting the collector of the eighth transistor. 20. The voltage limiting means having a Zener phenomenon for positive and negative bidirectional voltages is two Zener diodes whose anodes or cathodes are connected in common and in series. An output circuit for a PWM inverter according to any one of 1. 21. An N-channel type first IGBT.
, A P-channel type second IGBT, first and second diodes, and a PNP type third and fourth
Current control means capable of independently varying the value of the current flowing into the first and second current input terminals in three stages including 0, the current output terminal and the first and second current input terminals. 5, a DC main power supply, a first DC power supply in which a minus terminal is connected to the plus terminal of the DC main power supply, and a second DC power supply in which a plus terminal is connected to the minus terminal of the DC main power supply, The collector of the first IGBT, the cathode of the first diode and the positive terminal of the DC main power supply are connected, and the collector of the second IGBT and the anode of the second diode and the negative terminal of the DC main power supply are connected. The emitter of the first IGBT is connected to the anode of the first diode, the emitter of the second IGBT is connected to the cathode of the second diode, and the gate of the first IGBT and the second IG are connected. The gate of BT, the collector of the third transistor and the first current input terminal of the current control means 5 are connected, and the positive terminal of the first DC power source and the emitters of the third and fourth transistors are respectively connected via resistors. The base and collector of the fourth transistor, the base of the third transistor and the second current input terminal of the current control means 5 are connected, and the current output terminal of the current control means 5 is connected to the second direct current The current control is connected to a negative terminal of a power source, and a voltage limiting means having a Zener phenomenon for positive and negative bidirectional voltages is connected between the gate and the emitter of the first or second IGBT. The means 5 sets the current flowing into the first current input terminal to 0 and the current flowing into the second current input terminal to the first current.
And a second state in which the current flowing into the first current input terminal is 0 and the current flowing into the second current input terminal is smaller than the first current value. And a third state in which the current flowing into the second current input terminal is 0 and the current flowing into the first current input terminal is the third current value, and the second current input terminal The current flowing into the first current input terminal is set to 0
Has a fourth state in which a fourth current value is smaller than the current value of, and sequentially transits from the first state to the fourth state and then to the first state after the fourth state. An output circuit for a PWM inverter, which is configured to repeatedly transit from a state 1 to a fourth state. 22. N-channel type first IGBT
A P-channel type second IGBT, first and second diodes, a PNP-type third transistor, a current output terminal, and first and second current input terminals. The current control means 5 capable of independently varying the current value flowing into the second current input terminal in three steps including 0, the DC main power source, and the first terminal in which the minus terminal is connected to the plus terminal of the DC main power source. A direct current power supply; and a second direct current power supply in which a positive terminal is connected to the negative terminal of the direct current main power supply, and the collector of the first IGBT, the cathode of the first diode and the positive terminal of the direct current main power supply are connected. Connecting the collector of the second IGBT, the anode of the second diode and the negative terminal of the DC main power supply, and the emitter of the first IGBT, the anode of the first diode and the second The emitter of the GBT is connected to the cathode of the second diode, the gate of the first IGBT, the gate of the second IGBT, the collector of the third transistor and the first current input terminal of the current control means 5 are connected. , The positive terminal of the first DC power source is connected to the emitter and the base of the third transistor via resistors, respectively, and the base of the third transistor is connected to the second current input terminal of the current control means 5, The current output terminal of the current control means 5 is connected to the negative terminal of the second DC power source, and has a Zener phenomenon between the gate and the emitter of the first or second IGBT with respect to positive and negative bidirectional voltages. The current control means 5 has a configuration in which a voltage limit means is connected, and the current control means 5 sets the current flowing into the first current input terminal to 0 and sets the current flowing into the second current input terminal to the first current input terminal.
And a second state in which the current flowing into the first current input terminal is 0 and the current flowing into the second current input terminal is smaller than the first current value. And a third state in which the current flowing into the second current input terminal is 0 and the current flowing into the first current input terminal is the third current value, and the second current input terminal The current flowing into the first current input terminal is set to 0
Has a fourth state in which a fourth current value is smaller than the current value of, and sequentially transits from the first state to the fourth state and then to the first state after the fourth state. An output circuit for a PWM inverter, which is configured to repeatedly transit from a state 1 to a fourth state. 23. The voltage limiting means having a Zener phenomenon for positive and negative bidirectional voltages is two Zener diodes whose anodes or cathodes are connected in common and in series. PW described
Output circuit for M inverter. 24. A first IGBT of N channel type.
, P-channel type second IGBT, first and second diodes, NPN type sixth and seventh
Current control means capable of independently varying the value of the current flowing out from the first and second current output terminals in three stages including 0, the current input terminal and the first and second current output terminals. 6, a DC main power supply, a first DC power supply in which a minus terminal is connected to the plus terminal of the DC main power supply, and a second DC power supply in which a plus terminal is connected to the minus terminal of the DC main power supply, The collector of the first IGBT, the cathode of the first diode and the positive terminal of the DC main power supply are connected, and the collector of the second IGBT and the anode of the second diode and the negative terminal of the DC main power supply are connected. The emitter of the first IGBT and the anode of the first diode are connected to the emitter of the second IGBT and the cathode of the second diode, and the gate of the first IGBT and the second I The gate of the GBT, the collector of the sixth transistor and the first current output terminal of the current control means 6 are connected, and the negative terminal of the second DC power source and the emitters of the sixth and seventh transistors are respectively connected via resistors. Connecting the base and collector of the seventh transistor, the base of the sixth transistor and the second current output terminal of the current control means 6, and connecting the current input terminal of the current control means 6 to the first direct current. The current control is connected to a positive terminal of a power source, and a voltage limiting means having a Zener phenomenon for positive and negative bidirectional voltages is connected between the gate and the emitter of the first or second IGBT. A first state in which the means 6 sets the current flowing out from the first current output terminal to 0 and the current flowing out from the second current output terminal to a first current value; and the first current output terminal The second state in which the current flowing out from the second current output terminal is 0 and the current flowing out from the second current output terminal is a second current value smaller than the first current value, and the current flowing out from the second current output terminal. Is 0 and the current flowing out of the first current output terminal is the third current value, and the current flowing out of the second current output terminal is 0 and the current flowing out of the first current output terminal is 0. Has a fourth state in which is a fourth current value smaller than the third current value, transitions from the first state to the fourth state in order, and then to the first state after the fourth state. First to move
An output circuit for a PWM inverter, which is configured to sequentially and repeatedly shift from the above state to the fourth state. 25. A first IGBT of N-channel type
A second P-channel type IGBT, first and second diodes, an NPN type sixth transistor, a current input terminal and first and second current output terminals. The current control means 6 capable of independently varying the current value flowing out from the second current output terminal in three steps including 0, the DC main power source, and the first terminal in which the minus terminal is connected to the plus terminal of the DC main power source. DC power supply,
A second direct current power source in which a positive terminal is connected to a negative terminal of the direct current main power source, and a collector of the first IGBT, a cathode of the first diode, and a positive terminal of the direct current main power source are connected; The collector of the IGBT, the anode of the second diode, and the negative terminal of the DC main power supply are connected, and the emitter of the first IGBT, the anode of the first diode, the emitter of the second IGBT, and the cathode of the second diode are connected. The gate of the first IGBT, the gate of the second IGBT, the collector of the sixth transistor and the first current output terminal of the current control means 6 are connected to each other, and the negative terminal of the second DC power source is connected to the second terminal. The emitter and base of the transistor of 6 are connected via a resistor,
The base of the sixth transistor and the second current output terminal of the current control means 6 are connected, the current input terminal of the current control means 6 is connected to the plus terminal of the first DC power supply, and the first or second Of the IGBT, voltage limit means having a Zener phenomenon for positive and negative bidirectional voltages is connected between the gate and emitter of the IGBT, and the current control means 6 flows out from the first current output terminal. The first state in which the current is 0 and the current flowing out from the second current output terminal is the first current value, and the current flowing out from the first current output terminal is 0 and flows out from the second current output terminal A second state in which the current is a second current value smaller than the first current value, and a current flowing out from the second current output terminal is 0 and a current flowing out from the first current output terminal is third The third state with the current value of And a fourth state in which the current flowing out of the current output terminal is 0 and the current flowing out of the first current output terminal is a fourth current value smaller than the third current value. From the 4th state to the 4th state and then to the 1st state after the 4th state
An output circuit for a PWM inverter, which is configured to sequentially and repeatedly shift from the above state to the fourth state. 26. The voltage limiting means having a Zener phenomenon for positive and negative bidirectional voltages is two Zener diodes whose anodes or cathodes are connected in common and in series. PW described
Output circuit for M inverter.