JPH06314750A - Semiconductor element mounting board and manufacture thereof - Google Patents

Semiconductor element mounting board and manufacture thereof

Info

Publication number
JPH06314750A
JPH06314750A JP12790093A JP12790093A JPH06314750A JP H06314750 A JPH06314750 A JP H06314750A JP 12790093 A JP12790093 A JP 12790093A JP 12790093 A JP12790093 A JP 12790093A JP H06314750 A JPH06314750 A JP H06314750A
Authority
JP
Japan
Prior art keywords
substrate
lead
semiconductor element
adhesive layer
thermal adhesive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12790093A
Other languages
Japanese (ja)
Inventor
Toshio Ofusa
俊雄 大房
Taketo Tsukamoto
健人 塚本
Sotaro Toki
荘太郎 土岐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toppan Inc
Original Assignee
Toppan Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toppan Printing Co Ltd filed Critical Toppan Printing Co Ltd
Priority to JP12790093A priority Critical patent/JPH06314750A/en
Publication of JPH06314750A publication Critical patent/JPH06314750A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/403Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To provide a method of easily manufacturing a semiconductor element mounting board at a low cost, wherein a board and a lead are pasted together into one piece and electrically connected together at the same time. CONSTITUTION:A board 1 on which a wiring pattern is formed for mounting a semiconductor element and a lead 8 are bonded together into one piece through the intermediary of a thermal adhesive layer 3 by thermocompression, and the electrode terminal 2 of the board 1 and the lead 8 are electrically connected together through the intermediary of a conductive material 7.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体素子を実装して用
いる半導体素子搭載用基板及びその製造方法に関し、詳
しくは基板とリードとを貼り合せて一体化した半導体素
子搭載用基板及びその製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element mounting substrate on which a semiconductor element is mounted and a method of manufacturing the same, and more specifically, a semiconductor element mounting substrate and a method of manufacturing the same in which a substrate and leads are bonded together. It is about.

【0002】[0002]

【従来の技術及び発明が解決しようとする課題】従来、
半導体素子を実装するプリント配線基板とリード(リー
ドフレーム等)との接続は半田付けによって行ってい
た。
2. Description of the Related Art Conventionally, the problems to be solved by the invention
A printed wiring board on which a semiconductor element is mounted and leads (such as a lead frame) are connected by soldering.

【0003】しかしながら、上記構成によると、基板と
リードとの電気的な接続部分と両者を物理的に固定する
部分とが半田付けした部分の一箇所だけなので、リード
ピッチを狭小化しようとする場合基板とリードとの接着
が非常に難しく不安定で、後に基板とリードとの接続不
良を起こしやすいという欠点がある。
However, according to the above-mentioned structure, the electrical connection between the substrate and the lead and the portion for physically fixing the two are only at one soldered portion, so that the lead pitch is narrowed. Adhesion between the substrate and the lead is very difficult and unstable, and there is a drawback that a connection failure between the substrate and the lead is likely to occur later.

【0004】本発明は上記従来の欠点に鑑みなされたも
ので、その目的は基板とリードとを貼り合せて一体化す
ると同時に電気的な接続を可能にした構造の半導体素子
搭載用基板及びこのような基板を安価で簡単に製造する
方法を提供することにある。
The present invention has been made in view of the above-mentioned conventional drawbacks, and an object thereof is a substrate for mounting a semiconductor element having a structure in which a substrate and a lead are bonded and integrated with each other, and at the same time, an electrical connection is possible. Another object of the present invention is to provide a method for inexpensively and easily manufacturing a flexible substrate.

【0005】[0005]

【課題を解決するための手段】上記目的を達成するた
め、請求項1の発明は、半導体素子を搭載するための配
線パターンを形成した基板とリードとを熱圧着により固
定して一体化するとともに前記基板の電極端子と前記リ
ードとを導電物質を介して電気的に接続してなることを
特徴としている。
In order to achieve the above-mentioned object, the invention of claim 1 is to integrate a substrate and a lead, on which a wiring pattern for mounting a semiconductor element is formed, by thermocompression bonding. The electrode terminal of the substrate and the lead are electrically connected via a conductive material.

【0006】また、請求項2の発明は、半導体素子を搭
載するための配線パターンを形成した基板の表面に熱接
着層を設けるとともに前記基板の電極端子が露出するよ
うにこの部分の熱接着層を除去して凹部を形成し、次に
この熱接着層の凹部に導電物質を充填した後、前記基板
とこの基板に固定するリードとを熱圧着することを特徴
としている。
According to a second aspect of the present invention, a thermal adhesive layer is provided on the surface of the substrate on which a wiring pattern for mounting a semiconductor element is formed, and the thermal adhesive layer in this portion is exposed so that the electrode terminals of the substrate are exposed. Is removed to form a concave portion, and then the concave portion of the thermal adhesive layer is filled with a conductive material, and then the substrate and the lead fixed to the substrate are thermocompression bonded.

【0007】また、請求項3の発明は、半導体素子を搭
載するための配線パターンを形成した基板の表面に熱接
着層を設け、その上に保護フィルムを貼り合せるととも
に前記基板の電極端子が露出するようにこの部分の熱接
着層及び保護フィルムを除去して凹部を形成し、次にこ
の凹部に導電物質を充填した後、前記保護フィルムを剥
離し、前記基板とこの基板に固定するリードとを位置合
せして熱圧着することを特徴としている。
According to a third aspect of the present invention, a thermal adhesive layer is provided on the surface of the substrate on which a wiring pattern for mounting a semiconductor element is provided, and a protective film is attached thereon, and the electrode terminals of the substrate are exposed. As described above, the heat-adhesive layer and the protective film in this portion are removed to form a concave portion, and then the concave portion is filled with a conductive substance, and then the protective film is peeled off, and the substrate and leads fixed to the substrate are formed. It is characterized by aligning and thermocompression bonding.

【0008】さらに、請求項4の発明は、請求項2また
は3の発明において、基板と熱圧着するリードの先端部
分に凹部又は凹凸部を形成したことを特徴としている。
Further, the invention of claim 4 is characterized in that, in the invention of claim 2 or 3, a concave portion or an uneven portion is formed at a tip portion of a lead which is thermocompression bonded to the substrate.

【0009】[0009]

【作用】請求項1に係る発明にあっては、基板の電極端
子とリードとが導電物質を介して電気的に接続されてい
て、且つ基板とリードとは熱圧着により固定され一体化
しているため、基板とリードとの接着力が非常に強く強
固となり、後に基板とリードとの接続不良が起こらな
い。
In the invention according to claim 1, the electrode terminal of the substrate and the lead are electrically connected through the conductive material, and the substrate and the lead are fixed and integrated by thermocompression bonding. Therefore, the adhesive force between the substrate and the lead is very strong and strong, and a connection failure between the substrate and the lead does not occur later.

【0010】また、請求項2に係る発明にあっては、基
板の表面に熱接着層を設けるとともに基板の電極端子が
露出するようにこの部分の熱接着層を除去して凹部を形
成し、この凹部に導電物質を充填した後、基板とリード
とを熱圧着することにより、基板とこれに接続する多数
のリードとが一括接続され、基板と多数のリードとが熱
圧着により一体化され且つ電気的に接続された構造の半
導体素子搭載用基板を安価に且つ簡単に製造できる。
Further, in the invention according to claim 2, a thermal adhesive layer is provided on the surface of the substrate, and the thermal adhesive layer in this portion is removed to form a recess so that the electrode terminals of the substrate are exposed, After filling the concave portion with a conductive material, the substrate and the leads are thermocompression bonded, whereby the substrate and a large number of leads connected thereto are collectively connected, and the substrate and a large number of leads are integrated by thermocompression bonding and A semiconductor element mounting substrate having an electrically connected structure can be manufactured inexpensively and easily.

【0011】また、請求項3に係る発明にあっては、基
板の表面に熱接着層を設け、その上にさらに保護フィル
ムを貼り合せ、基板の電極端子の部分の熱接着層及び保
護フィルムを除去し、出来た凹部に導電物質を充填した
後に、この保護フィルムを剥離するようにしたので、凹
部に導電物質を充填する際に凹部以外の部分に付着した
導電物質をきれいに取り除くことができ、しかも導電物
質が熱接着層の表面よりも少し盛り上がって形成され、
さらに盛り上がりの高さを保護フィルムの厚みを変える
ことにより自由に調整できるため、リードとの接続がよ
り確実になる。
Further, in the invention according to claim 3, a heat-adhesive layer is provided on the surface of the substrate, and a protective film is further adhered thereon, and the heat-adhesive layer and the protective film of the electrode terminal portion of the substrate are attached. Since the protective film is peeled off after filling with the conductive material in the formed recess, the conductive material attached to the portion other than the recess can be removed cleanly when filling the conductive material in the recess, Moreover, the conductive material is formed slightly higher than the surface of the thermal bonding layer,
Furthermore, the height of the rise can be freely adjusted by changing the thickness of the protective film, so that the connection with the lead becomes more reliable.

【0012】さらに、請求項4に係る発明にあっては、
リードの先端部分に凹部又は凹凸部を形成することによ
り、リードを基板と熱圧着した際に導電物質がリードか
らはみ出し、隣のリード等に付着してショートするよう
な場合の如き不具合を防止できるので、リードピッチの
狭小化に都合が良い。
Further, in the invention according to claim 4,
By forming a recess or an uneven portion at the tip of the lead, it is possible to prevent problems such as when the lead is thermocompression-bonded with the substrate, the conductive material protrudes from the lead and adheres to the adjacent lead or the like to cause a short circuit. Therefore, it is convenient for narrowing the lead pitch.

【0013】[0013]

【実施例】以下、添付図面を参照して本発明の実施例を
詳述する。
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

【0014】図1乃至図3は本発明の一実施例を示すも
ので、図1は半導体素子搭載用基板の要部断面図、図2
はその要部平面図、図3はその製造方法を工程順に示す
要部断面図である。
FIGS. 1 to 3 show an embodiment of the present invention. FIG. 1 is a sectional view of a main part of a semiconductor element mounting substrate, FIG.
Is a plan view of relevant parts, and FIG. 3 is a sectional view of relevant parts showing the manufacturing method in the order of steps.

【0015】図1に示すように、本実施例の構成によれ
ば、半導体素子搭載用基板10は、基板1とリード8と
が熱接着層3を介して熱圧着により固定されており、且
つ基板1の電極端子2とリード8とが例えば半田のよう
な導電物質7を介して電気的に接続されている。
As shown in FIG. 1, according to the structure of the present embodiment, the semiconductor element mounting substrate 10 has the substrate 1 and the leads 8 fixed by thermocompression bonding via the thermal adhesive layer 3, and The electrode terminals 2 of the substrate 1 and the leads 8 are electrically connected to each other via a conductive material 7 such as solder.

【0016】上記基板1は、半導体素子を搭載するため
のプリント配線基板で、種々の回路の配線パターンが形
成されている。基板1は単層構成の場合と、内層パター
ンを形成した絶縁層を層状に積層して得る多層構成の場
合とがあるが、本発明ではどちらの構成であってもかま
わない。このようなプリント配線基板は、従来公知の、
例えばパターンめっき法等を用いて製造することができ
る。
The board 1 is a printed wiring board on which a semiconductor element is mounted, on which wiring patterns of various circuits are formed. The substrate 1 may have a single-layer structure or a multi-layer structure obtained by laminating insulating layers having an inner layer pattern in layers, but in the present invention, either structure may be used. Such a printed wiring board is conventionally known.
For example, it can be manufactured using a pattern plating method or the like.

【0017】上記リード8は、一般に半導体素子のパッ
ケージに使用されるリードフレームの形態をなしてい
る。すなわち、このようなリードフレームは、基板1の
電極端子2と電気的に接続され且つこの基板1を中心と
して略放射状に配置される多数のリード8と、これら多
数のリード8を一体に支えるフレームとを具備する。こ
のリード8を有するリードフレームは、1枚の金属板を
機械的な打抜きやエッチングにより上記のような形状に
加工して作製される。
The leads 8 are in the form of lead frames generally used for semiconductor device packages. That is, such a lead frame is a frame that supports a large number of leads 8 that are electrically connected to the electrode terminals 2 of the substrate 1 and that are arranged substantially radially around the substrate 1, and that integrally support the plurality of leads 8. And. The lead frame having the leads 8 is manufactured by processing a single metal plate into the above-described shape by mechanical punching or etching.

【0018】次に、上記半導体素子搭載用基板10の製
造方法を説明する。
Next, a method of manufacturing the semiconductor element mounting substrate 10 will be described.

【0019】図3の(a)に示すように、まず前述の如
くして製造された基板1の表面(リード8を接続しよう
とする面)に熱接着層3を設ける。該熱接着層3には熱
硬化性の樹脂、例えばエポキシとナイロンの混合樹脂
(市販品として例えば東亜合成(株)製BX−60等が
ある。)を使用する。熱接着層3を設ける方法は、基板
1に直接塗布してもよいし、あるいはシート状に加工し
たものを基板1に貼り合せてもよい。なお、熱接着層3
は少なくともリード8を固定する部位に設ければよい
が、基板1の全面に設けることも出来る。このように基
板1の全面に設けた場合には同時に他の回路を保護する
ことが出来るという効果を有する。
As shown in FIG. 3A, first, the thermal adhesive layer 3 is provided on the surface (the surface to which the leads 8 are to be connected) of the substrate 1 manufactured as described above. A thermosetting resin, for example, a mixed resin of epoxy and nylon (such as BX-60 manufactured by Toagosei Co., Ltd. as a commercially available product) is used for the thermal adhesive layer 3. As the method for providing the thermal adhesive layer 3, the substrate 1 may be directly applied, or a sheet-shaped product may be attached to the substrate 1. The thermal adhesive layer 3
It suffices that it is provided at least in a portion where the leads 8 are fixed, but it can also be provided on the entire surface of the substrate 1. In this way, when it is provided on the entire surface of the substrate 1, there is an effect that other circuits can be protected at the same time.

【0020】該熱接着層3の上には更に後で剥離可能な
保護フィルム4を設ける。該保護フィルム4は例えばポ
リエチレンテレフタレートで出来ており、熱接着層3と
シート状に貼り合せたものを使用するのが簡易である。
すなわち、あらかじめ熱接着層3の両面に保護フィルム
4を貼り合せた積層体を作製し、使用時にこの積層体の
一方の保護フィルム4を剥離し、熱接着層3を基板1側
にして貼り合せる。
A protective film 4 which can be peeled off later is further provided on the thermal adhesive layer 3. The protective film 4 is made of, for example, polyethylene terephthalate, and it is easy to use a sheet bonded to the thermal adhesive layer 3 in a sheet form.
That is, a laminate in which the protective films 4 are bonded to both surfaces of the thermal adhesive layer 3 in advance is prepared, and one protective film 4 of the laminate is peeled off at the time of use, and the thermal adhesive layer 3 is bonded to the substrate 1 side. .

【0021】次に、図3の(b)に示すように、リード
8を電気的に接続する基板1の電極端子2が露出するよ
うに、この部分の熱接着層3及び保護フィルム4を例え
ばエキシマレーザーやプラズマエッチング等の手段5を
用いて除去し凹部6を形成する。なお、このような凹部
6を形成する方法として、前記の熱接着層3の両面に保
護フィルム4を貼り合せた積層体に基板1と貼り合せる
前にあらかじめ基板1の電極端子2に対応する部分を金
型等で打抜いて形成しておくこともできる。
Next, as shown in FIG. 3B, the thermal adhesive layer 3 and the protective film 4 in this portion are formed, for example, so that the electrode terminals 2 of the substrate 1 for electrically connecting the leads 8 are exposed. A concave portion 6 is formed by removing it using a means 5 such as an excimer laser or plasma etching. As a method of forming such a recess 6, a portion corresponding to the electrode terminal 2 of the substrate 1 is previously attached to the laminate in which the protective films 4 are attached to both surfaces of the thermal adhesive layer 3 before being attached to the substrate 1. It can also be formed by punching with a die or the like.

【0022】次に、図3の(c)に示す如く、形成した
上記凹部6に導電物質7として例えば半田ペーストを充
填する。導電物質7の充填はディスペンサを使用しても
よいし、穴埋め印刷法でもよい。また、半田ペーストの
代りに熱溶融性の他の導電物質を上記方法で充填しても
よいし、さらに、電解めっき法、無電解めっき法、スー
パーソルダ法等によってもかまわない。要するに、使用
する導電物質7の種類や充填方法については特に問わな
い。
Next, as shown in FIG. 3C, the recess 6 thus formed is filled with, for example, a solder paste as a conductive material 7. The conductive material 7 may be filled using a dispenser or a hole filling printing method. Further, instead of the solder paste, other heat-fusible conductive material may be filled by the above method, and further electrolytic plating method, electroless plating method, super solder method or the like may be used. In short, the type of conductive material 7 used and the filling method are not particularly limited.

【0023】例えば、導電物質7を穴埋め印刷法で充填
する場合には、導電物質7、例えば半田ペーストを保護
フィルム4上に塗布し、これをスキージ等で掻き取るこ
とにより、凹部6のみに導電物質7が充填される。この
とき、凹部6以外の部分にもごく少量の導電物質7が付
着し、残ることもあるが、図3の(d)に示すように、
最上の保護フィルム4を剥離することにより、きれいな
表面が露出するので不都合はない。また、こうすること
によって、凹部6の導電物質7が熱接着層3の表面より
も少し盛り上がって形成される。
For example, when the conductive material 7 is filled by the hole filling printing method, the conductive material 7, for example, a solder paste is applied on the protective film 4 and scraped off with a squeegee or the like so that only the concave portion 6 is conductive. The substance 7 is filled. At this time, a very small amount of the conductive material 7 may adhere to and remain on the portions other than the recess 6, but as shown in FIG.
There is no inconvenience because the clean surface is exposed by peeling off the uppermost protective film 4. Further, by doing so, the conductive substance 7 in the recess 6 is formed so as to be slightly raised above the surface of the thermal bonding layer 3.

【0024】次に、図3の(e)に示すように、基板1
とリード8とを接続する。基板1とリード8との接続に
はまず基板1とリード8とを位置合せして、例えば熱接
着層3に前記のエポキシとナイロンの混合樹脂BX−6
0(東亜合成(株)製)を、導電物質7に半田ペースト
をそれぞれ使用した場合には140℃前後に加熱しなが
ら圧着することで仮止めができる。次に、温度を180
℃前後に上げ、熱接着層3の樹脂を硬化させてリード8
の接着固定を確実なものとし、さらに温度を200℃前
後に上げることで半田ペーストが溶融し、半田が凹部6
内に隙間なく充填される。
Next, as shown in FIG. 3E, the substrate 1
And lead 8 are connected. In order to connect the substrate 1 and the lead 8, first, the substrate 1 and the lead 8 are aligned, and for example, the above-mentioned epoxy-nylon mixed resin BX-6 is applied to the thermal adhesive layer 3.
When 0 (manufactured by Toagosei Co., Ltd.) is used as the conductive material 7, the solder paste can be temporarily fixed by pressure bonding while heating to around 140 ° C. Then set the temperature to 180
The temperature of the lead 8
The adhesive paste is secured, and the solder paste is melted by raising the temperature to around 200 ° C.
Filled inside without any gaps.

【0025】このようにして、基板1とリード8とが熱
圧着による貼り合せによって一体化され且つ両者が電気
的に接続された半導体素子搭載用基板10が出来上が
る。
In this way, the semiconductor element mounting substrate 10 in which the substrate 1 and the leads 8 are integrated by bonding by thermocompression and electrically connected to each other is completed.

【0026】なお、本実施例では、熱接着層3の上に保
護フィルム4を貼り合せ、凹部6に導電物質7を充填し
た後に、保護フィルム4を剥離するようにしたが、導電
物質7の充填方法によっては、必ずしもこのような保護
フィルム4を使用する必要はない。
In this embodiment, the protective film 4 is attached onto the thermal adhesive layer 3, the concave portion 6 is filled with the conductive substance 7, and then the protective film 4 is peeled off. Depending on the filling method, it is not always necessary to use such a protective film 4.

【0027】また、上記のようにリード8を基板1と熱
圧着した際に凹部6の導電物質7がリード8からはみ出
し、隣のリード等に付着してショートするのを防止する
ため、図4の(a)〜(c)に示す如く、リード8の先
端部分に孔8aや溝8b,8c等を形成しておくことも
好ましい態様である。
Further, in order to prevent the conductive material 7 in the recess 6 from protruding from the lead 8 and adhering to an adjacent lead or the like to cause a short circuit when the lead 8 is thermocompression-bonded to the substrate 1 as described above, FIG. As shown in (a) to (c), it is also a preferable embodiment to form holes 8a, grooves 8b, 8c, etc. at the tip portion of the lead 8.

【0028】また、図5に示すように、基板1と固定し
たリード8に例えばエポキシ等の樹脂9をコーティング
して基板1とリード8との接続部分を保護するようにし
てもよい。またさらに、基板1とリード8との電気的接
続箇所は本実施例の図2に示す如く一列に並べて必ずし
も設ける必要はなく、近年の電極密度の増加傾向を考慮
すると、例えば図6に示すように互い違いにずらして千
鳥状に設けることも望ましい。
Further, as shown in FIG. 5, the lead 8 fixed to the substrate 1 may be coated with a resin 9 such as epoxy to protect the connection portion between the substrate 1 and the lead 8. Furthermore, the electrical connection points between the substrate 1 and the leads 8 do not necessarily have to be arranged in a line as shown in FIG. 2 of the present embodiment, and considering the recent tendency of increase in electrode density, for example, as shown in FIG. It is also desirable to stagger them in a staggered manner.

【0029】[0029]

【発明の効果】以上詳細に説明したように、本発明によ
れば、基板とリードとの接着力が非常に強く一体化され
ているので、両者の電気的接続の信頼性が高い構造の半
導体素子搭載用基板を提供することが出来る。
As described in detail above, according to the present invention, since the adhesive force between the substrate and the lead is extremely strong and integrated, the semiconductor having a structure in which the electrical connection between the two is highly reliable. A device mounting board can be provided.

【0030】また、本発明によれば、基板の表面に熱接
着層を設けるとともに基板の電極端子が露出するように
この部分の熱接着層を除去して凹部を形成し、この凹部
に導電物質を充填した後、基板とリードとを熱圧着して
貼り合せることにより、上記構造に係る半導体素子搭載
用基板を安価に且つ簡単に製造することが出来る。
Further, according to the present invention, a thermal adhesive layer is provided on the surface of the substrate, and the thermal adhesive layer in this portion is removed so that the electrode terminals of the substrate are exposed to form a concave portion. After filling the substrate, the substrate and the leads are bonded by thermocompression bonding, so that the semiconductor element mounting substrate having the above structure can be manufactured inexpensively and easily.

【0031】また、上記熱接着層の上に保護フィルムを
貼り合せることにより、上記凹部に導電物質を充填する
際に凹部以外の部分に付着した導電物質をきれいに取り
除くことができ、しかも凹部の導電物質が少し盛り上が
って形成されるので、リードとの接続がより確実にな
る。
Further, by sticking a protective film on the heat-bonding layer, it is possible to cleanly remove the conductive substance adhering to the portion other than the concave portion when the concave portion is filled with the conductive substance, and further the conductive property of the concave portion is improved. Since the substance is formed to be slightly raised, the connection with the lead becomes more reliable.

【0032】またさらに、基板と接続する上記リードの
先端部分に凹部又は凹凸部を形成することにより、リー
ドと基板と熱圧着した際に導電物質がリードからはみ出
し、隣のリード等に付着してショートするような如き不
具合を防止することができる。
Furthermore, by forming a concave portion or a concave-convex portion at the tip end portion of the lead connected to the substrate, the conductive substance sticks out from the lead and adheres to the adjacent lead when the lead and the substrate are thermocompression bonded. It is possible to prevent problems such as short circuit.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を示す半導体素子搭載用基板
の要部断面図である。
FIG. 1 is a sectional view of an essential part of a semiconductor element mounting substrate showing an embodiment of the present invention.

【図2】その要部平面図である。FIG. 2 is a plan view of an essential part thereof.

【図3】その製造方法を工程順に示す要部断面図であ
る。
FIG. 3 is a cross-sectional view of a main part showing the manufacturing method in the order of steps.

【図4】本発明の別の実施例を示す図である。FIG. 4 is a diagram showing another embodiment of the present invention.

【図5】本発明の他の実施例を示す図である。FIG. 5 is a diagram showing another embodiment of the present invention.

【図6】本発明のその他の実施例を示す図である。FIG. 6 is a diagram showing another embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 基板 2 電極端子 3 熱接着層 4 保護フィルム 5 エッチング手段 6 凹部 7 導電物質 8 リード 9 オーバーコート樹脂 10 半導体素子搭載用基板 1 Substrate 2 Electrode Terminal 3 Thermal Adhesive Layer 4 Protective Film 5 Etching Means 6 Recess 7 Recess 7 Conductive Material 8 Lead 9 Overcoat Resin 10 Semiconductor Element Mounting Substrate

─────────────────────────────────────────────────────
─────────────────────────────────────────────────── ───

【手続補正書】[Procedure amendment]

【提出日】平成5年12月22日[Submission date] December 22, 1993

【手続補正1】[Procedure Amendment 1]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】0016[Correction target item name] 0016

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【0016】 上記基板1は、半導体素子を搭載するた
めのプリント配線基板で、種々の回路の配線パターンが
形成されている。基板1は単層構成の場合と、内層パタ
ーンを形成した絶縁層を層状に積層して得る多層構成の
場合とがあるが、本発明ではどちらの構成であってもか
まわない。また、基板1は、電源層またはグランド層
(接地層)、あるいはその両方を設けることにより電気
的特性を向上させた基板を用いることも可能である。
のようなプリント配線基板は、従来公知の、例えばパタ
ーンめっき法等を用いて製造することができる。
The board 1 is a printed wiring board on which a semiconductor element is mounted, and wiring patterns of various circuits are formed. The substrate 1 may have a single-layer structure or a multi-layer structure obtained by laminating insulating layers having an inner layer pattern in layers, but in the present invention, either structure may be used. The substrate 1 is a power supply layer or a ground layer.
(Grounding layer), or both to provide electricity
It is also possible to use a substrate having improved optical characteristics. Such a printed wiring board can be manufactured using a conventionally known method such as a pattern plating method.

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 半導体素子を搭載するための配線パター
ンを形成した基板とリードとを熱圧着により固定して一
体化するとともに前記基板の電極端子と前記リードとを
導電物質を介して電気的に接続してなることを特徴とす
る半導体素子搭載用基板。
1. A substrate on which a wiring pattern for mounting a semiconductor element is formed and a lead are fixed by thermocompression bonding to be integrated with each other, and an electrode terminal of the substrate and the lead are electrically connected via a conductive substance. A semiconductor element mounting substrate characterized by being connected.
【請求項2】 半導体素子を搭載するための配線パター
ンを形成した基板の表面に熱接着層を設けるとともに前
記基板の電極端子が露出するようにこの部分の熱接着層
を除去して凹部を形成し、次にこの熱接着層の凹部に導
電物質を充填した後、前記基板とこの基板に固定するリ
ードとを熱圧着することを特徴とする半導体素子搭載用
基板の製造方法。
2. A thermal adhesive layer is provided on the surface of a substrate on which a wiring pattern for mounting a semiconductor element is formed, and the thermal adhesive layer is removed to form a recess so that the electrode terminals of the substrate are exposed. Then, after filling the concave portion of the thermal adhesive layer with a conductive material, the substrate and the leads to be fixed to the substrate are thermocompression bonded, and the method for manufacturing a semiconductor element mounting substrate.
【請求項3】 半導体素子を搭載するための配線パター
ンを形成した基板の表面に熱接着層を設け、その上に保
護フィルムを貼り合せるとともに前記基板の電極端子が
露出するようにこの部分の熱接着層及び保護フィルムを
除去して凹部を形成し、次にこの凹部に導電物質を充填
した後、前記保護フィルムを剥離し、前記基板とこの基
板に固定するリードとを位置合せして熱圧着することを
特徴とする半導体素子搭載用基板の製造方法。
3. A thermal adhesive layer is provided on the surface of a substrate on which a wiring pattern for mounting a semiconductor element is provided, and a protective film is attached on the thermal adhesive layer so that the electrode terminals of the substrate are exposed to heat. After removing the adhesive layer and the protective film to form a concave portion, and then filling the concave portion with a conductive material, the protective film is peeled off, and the substrate and the leads to be fixed to the substrate are aligned and thermocompression bonded. A method of manufacturing a substrate for mounting a semiconductor element, comprising:
【請求項4】 前記基板と熱圧着するリードの先端部分
に凹部又は凹凸部を形成したことを特徴とする請求項2
または3記載の半導体素子搭載用基板の製造方法。
4. A concave portion or a concave-convex portion is formed at a tip portion of a lead which is thermocompression-bonded to the substrate.
Alternatively, the method of manufacturing a semiconductor element mounting substrate according to the item 3 above.
JP12790093A 1993-04-30 1993-04-30 Semiconductor element mounting board and manufacture thereof Pending JPH06314750A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12790093A JPH06314750A (en) 1993-04-30 1993-04-30 Semiconductor element mounting board and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12790093A JPH06314750A (en) 1993-04-30 1993-04-30 Semiconductor element mounting board and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH06314750A true JPH06314750A (en) 1994-11-08

Family

ID=14971446

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12790093A Pending JPH06314750A (en) 1993-04-30 1993-04-30 Semiconductor element mounting board and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH06314750A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005283450A (en) * 2004-03-30 2005-10-13 Nagano Keiki Co Ltd Pressure sensor and its manufacturing method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005283450A (en) * 2004-03-30 2005-10-13 Nagano Keiki Co Ltd Pressure sensor and its manufacturing method
US7484417B2 (en) 2004-03-30 2009-02-03 Nagano Keiki Co., Ltd. Pressure sensor and manufacturing method of the same

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