JPH06314749A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH06314749A
JPH06314749A JP5102084A JP10208493A JPH06314749A JP H06314749 A JPH06314749 A JP H06314749A JP 5102084 A JP5102084 A JP 5102084A JP 10208493 A JP10208493 A JP 10208493A JP H06314749 A JPH06314749 A JP H06314749A
Authority
JP
Japan
Prior art keywords
chip
semiconductor chip
semiconductor device
semiconductor
mounting portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5102084A
Other languages
Japanese (ja)
Inventor
Motoharu Moriyama
基治 森山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP5102084A priority Critical patent/JPH06314749A/en
Publication of JPH06314749A publication Critical patent/JPH06314749A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

Abstract

PURPOSE:To obtain a semiconductor device which is small in dispersion of high frequency characteristics and wherein a semiconductor chip mounted on a chip mount is restrained from getting out of mounting position. CONSTITUTION:A chip mount 8, which is so protruding trapezoidal in cross section as to make its base angle equal to an angle of 45 deg. or below to the other part of a mount 2 and equal to a semiconductor chip 3 in width, is provided to the mount 2, and the semiconductor chip 3 is mounted on the chip mount 8 by soldering.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、高周波半導体装置に
関し、特に半導体チップをマウント部に取り付ける際の
位置ずれが少ない高周波半導体装置に関するものであ
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-frequency semiconductor device, and more particularly to a high-frequency semiconductor device which is less likely to be displaced when mounting a semiconductor chip on a mount portion.

【0002】[0002]

【従来の技術】図4は、従来のマイクロ波電力増幅器に
使用されている半導体装置の構成を示す斜視図である。
図において、101はパッケージ、103はマウント部
102に半田で取付けられているトランジスタにより構
成される半導体チップ、105はボンディングパッド、
104は半導体チップ103とボンディングパッド10
5を接続する金ワイヤ、106はボンディングパッド1
05と接続されているリードである。
2. Description of the Related Art FIG. 4 is a perspective view showing a structure of a semiconductor device used in a conventional microwave power amplifier.
In the figure, 101 is a package, 103 is a semiconductor chip composed of transistors mounted on the mount 102 by soldering, 105 is a bonding pad,
Reference numeral 104 denotes the semiconductor chip 103 and the bonding pad 10.
Gold wire connecting 5 and 106 bonding pad 1
05 is a lead connected to.

【0003】次に、組立方法について説明する。図4に
示すように、パッケージ101のマウント部102上の
所定の取り付け位置に、顕微鏡下で目視により手作業
で、半導体チップ103を半田により取り付けた後、半
導体チップ103とボンディングパット105をワイヤ
104で接続し、半導体装置を得る。
Next, the assembly method will be described. As shown in FIG. 4, the semiconductor chip 103 is manually attached by soldering to a predetermined attachment position on the mount portion 102 of the package 101 under a microscope, and then the semiconductor chip 103 and the bonding pad 105 are connected to the wire 104. To obtain a semiconductor device.

【0004】[0004]

【発明が解決しようとする課題】従来の半導体装置は以
上のように構成されているため、マウント部102上に
おける半導体チップ103の取り付け位置が規定しにく
く、取り付け位置のばらつきが発生しやすくなり、この
ばらつきに伴うワイヤ104の長さの変動の影響によ
り、半導体装置の高周波特性に大きなばらつきが生じる
という問題点があった。
Since the conventional semiconductor device is configured as described above, it is difficult to define the mounting position of the semiconductor chip 103 on the mount portion 102, and the mounting position tends to vary. Due to the influence of the variation in the length of the wire 104 due to this variation, there is a problem in that the high frequency characteristics of the semiconductor device greatly vary.

【0005】また、半導体チップ103をマウント部1
02上に取り付ける際に使用する半田が多すぎた場合、
半田によって、マウント部102に対するチップ103
の浮きが発生し、半導体チップ103の底面からの放熱
効率が悪くなるという問題点があった。
The semiconductor chip 103 is mounted on the mount unit 1.
If too much solder is used when mounting on 02,
By soldering, the chip 103 for the mount portion 102
However, there is a problem that the heat radiation efficiency from the bottom surface of the semiconductor chip 103 deteriorates.

【0006】この発明は上記のような問題点を解消する
ためになされたもので、半導体チップの取り付け位置を
安定させることにより、高周波特性のばらつきを抑えた
半導体装置を得ることを目的とする。
The present invention has been made to solve the above problems, and an object thereof is to obtain a semiconductor device in which variations in high frequency characteristics are suppressed by stabilizing the mounting position of the semiconductor chip.

【0007】また、この発明は、過剰な量の半田によっ
て発生するマウント部に対する半導体チップの浮きをな
くして、放熱効率に優れた半導体装置を得ることを目的
とする。
Another object of the present invention is to obtain a semiconductor device excellent in heat dissipation efficiency by eliminating the floating of the semiconductor chip with respect to the mount portion caused by an excessive amount of solder.

【0008】[0008]

【課題を解決するための手段】この発明に係る半導体装
置は、マウント部の半導体チップを取り付ける所定の領
域に、その断面形状が他の領域に対して底角が45°以
下の台形形状となるように隆起しており、かつ、その上
面の横幅が半導体チップの横幅と同程度となるように形
成されたチップ取付部を設け、これに半導体チップを半
田付けするようにしたものである。
A semiconductor device according to the present invention has a trapezoidal shape whose cross-sectional shape is 45 ° or less in a predetermined area where a semiconductor chip of a mount portion is mounted, with respect to other areas. As described above, the chip mounting portion is formed so that the lateral width of the upper surface thereof is approximately the same as the lateral width of the semiconductor chip, and the semiconductor chip is soldered thereto.

【0009】また、この発明に係る半導体装置は、マウ
ント部の半導体チップを取り付ける所定の領域に、その
両外側に設けられた所定の深さと幅を有する溝によって
他の領域と区別された,その上面の幅が上記半導体チッ
プの横幅と同程度のチップ取付部を設け、これに半導体
チップを半田付けするようにしたものである。
Further, the semiconductor device according to the present invention is distinguished from the other regions by the grooves having the predetermined depth and width provided on both outer sides of the predetermined region where the semiconductor chip of the mount portion is mounted. A chip mounting portion having a width of the upper surface that is approximately the same as the lateral width of the semiconductor chip is provided, and the semiconductor chip is soldered thereto.

【0010】[0010]

【作用】この発明においては、マウント部の半導体チッ
プを取り付ける所定の領域に、その断面形状が他の領域
に対して底角が45°以下の台形形状となるように隆起
しており、かつ、その上面の横幅が半導体チップの横幅
と同程度となるように形成されたチップ取付部を設け、
これに半導体チップを半田付けするようにしたから、チ
ップ取付部が目視しやすく、半導体チップを取り付ける
際の取り付け位置の確認が容易となるので、半導体チッ
プの取り付け位置のずれが少ない半導体装置を得ること
が可能となる。また、半導体チップを半田付けする際に
使用する半田が多すぎた場合でも、半田はチップ取付部
の外へ、斜面に沿って流れ出すため、半導体チップの浮
きが発生せず、放熱効率に優れた半導体装置を得ること
ができる。
According to the present invention, a predetermined area of the mount portion to which the semiconductor chip is attached is raised so that its sectional shape is a trapezoidal shape having a base angle of 45 ° or less with respect to other areas, and Provide a chip mounting portion formed so that the lateral width of its upper surface is approximately the same as the lateral width of the semiconductor chip,
Since the semiconductor chip is soldered to this, the chip mounting portion is easy to see and the mounting position when mounting the semiconductor chip can be easily confirmed, so that a semiconductor device with less displacement of the mounting position of the semiconductor chip is obtained. It becomes possible. Moreover, even if too much solder is used when soldering the semiconductor chip, the solder flows out of the chip mounting part along the slope, so that the semiconductor chip does not float and the heat dissipation efficiency is excellent. A semiconductor device can be obtained.

【0011】また、この発明においては、マウント部の
半導体チップを取り付ける所定の領域に、その両外側に
設けられた所定の深さと幅を有する溝によって他の領域
と区別された,その上面の幅が上記半導体チップの横幅
と同程度のチップ取付部を設け、これに半導体チップを
半田付けするようにしたから、この溝を目視の際の目印
として、半導体チップを取り付ける際の取り付け位置の
確認が容易にできるので、取り付け位置のずれが少ない
半導体装置を得ることが可能となる。また、半導体チッ
プをチップ取付部に半田付けする際に使用する半田が多
すぎた場合でも、半田はチップ取付部の周囲の溝へ流れ
出すため、チップの浮きが発生せず、放熱効率に優れた
半導体装置を得ることができる。
Further, according to the present invention, the width of the upper surface of the mounting portion, which is distinguished from the other areas by the grooves having the predetermined depth and width provided on both outer sides of the predetermined area for mounting the semiconductor chip. Is provided with a chip mounting portion having the same width as the semiconductor chip, and the semiconductor chip is soldered to this.Therefore, as a mark for visual inspection of this groove, it is possible to confirm the mounting position when mounting the semiconductor chip. Since it can be easily performed, it is possible to obtain a semiconductor device in which the mounting position is less displaced. Moreover, even if too much solder is used when soldering the semiconductor chip to the chip mounting part, the solder flows out into the groove around the chip mounting part, so the chip does not float and the heat dissipation efficiency is excellent. A semiconductor device can be obtained.

【0012】[0012]

【実施例】【Example】

実施例1.図1は本発明の第1の実施例による半導体装
置の構成を示す斜視図である。図において、1はパッケ
ージ、2はマウント部、3はトランジスタからなる半導
体チップ、8はマウント部2の、半導体チップ3を取り
付ける所定の位置に設けられたチップ取付部で、マウン
ト部2に対して底角が45°以下となるように台形形状
に隆起しており、かつチップ取付部8の幅は半導体チッ
プ3の幅と同等程度に形成されている。4は金ワイヤ、
5はボンディングパッド、6はリードである。
Example 1. 1 is a perspective view showing the configuration of a semiconductor device according to a first embodiment of the present invention. In the figure, 1 is a package, 2 is a mount portion, 3 is a semiconductor chip made of a transistor, 8 is a chip mounting portion provided at a predetermined position of the mounting portion 2 for mounting the semiconductor chip 3, and with respect to the mounting portion 2. It is raised in a trapezoidal shape so that the base angle is 45 ° or less, and the width of the chip mounting portion 8 is formed to be approximately the same as the width of the semiconductor chip 3. 4 is a gold wire,
Reference numeral 5 is a bonding pad, and 6 is a lead.

【0013】次に、製造工程について説明する。パッケ
ージ1のチップ取付部8上に半導体チップ3を半田で取
り付けた後、半導体チップ3とボンディングパット5を
ワイヤ4で接続し、半導体装置を得る。
Next, the manufacturing process will be described. After the semiconductor chip 3 is mounted on the chip mounting portion 8 of the package 1 by soldering, the semiconductor chip 3 and the bonding pad 5 are connected by the wire 4 to obtain a semiconductor device.

【0014】本実施例においては、半導体チップ3のチ
ップ取付部8への取り付けは、顕微鏡等を用いて目視に
より手作業で行われるが、チップ取付部8の幅は半導体
チップ3とほぼ同じ幅であり、マウント部2に対して隆
起しているように形成されているので、チップ取付位置
の視覚による認識が容易であり、また、半導体チップ3
の取付位置が所定の取り付け位置から大きくずれた場合
は、上記チップ取付部8からチップが落ちることによ
り、取り付け位置のずれが確認できるため、半導体チッ
プを取り付ける位置を一定にすることができる。
In the present embodiment, the semiconductor chip 3 is mounted on the chip mounting portion 8 by visual inspection using a microscope or the like, but the width of the chip mounting portion 8 is almost the same as that of the semiconductor chip 3. Since it is formed so as to be raised with respect to the mount portion 2, it is easy to visually recognize the chip mounting position, and the semiconductor chip 3
When the mounting position of 1 is largely deviated from the predetermined mounting position, the chip is dropped from the chip mounting portion 8 so that the displacement of the mounting position can be confirmed, so that the mounting position of the semiconductor chip can be made constant.

【0015】また、上記の製造工程において、半導体チ
ップ3をチップ取付部8に固着するための半田が多かっ
た場合でも、マウント部2と半導体チップ3の間から半
田が流れ出すので、半導体チップ3の浮きをなくすこと
ができる。
Further, in the manufacturing process described above, even when a large amount of solder is used to fix the semiconductor chip 3 to the chip mounting portion 8, the solder flows out from between the mount portion 2 and the semiconductor chip 3, so that the semiconductor chip 3 is The floating can be eliminated.

【0016】図2に半導体チップをマウント部に取りつ
けた時の半導体チップ底面からの熱放散状況を模式的に
示す。図において、50はマウント部52上のチップ取
付部54に取りつけられたチップ、51はチップ50の
底面のエッジ部、53はエッジ部51から放散される
熱、54はチップ50の底面である。図に示すように、
半導体チップエッジ部51からの熱は放射的に熱放散さ
れるため、効率的な熱放散を行うためには、チップエッ
ジ部51におけるマウント部52とチップ底面54のな
す角度は45°以下であることが必要となる。本実施例
においては、チップ取付部8はマウント部2に対して4
5°以下の角度で構成されているので、マウント部2の
熱抵抗が高くなることを防ぎ、該チップ取付部8を設け
たことによる半導体装置の特性劣化を防ぐことができ
る。
FIG. 2 schematically shows how the heat is dissipated from the bottom surface of the semiconductor chip when the semiconductor chip is mounted on the mount portion. In the figure, 50 is a chip attached to a chip mounting part 54 on a mount part 52, 51 is an edge part of the bottom surface of the chip 50, 53 is heat dissipated from the edge part 51, and 54 is a bottom surface of the chip 50. As shown in the figure,
The heat from the semiconductor chip edge portion 51 is radiatively dissipated. Therefore, in order to dissipate the heat efficiently, the angle formed between the mount portion 52 and the chip bottom surface 54 in the chip edge portion 51 is 45 ° or less. Will be required. In the present embodiment, the chip mounting portion 8 is 4 times larger than the mounting portion 2.
Since it is formed at an angle of 5 ° or less, it is possible to prevent the thermal resistance of the mount portion 2 from increasing and prevent the characteristic deterioration of the semiconductor device due to the provision of the chip mounting portion 8.

【0017】このように本実施例1においては、半導体
チップを取り付ける位置に、マウント部2に対して隆起
しており、その幅が半導体チップ3の幅と同等であるチ
ップ取付部8を設け、このチップ取付部8上に半導体チ
ップ3を半田付けするようにしたから、半導体チップ3
を取り付ける位置が目視しやすいので、半導体チップ3
を取り付ける際の取り付け位置の確認が容易となり、取
り付け位置のずれが少ない半導体装置を得ることがで
き、ワイヤ4の長さの変動の影響を小さくした、安定し
た高周波特性を備えた半導体装置が得られる。
As described above, in the first embodiment, the chip mounting portion 8 is provided at the position where the semiconductor chip is mounted so as to be raised with respect to the mount portion 2 and whose width is equal to that of the semiconductor chip 3. Since the semiconductor chip 3 is soldered onto the chip mounting portion 8, the semiconductor chip 3
Since the mounting position is easy to see, the semiconductor chip 3
It is possible to easily confirm the mounting position when mounting the semiconductor device, obtain a semiconductor device with less displacement of the mounting position, reduce the influence of the variation in the length of the wire 4, and obtain a semiconductor device having stable high frequency characteristics. To be

【0018】また、半導体チップ3を取り付ける際に使
用する半田が多すぎた場合は、半田はチップ取付部8の
外へ、斜面に沿って流れ出すため、チップ3の浮きがな
くなるので、半導体チップ3からマウント部2への放熱
効率の低下を防いだ半導体装置を得られる。
If too much solder is used to mount the semiconductor chip 3, the solder will flow out of the chip mounting portion 8 along the slope, and the chip 3 will not float. It is possible to obtain the semiconductor device in which the reduction of the heat radiation efficiency from the to the mount portion 2 is prevented.

【0019】実施例2.図3は本発明の第2の実施例に
よる半導体装置の構成を示す斜視図であり、図におい
て、図1と同一符号は、同一又は相当する部分を示し、
12はチップマウント部、9は半導体チップ3を取り付
ける所定の位置に設けられたチップ取付部、7は半導体
チップ取付部9の両外側に半導体チップ3の横幅と同程
度の横幅を保って設けられた溝である。ここで、半導体
装置の特性劣化を防ぐため、溝7の幅,及び深さは共
に、半導体チップ3に対するマウント部12の熱抵抗が
高くならないように設定する。
Example 2. FIG. 3 is a perspective view showing the configuration of a semiconductor device according to a second embodiment of the present invention. In the figure, the same reference numerals as those in FIG. 1 denote the same or corresponding parts,
Reference numeral 12 is a chip mounting portion, 9 is a chip mounting portion provided at a predetermined position for mounting the semiconductor chip 3, and 7 is provided on both outer sides of the semiconductor chip mounting portion 9 while maintaining a lateral width similar to that of the semiconductor chip 3. It is a groove. Here, in order to prevent the deterioration of the characteristics of the semiconductor device, both the width and the depth of the groove 7 are set so that the thermal resistance of the mount portion 12 with respect to the semiconductor chip 3 does not become high.

【0020】本実施例2においては、上記実施例1と同
様に、半導体チップ3の半導体チップ取付部9への取り
付けは、顕微鏡等を用いて、目視により手作業で行われ
るが、この取り付けの際に溝7を目印とすることによ
り、チップ取付部9の確認が容易になるため、半導体チ
ップ3を取り付ける時の位置決めを精度良く行うことが
できる。
In the second embodiment, as in the first embodiment, the semiconductor chip 3 is mounted on the semiconductor chip mounting portion 9 by a visual check using a microscope or the like. At this time, by using the groove 7 as a mark, the chip mounting portion 9 can be easily confirmed, so that the positioning when mounting the semiconductor chip 3 can be performed accurately.

【0021】また、半導体チップ取り付け部8に半導体
チップ3を取り付ける際に、チップ固着用の半田が多か
った場合でも半田が溝7に流れ出し、チップ3の浮きを
なくすことができる。
Further, when the semiconductor chip 3 is mounted on the semiconductor chip mounting portion 8, even if there is a lot of solder for fixing the chip, the solder flows out into the groove 7 and the floating of the chip 3 can be eliminated.

【0022】このように本実施例2においては、半導体
チップ3と同等の横幅を有し、その両外側に所定の幅及
び深さを有する溝7が設けられたチップ取付部9を、マ
ウント部2上の半導体チップ3を取り付ける所定の位置
に設け、この半導体チップ取付部9上に半導体チップ3
を取り付けるようにしたから、この溝7を目視の際の目
印とすることができ、半導体チップ3を取り付ける際の
取り付け位置の確認が容易となり、取り付け位置のずれ
が少ない半導体装置を得ることができ、ワイヤ4の長さ
の変動の影響を小さくした、安定した高周波特性を備え
た半導体装置が得られる。
As described above, in the second embodiment, the chip mounting portion 9 having the lateral width equivalent to that of the semiconductor chip 3 and the groove 7 having the predetermined width and depth is provided on both outer sides of the chip mounting portion 9. The semiconductor chip 3 on the semiconductor chip 3 is provided at a predetermined position for mounting the semiconductor chip 3 on the semiconductor chip mounting portion 9.
Since the groove 7 is attached, the groove 7 can be used as a mark for visual inspection, the attachment position can be easily confirmed when the semiconductor chip 3 is attached, and a semiconductor device with less displacement of the attachment position can be obtained. It is possible to obtain a semiconductor device having stable high frequency characteristics in which the influence of the variation in the length of the wire 4 is reduced.

【0023】また、半導体チップ3を半導体チップ取り
付け部9に取り付ける際に使用する半田が多すぎた場合
でも、半田はチップ取付部9の周囲の溝7へ流れ出すた
め、チップ3の浮きがなくなり、放熱効率に優れた半導
体装置を得ることができる。
Further, even if too much solder is used to attach the semiconductor chip 3 to the semiconductor chip mounting portion 9, since the solder flows out into the groove 7 around the chip mounting portion 9, the chip 3 is prevented from floating. A semiconductor device having excellent heat dissipation efficiency can be obtained.

【0024】[0024]

【発明の効果】以上のようにこの発明によれば、マウン
ト部の半導体チップを取り付ける所定の領域に、その断
面形状が他の領域に対して底角が45°以下の台形形状
となるように隆起しており、かつ、その上面の横幅が半
導体チップの横幅と同程度となるように形成されたチッ
プ取付部を設け、これに半導体チップを半田付けするよ
うにしたから、チップ取付部が目視しやすく、半導体チ
ップを取り付ける際の取り付け位置の確認が容易とな
り、取り付け位置のずれが少ない半導体装置を得ること
ができる効果がある。
As described above, according to the present invention, a predetermined area where a semiconductor chip of a mount portion is mounted has a trapezoidal cross section whose base angle is 45 ° or less with respect to other areas. Since the semiconductor chip is soldered to the chip mounting part that is raised and whose upper surface has a width that is approximately the same as the width of the semiconductor chip, the chip mounting part is visible. In addition, it is easy to confirm the mounting position when mounting the semiconductor chip, and it is possible to obtain a semiconductor device in which the mounting position is less displaced.

【0025】また、この発明によれば、マウント部の半
導体チップを取り付ける所定の領域に、その断面形状が
他の領域に対して底角が45°以下の台形形状となるよ
うに隆起しており、かつ、その上面の横幅が半導体チッ
プの横幅と同程度となるように形成されたチップ取付部
を設け、これに半導体チップを半田付けするようにした
から、半導体チップを取り付ける際に使用する半田が多
すぎた場合でも、半田はチップ取付部の外へ斜面に沿っ
て流れ出すので、半導体チップの浮きがなくなり、放熱
効率に優れた半導体装置を得ることができる効果があ
る。
Further, according to the present invention, in the predetermined region where the semiconductor chip of the mount portion is mounted, the protrusion is formed so that its cross-sectional shape is a trapezoidal shape having a base angle of 45 ° or less with respect to other regions. Moreover, since the chip mounting portion is formed so that the lateral width of the upper surface thereof is approximately the same as the lateral width of the semiconductor chip and the semiconductor chip is soldered to this, the solder used when mounting the semiconductor chip. Even if the amount is too large, the solder flows out of the chip mounting portion along the slope, so that the semiconductor chip is prevented from floating and a semiconductor device having excellent heat dissipation efficiency can be obtained.

【0026】また、この発明によれば、マウント部の半
導体チップを取り付ける所定の領域に、その両外側に設
けられた所定の深さと幅を有する溝によって他の領域と
区別された,その上面の幅が上記半導体チップの横幅と
同程度のチップ取付部を設け、これに半導体チップを半
田付けするようにしたから、この溝を目視の目印とする
ことで、半導体チップを取り付ける際の取り付け位置の
確認が容易となり、取り付け位置のずれが少ない半導体
装置を得ることができる効果がある。
Further, according to the present invention, in the predetermined region where the semiconductor chip of the mount portion is mounted, the upper surface of the upper region is distinguished from the other regions by the grooves provided on both outer sides thereof and having the predetermined depth and width. Since the width of the chip mounting portion is about the same as the width of the semiconductor chip and the semiconductor chip is soldered to the chip mounting portion, this groove is used as a visual mark, so that the mounting position when mounting the semiconductor chip There is an effect that the confirmation becomes easy and a semiconductor device in which the mounting position is less displaced can be obtained.

【0027】また、この発明によれば、マウント部の半
導体チップを取り付ける所定の領域に、その両外側に設
けられた所定の深さと幅を有する溝によって他の領域と
区別された,その上面の幅が上記半導体チップの横幅と
同程度のチップ取付部を設け、これに半導体チップを半
田付けするようにしたから、半導体チップを取付ける際
に使用する半田が多すぎた場合でも、半田はチップ取付
部の周囲の溝へ流れ出すので、半導体チップの浮きがな
くなり、放熱効率に優れた半導体装置を得ることができ
る効果がある。
Further, according to the present invention, in a predetermined region where the semiconductor chip of the mount portion is mounted, a groove having a predetermined depth and width provided on both outer sides of the mount region distinguishes it from other regions, and The width of the chip is about the same as the width of the semiconductor chip, and the semiconductor chip is soldered to the chip mounting part. Since it flows into the groove around the portion, the semiconductor chip is prevented from floating, and a semiconductor device having excellent heat dissipation efficiency can be obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例による半導体装置の構成
を示す斜視図である。
FIG. 1 is a perspective view showing a configuration of a semiconductor device according to a first embodiment of the present invention.

【図2】本発明の第1の実施例による半導体装置の熱放
散状況を示す模式図である。
FIG. 2 is a schematic diagram showing a heat dissipation state of the semiconductor device according to the first embodiment of the present invention.

【図3】本発明の第2の実施例による半導体装置の構成
を示す斜視図である。
FIG. 3 is a perspective view showing a configuration of a semiconductor device according to a second embodiment of the present invention.

【図4】従来の半導体装置の構成を示す斜視図である。FIG. 4 is a perspective view showing a configuration of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1 パッケージ 2 マウント部 3 トランジスタにより構成される半導体チップ 4 ワイヤ 5 ボンディングパッド 6 リード 7 溝 8 チップ取付部 9 チップ取付部 12 マウント部 50 半導体チップ 51 チップエッジ部 52 マウント部 53 熱放散 54 チップ底面 101 パッケージ 102 マウント部 103 トランジスタにより構成される半導体チップ 104 ワイヤ 105 ボンディングパッド 106 リード 1 Package 2 Mount Part 3 Semiconductor Chip Composed of Transistor 4 Wire 5 Bonding Pad 6 Lead 7 Groove 8 Chip Mount Part 9 Chip Mount Part 12 Mount Part 50 Semiconductor Chip 51 Chip Edge Part 52 Mount Part 53 Heat Dissipation 54 Chip Bottom 101 Package 102 mount portion 103 semiconductor chip composed of transistors 104 wire 105 bonding pad 106 lead

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 パッケージ内に設けられたマウント部の
所定領域に半導体チップを半田付けしてなる半導体装置
において、 上記マウント部には、他の領域からその断面形状が台形
形状となるように隆起した,その上面の横幅が上記半導
体チップの横幅と同程度のチップ取付部が形成され、 該チップ取付部に上記半導体チップを半田付けしたこと
を特徴とする半導体装置。
1. A semiconductor device in which a semiconductor chip is soldered to a predetermined region of a mount portion provided in a package, wherein the mount portion is raised from another region so as to have a trapezoidal cross section. A semiconductor device, in which a chip mounting portion whose upper surface has a lateral width substantially equal to the lateral width of the semiconductor chip, and the semiconductor chip is soldered to the chip mounting portion.
【請求項2】 請求項1記載の半導体装置において、 上記チップ取付部は、上記台形の底角が45°以下の角
度で隆起していることを特徴とする半導体装置。
2. The semiconductor device according to claim 1, wherein the chip mounting portion is raised at a base angle of the trapezoid of 45 ° or less.
【請求項3】 パッケージ内に設けられたマウント部の
所定領域に半導体チップを半田付けしてなる半導体装置
において、 上記マウント部には、その両外側に設けられた所定の深
さと幅を有する溝によって他の領域と区別された,その
上面の幅が上記半導体チップの横幅と同程度のチップ取
付部が形成され、 該チップ取付部に上記半導体チップを半田付けしたこと
を特徴とする半導体装置。
3. A semiconductor device in which a semiconductor chip is soldered to a predetermined region of a mount portion provided in a package, wherein the mount portion has grooves provided on both outer sides thereof and having a predetermined depth and width. A semiconductor device characterized in that a chip mounting portion whose upper surface width, which is distinguished from other regions by the same width as the lateral width of the semiconductor chip, is formed, and the semiconductor chip is soldered to the chip mounting portion.
JP5102084A 1993-04-28 1993-04-28 Semiconductor device Pending JPH06314749A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5102084A JPH06314749A (en) 1993-04-28 1993-04-28 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5102084A JPH06314749A (en) 1993-04-28 1993-04-28 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH06314749A true JPH06314749A (en) 1994-11-08

Family

ID=14317915

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5102084A Pending JPH06314749A (en) 1993-04-28 1993-04-28 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH06314749A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106842456A (en) * 2017-03-24 2017-06-13 宁波宇达光电股份有限公司 A kind of ready-package optical branching device
JP2021019149A (en) * 2019-07-23 2021-02-15 三菱電機株式会社 Semiconductor device
US11282809B2 (en) 2018-12-25 2022-03-22 Sumitomo Electric Device Innovations, Inc. Method of manufacturing electronic component and method of manufacturing semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106842456A (en) * 2017-03-24 2017-06-13 宁波宇达光电股份有限公司 A kind of ready-package optical branching device
US11282809B2 (en) 2018-12-25 2022-03-22 Sumitomo Electric Device Innovations, Inc. Method of manufacturing electronic component and method of manufacturing semiconductor device
JP2021019149A (en) * 2019-07-23 2021-02-15 三菱電機株式会社 Semiconductor device

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