JPH06310579A - Measuring method for semiconductor device - Google Patents

Abstract

PURPOSE:To accurately measure the ion resistance of a semiconductor device in the state of a wafer. CONSTITUTION:Three TEGs (Test Elevnt Group) are provided in the same arrangement as that of MOSFET elements on a wafer in which the MOSFET elements are formed and are made up of 9, 16 and 25 pieces of MOSFET cells, and a common gate electrode and a common source electrode are formed for every TEG. The MOSFET cells are divided into the groups of a cell (E) adjacent to four cells, cells (B, D, F, H) adjacent to three cells and cells (A, C, G, I) adjacent to two cells. The respective resistance values Ra, Rb, Rc are set up as an unknown number for the MOSFET cells belonging to each group. The ion resistance is measured for every TEG, and the unknown numbers Ra, Rb, Rc are calculated by using the measured values.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for measuring a semiconductor device in which a large number of cells are connected in parallel, and more particularly to a method for measuring the characteristics of the semiconductor device in a wafer state.

[0002]

2. Description of the Related Art Power semiconductor devices for controlling large voltages and large currents are widely used in drive circuits of various motors and switching regulators.

There is a demand for a large current to increase the capacity of the power semiconductor device, and as a method for realizing a large current, a method of improving the cell packing density by a fine processing technique is known. That is, by reducing the size of each cell and the distance between each cell, the number of cells formed in a unit area on the chip is increased to increase the current density,
Achieve a large current.

Below, M is used as an example of a power semiconductor device.
An OS type FET will be taken, and its structure and operation will be described with reference to the drawings. FIG. 4 is a diagram showing the structure of a general vertical structure MOS type FET, and FIG.
It is sectional drawing of ET. In FIG. 4 (b), the upper surface of the n ⁺ -type semiconductor substrate (drain region) 1, n ^- -type epitaxial layer 2 is formed, the n ^- selectively p-type body region in a surface portion of the type epitaxial layer 2 A large number of 3 are formed at predetermined intervals. Then, two n ⁺ type source regions 4 are formed on the surface portion in the p type body region 3 at predetermined intervals.

Here, in FIG. 4A, the p-type body region 3 is formed.
A view of the configuration of the n ⁺ type source region 4 from above is shown. The figure shows one p-type body region 3 formed on the surface portion of the n ⁻ -type epitaxial layer 2, which is
A unit cell that constitutes an S-type FET element. And p
An n ⁺ type source region 4 is formed on the surface of the type body region 3 so as to surround the central p type body region 3.

The above-mentioned MOS type FET is composed of a large number of MOS type Fs.
ET cells are formed in the same process to have the same structure, and they are connected in parallel. The array of MOS type FET cells is formed by an array in which each cell is formed at equal intervals in the vertical and horizontal directions, or an array in which each cell has six adjacent cells (staggered arrangement). .

Returning to FIG. 4 (b). n p-type body region 3 and the n ⁺ -type source region 4 is formed ^- the mold on the surface of the epitaxial layer 2, n ⁺ -type surface of the source region 4 and part n ⁺ -type source region between 4,4 A silicon oxide film 5 is formed except on the p-type body region 3. Then, on the upper surface of the p type body region 3 located between the n ⁺ type source region 4 and the n ⁻ type epitaxial layer 2 and on the n ⁻ type epitaxial layer 2, the upper surface of the silicon oxide film 5 is made of polysilicon. The gate electrode 6 is formed. The surface of the n ⁺ type source region 4 and p
A source electrode 8 made of aluminum is formed so as to be connected to a part of the surface of the mold body region 3. The source electrode 8 and the gate electrode 6 are electrically insulated by the PSG film 7. Further, the drain electrode 9 is uniformly formed on the lower surface of the n ⁺ type semiconductor substrate 1.

The turn-on of the MOS FET having the above structure is performed by applying a positive gate voltage of a predetermined value or more to the gate electrode 6. That is, by applying the gate voltage, the semiconductor region in the vicinity of the surface of the p-type body region 3 located below the gate electrode 6 is inverted in conductivity type from p-type to n-type, and via the n-channel formed by the inversion region. Thus, electrons are allowed to flow from the n ⁺ type source region 4 to the n ⁺ type semiconductor substrate 1.

On the other hand, at the time of turn-off, the application of the gate voltage is stopped and the n channel formed in the vicinity of the surface of the p type body region 3 is closed, so that the n ⁺ type source region 4 to the n ⁺ type semiconductor substrate 1 are closed. Block the inflow of electrons into.

Next, the characteristic measurement of the MOS type FET will be described. The MOS type FET shown in FIG. 4B is a stage where the wafer process is completed, and thereafter, a dicing process, a die bonding process, a wire bonding process, an airtight sealing process, and the like are performed to complete a semiconductor device. Therefore, generally, in the state where the wafer process is completed, a pass / fail judgment such as measuring the on-resistance of the MOS type FET is performed, and the process after the above dicing is not performed on the defective product, thereby eliminating waste. .

By the way, when measuring the on-resistance of a MOS FET in a wafer state, a large current cannot flow. The reason for this is that when performing the above-mentioned measurement, it is common to arrange the drain electrode 9 on a conductive stage so as to be in contact therewith, but a good ohmic connection is made between this stage and the drain electrode 9. This is because it is difficult to stably flow a large current with high precision.

Therefore, when it is desired to know the on-resistance of a MOS type FET in a wafer state, one MOS type F cell is provided separately from the n MOS type FET cells which form one chip.
An ET cell is provided as a test cell, a predetermined gate voltage is applied to the test cell to turn it on, and the on-resistance of one MOS FET cell is obtained from the current and voltage values at that time. Here, since each MOS type FET cell is finely formed in the same structure and in the same structure, the current flowing through each MOS type FET cell becomes equal. Therefore, M consisting of n MOS type FET cells
The ON resistance of the OS type FET element can be calculated as 1 / n of the ON resistance of one test cell.

[0013]

FIG. 5 shows the flow of carriers when measuring the on-resistance of one test MOS FET cell. In the figure, the area indicated by the number given to each part is the same as that in FIG.

[0014] From through the n-channel in the vicinity of the surface of the p-type body region 3 in the manner described above n ⁺ -type source region 4 n ⁺
When electrons flow into the n-type semiconductor substrate 1, the path through which the electrons pass through the n ⁻ -type epitaxial layer 2 is considerably wider than the region where the p-type body region 3 is formed, as shown by the arrow in FIG. Has spread to.

On the other hand, in the MOS type FET element consisting of n MOS type FET cells, the cells adjacent to each MOS type FET cell are also in the ON state,
As shown in FIG. 4B, the path through which electrons pass through the n ⁻ type epitaxial layer 2 is narrower than that shown in FIG. (Actually, even in a MOS type FET element composed of n MOS type FET cells, the path through which electrons flow is widened as shown in FIG. 5. However, since the MOS type FET cells are close to each other, any one A region where electrons flowing from a cell overlap with electrons flowing from a cell adjacent to the cell is formed, and the region between any one of the above cells and the region of a cell adjacent to the cell is defined with an intermediate position between the cells as a boundary. The number of electrons flowing to
Since it is considered that the number of electrons flowing from the area of the adjacent cell to the area of any one cell is the same, the path through which the electrons flow is substantially within the range shown in FIG. 4B. You can As described above, the range in which electrons pass through the n ⁻ type epitaxial layer 2, that is, the cross-sectional area type is one test MOS compared to the case of the MOS type FET element including n MOS type FET cells. Type F
Since it is larger in the case of ET cell, MOS type FE
One test MO rather than the on resistance of each cell of the T element
The on-resistance of the S-type FET cell is smaller. Generally, when MOS type FET cells are regularly arranged, the smaller the number of cells adjacent to a certain MOS type FET cell, the smaller the ON resistance of the cell.

Therefore, when the on-resistance of a MOS-type FET element composed of n MOS-type FET cells is to be obtained, the on-resistance of one test MOS-type FET cell is obtained by actual measurement, and the value is calculated for n minutes. When calculated as 1, the value becomes smaller than the actual on-resistance.

As described above, there is a problem that an accurate value cannot be obtained when measuring the on-resistance of a semiconductor device in a wafer state. The present invention solves the above problem, and an object thereof is to accurately measure the on-resistance of a semiconductor device in a wafer state.

[0018]

A method for measuring a semiconductor device according to the present invention is premised on a semiconductor device in which a plurality of cells are arranged and formed according to a predetermined rule and the plurality of cells are connected in parallel.

A plurality of TEGs (test / test) formed on the same wafer as the semiconductor device and having different numbers of cells, respectively.
Within the element group), a resistance value corresponding to the number of adjacent cells is set as an unknown number for each of the cells, and a simultaneous combination of the set resistance value and the on-resistance value measured for each TEG is established. The on-resistance value of the semiconductor device is obtained from the above-set resistance value obtained by solving the equation.

[0020]

When a plurality of cells are arranged according to a predetermined rule, the number of cells adjacent to a certain cell is determined by the position in the area where the plurality of cells are formed. For example, the number of cells adjacent to the cells formed at the end of the region is smaller than the number of cells adjacent to the cells formed inside the region.

When the resistance value for each cell is set as an unknown number according to the number of cells adjacent to the cell, simultaneous equations of the same number as the unknown number are required to obtain the unknown number. . Therefore, TEGs having different numbers of cells are provided by the same number as the unknown number, and the on-resistance of each TEG is actually measured to determine TE.
Establish an equation for each G.

The value obtained by solving the simultaneous equations is a resistance value set for each cell according to the number of adjacent cells, and the TEG and the semiconductor device are formed in the same array in the same step. Therefore, an accurate ON resistance value of the semiconductor device can be obtained from the solution of the simultaneous equations.

[0023]

Embodiments of the present invention will be described below with reference to the drawings. The present invention can be applied to a semiconductor device in which a large number of cells are connected in parallel. Here, the vertical structure MOS type FET shown in FIG. 4 will be described as an example.

FIG. 1 is a diagram for explaining the structure of a TEG (test element group) formed on the same wafer as the MOS type FET. In the figure,
Each square represents a MOS type FET cell, and is formed in the same structure as the cell forming the MOS type FET element in the same step. Also, the arrangement of cells in each TEG is MO
It is formed in the same manner as the array of cells forming the S-type FET element.

Each of the three TEGs shown in FIG.
It is composed of 3 = 9 cells, 4 × 4 = 16 cells, and 5 × 5 = 25 cells. Then, for each TEG, MO
S-type FET cells are connected in parallel. That is, each T
A common gate electrode 6 and source electrode 8 are formed for each EG. The reason for providing three types of TEGs will be described later.

Next, the definition of the number of cells adjacent to any one cell will be described with reference to the TEG composed of nine cells shown on the left side of FIG. Here, these nine MOS type FET cells are
Call them cells A to I.

The cell E located at the center of the TEG is adjacent to the cell B on the upper side, the cell H on the lower side, the cell D on the left side, and the cell F on the right side, which is adjacent to a total of 4 cells. It is defined as In this embodiment, cells A, C, G, and I
Is not counted as a cell adjacent to cell E.

Similarly, defining the number of adjacent cells for each cell, cells B, D, located on the sides of the TEG are defined.
F and H are adjacent to 3 cells, and cells A, C, G, and I located at the corners of the TEG are 2 respectively.
Defined as adjacent to a cell.

By the way, as described above, each MOS type F
Even when the ET cells are formed in the same structure in the same process, the on-resistance of the MOS type FET cell differs depending on the number of cells adjacent to the MOS type FET cell. Therefore, if the MOS-type FET cells are divided into groups according to the number of adjacent cells, the MOS-type FET cells belonging to each group have respective predetermined ON resistance values.

When this grouping is applied to the TEG consisting of the above 9 cells, the on resistance of the cell E adjacent to the 4 cells is _Ra , and the on resistances of the cells B, D, F, and H adjacent to the 3 cells are on. The resistance can be set to R _b , and the on-resistances of the cells A, C, G, and I adjacent to the two cells can be set to R _c . Thus, the MOS type FE as in this embodiment is
In the case of an array of T cells, the cells are divided into 3 groups,
Since three unknowns are set as the value of the ON resistance,
In order to obtain the unknown value, it is necessary to provide three TEGs each having a different number of cells.

Similarly, if the TEG comprising 16 cells shown in FIG. 1 is divided into groups, the number of MOS type FET cells having an on-resistance R _a is four,
The number of MOS type FET cells having the on-resistances R _b and R _c is 8 and 4, respectively. Further, 25 for the TEG composed of cells, the on-resistance R _a, the number of MOS-type FET cell having a R _b, and R _c each 9
12 pieces, 4 pieces.

On the other hand, each TEG is turned on, and each on resistance is measured from the current and voltage values at that time. This measured value is the TE of 9 cells, 16 cells, and 25 cells.
If G, R ₉ , R ₁₆ , and R ₂₅ , respectively, then the following simultaneous three-dimensional linear equations hold.

[0033]

[Equation 1]

In the above equations (1) to (3),
Since the values of R ₉ , R ₁₆ and R ₂₅ have been obtained by measurement, the on resistances R _a , R _b and R _c can be calculated.

By the way, generally, a vertical structure MOS type FET element used as a power semiconductor device is composed of a large number of MOS type FET cells. Therefore, the MOS-type FET that constitutes the above-mentioned MOS-type FET element
When the cells are divided into groups as described above, most of the cells are adjacent to the four cells and belong to the group having the on-resistance R _a . As an example, 100 × 100 = 100
MOS with 00 MOS-type FET cells connected in parallel
Considering the type FET element, there are 9604 cells having the on-resistance R _a . Therefore, MOS type FET
When the number of MOS type FET cells forming the element is n, the value obtained by dividing R _a obtained as the solution of the simultaneous equations by n is a very good approximate value to the ON resistance of the MOS type FET element.

If a more accurate value is desired,
It may be calculated in consideration of the on-resistances R _b and R _c . As an example, taking again a MOS type FET element composed of 100 × 100 = 10000 MOS type FET cells, 9604 cells have an on-resistance R _a , 392 cells have an on-resistance R _b, and 392 on-resistances R _{b. Since} there are four cells having _c , assuming that the ON resistance value of the MOS type FET element is R _ON , a very accurate ON resistance value can be obtained by calculating R _ON from the following equation (4). You can

[0037]

[Equation 2]

By using the TEG as described above, it becomes possible to calculate the accurate on-resistance of the MOS type FET element. These TEGs are a set of the above-mentioned three types of TEGs and are set on the wafer. A plurality of them are formed at predetermined positions. For example, TEGs are formed as a set for each of the above three types at a total of five locations near the upper and lower ends, right and left ends, and the center of the upper surface of the circular wafer, and the on-resistance is determined at each point. Alternatively, for each chip formed on the wafer, one set of TEG may be formed for each of the above three types and the measurement may be performed.

By the way, the shape of the TEG shown in FIG.
Each is a square having a cell array of 3 × 3, 4 × 4, and 5 × 5, but the present invention is not limited to this, and may be a rectangular TEG shown in FIG. 2, for example. In FIG. 2, the three TEGs are 3 × 3 = 9 and 4 × 3 =, respectively.
12 and 5 × 3 = 15 cells, and the measured on-resistance of each of these TEGs is R ₉ , R ₁₂ ,
And R ₁₅ , the following simultaneous equations hold.

[0040]

[Equation 3]

By solving the above equations (1), (5) and (6), the accurate on-resistance of the MOS type FET element can be calculated. Next, an example of a case where the cells forming the MOS type FET element are in a staggered arrangement will be described with reference to FIG.

The figure shows the arrangement of cells in the three TEGs. The arrangement of the MOS type FET cells in each TEG is the same as the arrangement of the cells forming the MOS type FET element. Has become. Here, as in the example shown in FIG. 1, the MOS-type FE depends on the number of cells adjacent to a certain cell.
When the T cells are divided into groups, they can be divided into three. That is, cells adjacent to 6 cells (indicated by diagonal lines to the upper right and designated as ON resistance R _a ′), cells adjacent to 4 cells (indicated by white squares and designated as ON resistance R _b ′), and 3 cells Adjacent cells (indicated by diagonal lines to the right and denoted by ON resistance R _c ′).

The procedure for obtaining the on-resistance of the MOS type FET element is the same as the method explained in FIG. In the example shown in FIG. 3, each T consisting of 7 cells, 19 cells, and 37 cells is used.
The on-resistances measured with respect to EG are R ₇ , R ₁₉ , and
And R ₃₇ , the following simultaneous equations hold.

[0044]

[Equation 4]

If the above equations (7) to (9) are solved, MO
MOS type F with S type FET cells arranged in a staggered arrangement
An accurate ON resistance of the ET element can be calculated. The example of the arrangement of the two types of MOS type FET cells has been described above. Generally, when a plurality of cells are arranged according to a predetermined rule, an accurate ON resistance of the MOS type FET element is calculated by using the same means. can do.

The shape of the MOS type FET cell is shown in FIG.
The structure is not limited to that shown in (a), and the donut-shaped n ⁺ -type source region 4 may be formed on the surface of the p-type gate region 3 formed in a circular shape, for example.

Further, in the above embodiment, the n-channel MOS type FET has been described as an example, but the present invention is also applicable to a p-channel MOS type FET. further,
The present invention is not limited to MOS type FETs, and is applicable to a semiconductor device in which a plurality of cells are arranged and formed according to a predetermined rule and the plurality of cells are connected in parallel. On-resistances of transistors, thyristors, IGBTs, etc. can be accurately measured in a wafer state.

[0048]

As described above, according to the present invention,
A plurality of TEGs each having a different number of cells are provided on the same wafer as the semiconductor device whose ON resistance is to be measured, and a resistance value corresponding to the number of cells adjacent to any one cell in each TEG is set for each cell. Since it is set as an unknown number and the on-resistance value of each cell is obtained by solving a simultaneous equation consisting of the set resistance value and the measured on-resistance value of each TEG, in the wafer state where a large current cannot flow. An accurate value can be obtained even when measuring the on-resistance.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a TEG according to an embodiment of the present invention, illustrating a cell array and the number of cells adjacent to any one cell in the cell array.

FIG. 2 is a diagram showing TEGs having an array similar to that of the TEGs shown in FIG. 1 and having different numbers of cells.

FIG. 3 is a diagram showing a TEG according to another embodiment of the present invention, in which cells are arranged in a staggered arrangement.

4A and 4B are diagrams illustrating a configuration of a general vertical structure MOS FET, in which FIG. 4A is a view of only a gate region and a source region of one cell as seen from above, and FIG. 4B is a sectional view.

FIG. 5 is a diagram illustrating a carrier flow when there is only one MOS type FET cell forming the MOS type FET shown in FIG.

Claims (3)

[Claims] 1. A method for measuring a semiconductor device in which a plurality of cells are arranged and formed according to a predetermined rule, and the plurality of cells are connected in parallel, wherein the number of cells each formed on the same wafer as the semiconductor device is measured. In a plurality of different TEGs, a resistance value corresponding to the number of adjacent cells is set as an unknown number for each cell, and the set resistance value and the on-resistance value measured for each TEG are included. A method for measuring a semiconductor device, wherein an on-resistance value of the semiconductor device is obtained from the set resistance value obtained by solving simultaneous equations. 2. A method of measuring a semiconductor device, wherein a plurality of cells are arranged at equal intervals in a vertical direction and a horizontal direction, and the plurality of cells are connected in parallel, which is formed on the same wafer as the semiconductor device. In the three types of TEGs each having a different number of cells, the on-resistance value of a cell having four adjacent cells is _Ra and the number of adjacent cells is three.
The on-resistance value of one cell is set as R _b , the on-resistance value of a cell having two adjacent cells is set as R _c, and the set resistance value and the on-resistance value measured for each TEG are set. A method for measuring a semiconductor device, wherein the on-resistance value of the semiconductor device is obtained from R _a , R _b , and R _c obtained as a solution of the simultaneous equations 3. A method for measuring a semiconductor device in which a plurality of cells are formed in a staggered arrangement and the plurality of cells are connected in parallel, wherein the number of the cells formed on the same wafer as the semiconductor device is different from each other. Within the TEG of the type, the on-resistance value of a cell having 6 adjacent cells is _Ra , and the adjacent cell is 4
The on-resistance value of one cell is set to R _b , the on-resistance value of a cell having three adjacent cells is set to R _c, and the set resistance value and the on-resistance value measured for each TEG are set. A method for measuring a semiconductor device, wherein the on-resistance value of the semiconductor device is obtained from R _a , R _b , and R _c obtained as a solution of the simultaneous equations