JP3885686B2 - Method for simulating characteristics of semiconductor device and method for manufacturing semiconductor device using the method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device characteristic simulation method and a semiconductor device manufacturing method using the method.
[0002]
[Prior art]
In recent years, in device structure design, software necessary for analyzing and designing a semiconductor device on a computer called TCAD (Technology Computer Aided Design) has been used to improve the efficiency of device structure design.
[0003]
FIG. 5A shows a plan view of a DMOS having a regular hexagonal structure having a general trench gate, and FIG. 5B shows a cross-sectional view taken along line AA ′ in FIG. FIGS. 6A and 6B show a conventional simulation model of the device having this structure.
[0004]
In this DMOS, when the surface of the semiconductor substrate is viewed from above, one mesh is a regular hexagonal mesh and a trench gate is formed. FIG. 5 shows one mesh portion, that is, one regular hexagon. A square shaped cell is shown.
[0005]
Specifically, this DMOS has n ⁺ N on the silicon substrate 1 ^- Type epitaxial layer 2 and p ⁺ A semiconductor substrate 4 on which a mold channel layer 3 is formed is provided. The surface layer of the semiconductor substrate 4 has p ⁺ N from the surface of the mold channel layer 3 ^- A trench 5 reaching the type epitaxial layer 2 is formed. In the trench 5, one mesh has a regular hexagonal shape, and the crystal plane orientation of the side wall surface of the trench 5 is a (310) plane or a (110) plane. A gate electrode 7 made of polysilicon is formed in the trench 5 via a gate oxide film 6, thereby forming a trench gate.
[0006]
A source region 8 is formed adjacent to the trench 5 in the surface layer of the region surrounded by the trench gate in the semiconductor substrate 4. A source electrode 9 is further formed thereon. A silicon oxide film 10 is formed on the gate electrode 7. N ⁺ Type silicon substrate 1, n ^- A drain electrode 11 is formed on the side opposite to the side where the type epitaxial layer 2 is formed.
[0007]
In the DMOS configured as described above, when a positive voltage is applied to the gate electrode 7, the pMOS ⁺ An inversion layer is formed in a region of the mold channel layer 3 facing the trench 5, and this region becomes a channel. As a result, the source regions 8 to N ^- A path to the type epitaxial layer 2 can be made, and a current can flow between the source electrode 9 and the drain electrode 11. In addition, since the side surface of the trench 5 is a channel surface, the hexagonal cell has two kinds of channels, a channel surface 12 whose crystal plane orientation is a (110) plane and a channel surface 13 whose (310) plane is a crystal plane. There is a channel plane.
[0008]
In the case of simulating the characteristics of a power device having such a structure, as shown in FIGS. 6A and 6B, the channel surface has the same structure as the cross-sectional view shown in FIG. 310) A two-dimensional model of a cross-sectional structure in a region which is a plane is used, and this two-dimensional model is approximated by a cylindrical model (cylindrical model) rotated about the Y axis.
[0009]
[Problems to be solved by the invention]
FIG. 7 shows the result of calculating the VG-ID characteristic using the cylindrical model and the waveform of the VG-ID characteristic of the actual device. A one-dot chain line in FIG. 7 is a result of approximation by a cylindrical model, and a solid line is an actual measurement value in an actual device. As shown in FIG. 7, the result approximated by the cylindrical model is different from the actually measured value. This is for the following reason. As described above, a cell having a regular hexagonal structure has two types of channel planes with a crystal plane orientation of (110) plane and (310) plane. Since the device characteristics are slightly different for each crystal plane orientation, it is necessary to consider the plane orientation in order to calculate the characteristics of the entire cell. However, in the cylindrical model, calculation is performed on the assumption that all the channel planes have one plane orientation. For this reason, calculation accuracy was not obtained.
[0010]
As described above, in a device having a polygonal cell structure having a plurality of channel planes having different crystal plane orientations, a highly accurate calculation result cannot be obtained when a characteristic simulation is performed using a cylindrical model.
[0011]
In the characteristic simulation of a power device having a polygonal cell as described above, a method of performing characteristic simulation using a three-dimensional model instead of using a cylindrical model is conceivable as a method for improving calculation accuracy. In this case, since the simulation can be performed in consideration of the plane orientation, a highly accurate calculation result can be obtained.
[0012]
However, since the structure of the three-dimensional model is complicated, the calculation time takes about six times as compared with the case where the calculation is performed using a two-dimensional model such as a cylindrical model.
[0013]
In view of the above, the present invention provides a method for simulating characteristics of a semiconductor device having a polygonal cell structure that has a high calculation accuracy and can be calculated in a shorter time than a three-dimensional model, and a method for manufacturing a semiconductor device using the method. The purpose is to do.
[0014]
[Means for Solving the Problems]
In order to achieve the above object, according to the first aspect of the present invention, in one polygonal cell, the channel region (25) in contact with the channel surface (12, 13) and the gate electrode (7) according to the surface orientation of the channel surface. ) Including two-dimensional models (26, 27) having a cross-sectional structure including the electrodes (7, 9, 11) in the two-dimensional models (26, 27) connected in parallel, The two-dimensional model (26, 27) is simulated with the depth as the gate width (14) in the channel plane of each plane orientation.
[0015]
Thus, since the two-dimensional model is formed for each crystal plane orientation of the channel plane, the performance corresponding to the crystal plane orientation of the channel plane can be set for those two-dimensional models. For example, when an oxide film formed by thermal oxidation is used as the gate insulating film, the film thickness of the oxide film in contact with the channel surface is set for each crystal plane orientation of the channel surface. In addition, the mobility of electrons and holes and the work function of the gate electrode are set for the two-dimensional model for each crystal plane orientation of the channel plane.
[0016]
In addition, since the depth of each two-dimensional structure model is the gate width in the channel plane, it is the same as the gate width in an actual polygon cell structure device.
[0017]
From these things, according to this invention, a highly accurate calculation result can be obtained. In addition, since the calculation is performed using the two-dimensional model, the calculation can be performed in a shorter time compared to the case where the simulation is performed using the three-dimensional model.
[0018]
Specifically, as shown in claim 2, when the semiconductor substrate is viewed from above, the two-dimensional model (26, 27) extends from the center of one polygon cell to the outer peripheral edge of the polygon cell, A cross-sectional structure in a direction perpendicular to the channel plane is modeled, and is formed on the first semiconductor layer (1) and the first semiconductor layer (1), and the first semiconductor layer (1). A first conductivity type second semiconductor layer (2) having a lower concentration, a second conductivity type channel layer (3) formed on the second semiconductor layer (2), and a channel layer (3 ) From the surface to the second semiconductor layer (2), a gate insulating film (6) formed on the inner wall of the groove (5), and a gate formed via the gate insulating film (6) A first conductivity type first layer formed on the surface of the electrode (7) and the channel layer (3) in contact with one side surface of the groove (5); The semiconductor region (8), the first electrode (11) electrically connected to the first semiconductor layer (1), the channel layer (3) and the third semiconductor region (8) electrically connected to the first electrode (11). It is a configuration having two electrodes (9), and simulation is performed by connecting the first electrodes (11), the second electrodes (9), and the gate electrodes (7) in parallel in each two-dimensional model. It can be used as a model to perform characteristic simulation.
[0019]
In the invention according to claim 3, the first electrode (11) and the second electrode (9) connected in parallel between the two-dimensional models (26, 27), respectively, An external resistor (23) and a second external resistor (24) are connected.
[0020]
As a result, the current value of the current flowing between the first electrode and the second electrode can be made quantitative, and a characteristic simulation can be performed with higher accuracy.
[0021]
According to a fourth aspect of the present invention, a semiconductor device having a polygonal cell structure includes a first conductivity type first semiconductor layer (31) and a first conductivity type formed on the first semiconductor layer (31). Of the second semiconductor layer (32), and the first and second semiconductor layers (31, 32) constitute a parasitic diode, and the second semiconductor layer (36, 37) of each two-dimensional model (36, 37). 32) is characterized in that a characteristic simulation is performed assuming that they have the same potential.
[0022]
In this way, if each second semiconductor layer (32) is set to the same potential, these potentials can be fixed. Therefore, among the cells used in the simulation model, a current flows in a certain cell. It is possible to prevent the result of current bias that cannot occur in an actual device such that no current flows through the cell.
[0023]
In the invention according to claim 5, the characteristic simulation is performed on the assumption that the second semiconductor layers (32) of the respective two-dimensional models (36, 37) are connected to each other via the first resistor (43). It is characterized by doing.
[0024]
As described above, when the second semiconductor layers are connected to each other through the first resistor when the second semiconductor layers are set to the same potential, the second semiconductor layers are arranged between the cells connected by the first resistor. Therefore, it is possible to anticipate the sheet resistance of the assumed cell, and to obtain higher versatility.
[0025]
In the invention described in claim 6, when the two-dimensional models are connected to each other, the second semiconductor layer (32) of the two-dimensional model located at the end has a resistance value equivalent to infinity. A characteristic simulation is performed on the assumption that the ground is made through the resistors (44, 45).
[0026]
By adopting such a configuration, it is possible to prevent the second semiconductor layers of all the cells from being in a floating state among the simulation cells on the simulation model. Further, at this time, it is considered that current flows from each second semiconductor layer toward the ground side, and variation of the current occurs. However, by assuming that the resistance value of the second resistor is equivalent to infinity, It can be set as a simulation that such a current does not flow.
[0027]
As shown in claim 7, the two-dimensional model (36, 37) includes a collector region (31) corresponding to the first semiconductor layer, a buffer layer (32) corresponding to the second semiconductor layer, and a second semiconductor layer. (32) formed on the third semiconductor layer (2) and the third semiconductor layer (2) of the first conductivity type formed at a lower concentration than the second semiconductor layer (32). A channel layer (3) of the second conductivity type and a gate insulating film (6) formed on the surface of the groove (5) formed by reaching the third semiconductor layer (2) from the surface of the channel layer (3) ) And the gate electrode (7) formed on the gate insulating film (6) and the first conductivity type formed in contact with one side surface of the groove (5) of the surface layer of the channel layer (3). An emitter region (33) and an emitter electrode (3 electrically connected to the channel layer (3) and the emitter region (33) ) And, as a structure having an electrically connected to a collector electrode on the first semiconductor layer (31) (35), it can be carried out simulating properties.
[0028]
Further, as shown in claim 8, device design is performed using a simulation result obtained by the semiconductor device characteristic simulation method according to claim 1, and a semiconductor element is formed based on the device design. can do.
[0029]
In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.
[0030]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
FIGS. 1A and 1B are diagrams for explaining a simulation model in the first embodiment in which the present invention is applied to an actual regular hexagonal cell structure. FIG. 2 shows a configuration diagram when a regular hexagonal cell is modeled. In the components of FIGS. 1 and 2, the same components as those in FIG. 5 are denoted by the same reference numerals.
[0031]
In this embodiment, a case where a characteristic simulation of a DMOS having the regular hexagonal cell structure described above is performed will be described as an example. An actual regular hexagonal cell includes two (110) plane channel surfaces 12 and four (310) plane channel surfaces 13. When the channel plane crystal planes are different, the device characteristics are different as described above. When the channel planes have the same plane orientation, the same device characteristics are exhibited.
[0032]
From this, in this embodiment, two types of models are formed in which the channel surfaces are the (110) plane and the (310) plane. Specifically, in the planar structure, a rectangular cell is taken out from one regular hexagonal cell as shown in FIG. 1, and as shown in FIG. , (110) plane and (310) plane are arranged as regular hexagonal cell models. At this time, since the regular hexagonal cell has six channel surfaces, a total of six rectangular cells are arranged. In this specification, when the cell is simply called, it means this rectangular cell.
[0033]
Here, the six rectangular cells will be described. In the present embodiment, as shown in FIG. 1A, in the planar structure, a rectangular region 21 surrounded by an alternate long and short dash line is used as one cell. In this region 21, the channel surface 12 is a (110) surface and has an AA ′ cross section. The AA ′ cross section is a cross section in the direction from the center of the regular hexagonal cell toward the gate electrode in a planar structure, and is a cross section in the direction perpendicular to the channel surface 12. This cross-sectional structure includes a channel region 25 in contact with the channel surface 12 that is the (110) plane and the gate electrode 7. This region 21 is a planar structure in which two sets of two sides facing each other have a length between AA ′, that is, the length from the center of one regular hexagonal cell to the outer peripheral edge of the regular hexagonal cell. The other sets have the same length as the gate width 14.
[0034]
Similarly, a region 22 having a channel surface 13 surrounded by an alternate long and two short dashes line and having a crystal plane of (310) plane is also a cell.
[0035]
Since the plane orientations of the channel planes existing in the regular hexagonal cell are two types (310) and (110), as shown in FIG. 2, in this embodiment, the planar structure is divided into channel planes having two types of plane orientations. Has arranged rectangular cells. Then, if the channel surface is, for example, the (110) plane, one rectangular cell has a rectangular parallelepiped shape that is the gate width in the channel surface 12 having the (110) plane with respect to the AA ′ cross section. Yes. Further, since one regular hexagonal cell has two (110) plane channel surfaces 12 and four (310) plane channel surfaces 13, in this embodiment, the channel plane is (110). Are continuously arranged, and four rectangular cells having a channel surface of (310) plane are continuously arranged.
[0036]
When the gate insulating film is composed of an oxide film formed by thermal oxidation, the thickness of the oxide film formed on the side wall of the trench 5 is set for each channel surface. This is because when the gate oxide film is formed by a thermal oxidation method, the growth rate of the oxide film differs depending on the surface orientation of the side surface of the trench 5, so that the oxide film thickness varies and the gate oxide film thickness varies. This is because the device characteristics are also considered different.
[0037]
Further, the device characteristics of the regular hexagonal cell are a combination of device characteristics when the regular hexagonal cell is divided for each crystal plane of the channel plane and the channel plane is the (110) plane portion and the (310) plane portion. Therefore, in this embodiment, the electrodes of the gate electrode 7, the source electrode 9, and the drain electrode 11 in the cell whose channel surface is the (110) surface and the cell whose channel surface is the (310) surface are connected in parallel. ing.
[0038]
In this embodiment, the model size is set based on the gate width of a regular hexagonal cell. That is, the depth of the rectangular cell in this embodiment is the same as the gate width 14 in each channel surface. For this reason, as can be seen from the cell 21 and the cell 22 in FIG. 1, the source electrodes 9 are overlapped in adjacent cells. Therefore, in such a configuration, the area of the source electrode 9 and the drain electrode 11 is larger than that of the regular hexagonal cell, and the current value flowing between the source electrode 9 and the drain electrode 11 becomes larger than the actual value.
[0039]
Therefore, in this embodiment, external resistors 23 and 24 are added to the source electrode 9 and the drain electrode 11 respectively. Thereby, the quantitative value can be given to the current value flowing between the source electrode 9 and the drain electrode 11. In the present embodiment, a regular hexagonal cell is approximated by assuming that it is composed of six rectangular cells.
[0040]
The configuration diagram shown in FIG. 2 shows the depth by a dotted line in order to explain the concept of the simulation model, but the regular hexagonal cell model used in the simulation is shown in FIG. The cross-sectional structure shown by the solid line inside is used as the two-dimensional models 26 and 27.
[0041]
That is, it is a cross section taken along the line AA ′ in FIG. 1A, in which the channel surface 13 is the (310) surface, and the cross-sectional structure 2 includes the channel region 25 and the gate electrode 7 in contact with the channel surface 13. A model obtained by connecting a two-dimensional model 26 and a two-dimensional model 27 in which the channel surface 12 is the (110) plane in parallel as shown in FIG. 2 is used as a regular hexagonal cell model. The reason why the two-dimensional model is used in this way is that, in a regular hexagonal cell, the on-current flows one-dimensionally from the top to the bottom, so that it can be calculated using the two-dimensional model.
[0042]
In general, when describing the cross-sectional structure of a vertical DMOS, a cross-sectional structure having a gate electrode and two channel regions formed on both sides thereof and having two current paths is defined as one cell. Explained. The two-dimensional model in the present embodiment is obtained by modeling a region that divides the cell into left and right halves and shows one current path, that is, a region corresponding to a so-called half cell.
[0043]
The device characteristics of the DMOS having a regular hexagonal cell structure are simulated using the two-dimensional model configured as described above. In the simulation, the depth is considered for the two-dimensional model as follows.
[0044]
The two-dimensional model is assumed to have a predetermined depth. When the depth of one two-dimensional model is set to 1 μm, for example, in order to show one rectangular cell, it is necessary to consider how many two-dimensional models exist. Furthermore, since the cells are arranged according to the plane orientation of the channel plane, the number of cells having the same plane orientation may be considered.
[0045]
Therefore, in this embodiment, the depth of two types of two-dimensional cross-sectional models whose channel planes are the (110) plane and the (310) plane is the product of the gate width 14 in the channel plane and the number of crystal planes. Consider in the simulation. In the present embodiment, the depth of one two-dimensional model is 1 μm. However, since this depth is arbitrarily set, other lengths may be used.
[0046]
In addition, since the mobility of electrons and holes and the work function of the gate electrode are different for each crystal plane orientation of the channel plane, two types of two-dimensional models 26 and 27 having a (110) plane and a (310) plane as the channel plane. For the (110) plane and (310) plane, the mobility of electrons and holes and the work function of the gate electrode are set.
[0047]
FIG. 3 shows the results when the VG-ID characteristics are calculated using the model in this embodiment. A dotted line in FIG. 3 is a calculation result when the model of the present embodiment is used, and a solid line is an actual measurement value. As shown in FIG. 3, the calculation result is equivalent to the actual measurement value, and it can be seen that the calculation result is higher than the calculation result when the cylindrical model shown in FIG. 7 is used. Note that the vertical and horizontal scales in FIG. 3 are the same as those in FIG. As can be seen from this result, it is possible to calculate with high accuracy by using the model of this embodiment. According to the present invention, device characteristics such as static characteristics and transient analysis can be simulated in addition to the VG-ID characteristics.
[0048]
As described above, in this embodiment, the models 26 and 27 having a two-dimensional cross-sectional structure are formed for each plane orientation of the channel surface. For this reason, when the gate insulating film is composed of a thermal oxide film for each of the two-dimensional cross-sectional structure models 26 and 27, the thickness of the oxide film can be set for each plane orientation. In addition, the mobility of electrons and holes and the work function of the gate electrode can be set for each plane orientation. Since the device orientation dependence of device characteristics is modeled in this way, a correct solution can be obtained in the characteristic simulation. Further, in the present embodiment, since it is formed using a two-dimensional model, it can be calculated in a shorter time compared to a calculation using a three-dimensional model having a complicated structure.
[0049]
And device design can be performed efficiently by performing device design using the simulation result obtained in this way. Thereafter, a semiconductor device is formed by forming a semiconductor element based on this device design.
[0050]
In this embodiment, the DMOS has been described as an example. ⁺ Type silicon substrate 1 (n ⁺ Type drain) is p ⁺ The present invention can also be applied to an IGBT in which a mold is replaced and a source is replaced by an emitter and a drain is replaced by a collector. Further, the structure of the two-dimensional model in the present embodiment corresponds to the structure of the two-dimensional model described in claim 2.
[0051]
(Second Embodiment)
FIG. 4 shows a configuration diagram when an IGBT having a regular hexagonal cell structure in the second embodiment to which the present invention is applied is modeled. In the present embodiment, n is different from the DMOS shown in FIG. ⁺ P on the lower side of the silicon substrate 1 ⁺ A case will be described in which an IGBT having a structure to which a mold layer is added and having a floating layer in a floating state is modeled.
[0052]
This IGBT model has a configuration in which rectangular cells are taken out for each plane orientation of the channel surface, rectangular cells are arranged for each plane orientation, and they are connected in parallel as in FIG. That is, the cell having the (110) plane channel surface 12 and the cell having the (310) plane channel surface 13 are connected in parallel. And for FIG. 2, n ⁺ N type silicon substrate 1 ⁺ Type buffer layer 32 and p ⁺ P composed of type silicon substrate ⁺ Replaced with a collector region 31 and n ⁺ N type source layer 8 ⁺ The configuration is replaced with the mold emitter region 33. And n ⁺ Type emitter region 33 and p ⁺ An emitter electrode 34 is formed so as to be electrically connected to the type channel layer 3, and p ⁺ A collector electrode 35 is formed so as to be electrically connected to the mold collector region 31.
[0053]
Also in the present embodiment, the cross-sectional structures 36 and 37 indicated by the solid line in FIG. 4 are used as a two-dimensional model during characteristic simulation.
[0054]
Here, in the case of the model shown in FIG. ⁺ Type collector region 31 and n ⁺ N of parasitic diodes formed by PN junction with the buffer layer 32 ⁺ The potential of the mold buffer layer 32 is in a floating state. For this reason, as in the first embodiment, if the electrodes of the two-dimensional model for each channel surface are simply connected in parallel, the calculation of accumulated calculation errors during simulation will cause the parasitic diode cathode and cell to be connected between the cells. N ⁺ A difference occurs in the potential of the mold buffer layer 32. This causes a forward characteristic of the diode expressed by the following equation, and the hole injection current increases exponentially.
[0055]
[Expression 1]
J = JS (eqV / KT ^-1 )
As a result, there arises a problem that the result is a current bias that cannot occur in an actual device such that a current flows in a cell but no current flows in a cell.
[0056]
Therefore, in the present embodiment, each n of each IGBT configured in this way. ⁺ The two sides of the mold buffer layer 32 are virtual electrodes 41a, 41b, 42a, 42b, and n of the two-dimensional model 36. ⁺ One virtual electrode 41b provided in the mold buffer layer 32 and n of the two-dimensional model 37 ⁺ The configuration is such that one virtual electrode 42 a provided in the mold buffer layer 32 is connected via a resistor 43. That is, the IGBT has p ⁺ Type collector region 31 and n ⁺ A parasitic diode is formed by a PN junction with the buffer layer 32, and each n of the parasitic diodes that is in a floating state in an actual device. ⁺ The type buffer layer 32 is connected via a resistor 43. This resistor 43 is connected to each n ⁺ This corresponds to the sheet resistance of the mold buffer layer 32. With such a configuration, each n ⁺ The type buffer layer 32 is fixed to have the same potential.
[0057]
At this time, the positions of the virtual electrodes 41a, 41b, 42a, 42b are n ⁺ Below the mold buffer layer 32, that is, n ⁺ P of the type buffer layer 32 ⁺ This is the mold collector region 31 side. This is n at reverse bias ⁺ Since the depletion layer is formed up to the upper part of the mold buffer layer 32, the position does not reach the depletion layer.
[0058]
N of the two-dimensional model 36 ⁺ The other virtual electrode 41 a provided in the mold buffer layer 32 is grounded via a resistor 44, and n of the two-dimensional model 37 ⁺ The other virtual electrode 42 b provided in the mold buffer layer 32 is grounded via a resistor 45. These resistors 44 and 45 have virtually infinite resistance values. Thereby, it can be made highly versatile.
[0059]
By adopting such a configuration of the IGBT model having a floating layer, current flows in a certain cell, but current does not flow in a cell at all. You can avoid it. This is the n of each cell used in the simulation model. ⁺ It is presumed that the increase of the hole injection current due to the forward characteristics of the diode due to the potential difference is eliminated because the buffer layers 32 are connected so as to have the same potential.
[0060]
Furthermore, in this embodiment, the virtual electrodes 41a and 42b provided in each cell whose channel surfaces are the (310) plane and the (110) plane are grounded via the resistors 44 and 45. As a result, all cells in the simulation model ⁺ The mold buffer layer 32 can be prevented from entering a floating state. At this time, each n ⁺ It is conceivable that a current flows from the buffer layer 32 toward the ground side, and that the amount of the current varies, but such a current does not flow by assuming that the resistance values of the resistors 44 and 45 are infinite. Such a simulation can be used.
[0061]
In the present embodiment, the structure having a floating layer in the IGBT has been described as an example. However, the present invention is not limited to the IGBT but may be applied to any device having a structure having a floating layer. An embodiment to which the inventions of claims 4, 5, and 6 are applied is this embodiment, and the structure of the two-dimensional model in this embodiment corresponds to the structure of the two-dimensional model described in claim 7.
[0062]
(Other embodiments)
In each of the above-described embodiments, the case of a regular hexagonal cell structure has been described as an example. However, the present invention can be applied to a hexagonal shape that is not a regular hexagon and is not a regular hexagon.
[0063]
The conventional cylindrical model approximates the planar structure of a polygonal cell to a circular shape. For this reason, a cylindrical model cannot be used in a structure that cannot be approximated by a circular shape, for example, when the planar structure of a polygonal cell is an elongated hexagonal shape.
[0064]
On the other hand, in this embodiment, a two-dimensional model of the number of types of surface orientations of the channel surface is formed, and adjustments such as setting the depth as the gate width in the channel surface are made for each two-dimensional model. Therefore, even when the planar structure of the polygonal cell is, for example, an elongated hexagonal shape, the characteristic simulation can be performed.
[0065]
In each of the above-described embodiments, the case of a regular hexagonal cell is taken as an example, so that the gate width 14 on the channel surface is the same regardless of the channel surface. Therefore, the depth of the two-dimensional model is the product of the gate width of each channel face and the number of channel faces that are the same crystal face.
[0066]
On the other hand, when the gate width in the channel plane is different between the channel planes having the same crystal plane, the total length of the gate width in the channel plane in the same crystal plane orientation is expressed by the two-dimensional model. The characteristic simulation is performed as the depth. In this way, the gate width in the simulation model and the actual device is made the same.
[0067]
Further, the present invention can be applied not only to a hexagonal shape but also to other polygonal shaped cells. Further, if the cell structure has a polygonal shape, the present invention can be applied to a concave-shaped gate electrode instead of the trench shape regardless of the plane orientation of the channel surface. The trench 5 and the concave correspond to the grooves described in the claims.
[0068]
In each of the above-described embodiments, an N-channel type device in which the first conductivity type is n-type and the second conductivity type is p-type has been described as an example. However, the first conductivity type is p-type and the second conductivity type is an example. The present invention can also be applied to a P-channel type device in which the type is n-type and the conductivity type is the opposite of the above embodiments.
[Brief description of the drawings]
1A and 1B are diagrams for explaining a simulation model in a first embodiment to which the present invention is applied, in which FIG. 1A is a plan view, and FIG. 1B is a cross-sectional view along AA ′ in FIG.
FIG. 2 is a diagram showing a simulation model in the first embodiment to which the present invention is applied.
FIG. 3 is a diagram showing a result of examining VG-ID characteristics of a DMOS having a regular hexagonal cell structure using the simulation model shown in FIG. 2;
FIG. 4 is a diagram showing a simulation model in a second embodiment to which the present invention is applied.
5A and 5B are diagrams showing the structure of a regular hexagonal cell in which one mesh has a regular hexagonal shape, where FIG. 5A is a plan view and FIG. 5B is a cross-sectional view taken along line AA ′ in FIG. .
FIG. 6 is a diagram showing a cylindrical model that is conventionally used when simulating device characteristics of polygonal cells.
7 is a diagram showing a result of examining a VG-ID characteristic of a DMOS having a regular hexagonal cell structure using the cylindrical model shown in FIG. 6; FIG.
[Explanation of symbols]
1 ... n ⁺ Type silicon substrate, 2 ... n ^- Type epitaxial layer, 3 ... p ⁺ Type channel layer, 4 ... semiconductor substrate, 5 ... trench, 6 ... gate oxide film, 7 ... gate electrode, 8 ... n ⁺ Type source region, 9 ... source electrode, 10 ... oxide film, 11 ... drain electrode, 12 ... channel surface with crystal plane orientation of (110) plane, 13 ... channel plane with crystal plane orientation of (310) plane, 14 ... Gate width on channel surface, 21, 22 ... rectangular cell, 23, 24 ... external resistance, 25 ... channel region, 26, 27, 36, 37 ... two-dimensional cross-sectional structure model, 31 ... p ⁺ Type collector region, 32... N ⁺ Type buffer layer, 33... N ⁺ Type emitter region 34... Emitter electrode 35. Collector electrode 41 a, 41 b, 42 a, 42 b. Virtual electrode 43, 44, 45.

Claims (8)

In the method for simulating the characteristics of a semiconductor device having a polygonal cell structure in which the trench gate is a planar structure and one mesh is formed in a polygonal mesh shape,
A two-dimensional model (26, 27) of a cross-sectional structure including a channel region (25) in contact with one channel surface (12, 13) and a gate electrode (7) for each plane orientation of the channel surface in one polygonal cell Are used as a simulation model, and the depth of each of the two-dimensional models (26, 27) is determined by using the parallel connection of the electrodes (7, 9, 11) in each of the two-dimensional models (26, 27). A method for simulating the characteristics of a semiconductor device, wherein the simulation is performed with the same length as the gate width (14) in the channel plane in each of the plane orientations. The two-dimensional model (26, 27) is a cross section in a direction perpendicular to the channel plane, which is from the center of one polygon cell to the outer peripheral edge of the polygon cell when the semiconductor substrate is viewed from above. The two-dimensional model is a model of the structure of
A first conductivity type first semiconductor layer (1);
A second semiconductor layer (2) of a first conductivity type formed on the first semiconductor layer (1) and having a lower concentration than the first semiconductor layer (1);
A second conductivity type channel layer (3) formed on the second semiconductor layer (2);
A gate insulating film (6) formed on an inner wall of a groove (5) formed from the surface of the channel layer (3) to the second semiconductor layer (2), and the gate insulating film (6); A gate electrode (7) formed through
A surface layer of the channel layer (3), a third semiconductor region (8) of the first conductivity type formed in contact with one side surface of the groove (5);
A first electrode (11) electrically connected to the first semiconductor layer (1);
A second electrode (9) electrically connected to the channel layer (3) and the third semiconductor region (8);
2. The method for simulating the characteristics of a semiconductor device according to claim 1, wherein the first electrodes and the second electrodes in each of the two-dimensional models are connected in parallel. For the first electrode (11) and the second electrode (9) connected in parallel between the two-dimensional models (26, 27), a first external resistor (23), 3. The semiconductor device characteristic simulation method according to claim 2, wherein a second external resistor (24) is connected. The semiconductor device having the polygonal cell structure includes a second conductive type first semiconductor layer (31) and a first conductive type second semiconductor layer (32) formed on the first semiconductor layer (31). ), And the first and second semiconductor layers (31, 32) form a parasitic diode,
2. The characteristic simulation method for a semiconductor device according to claim 1, wherein the characteristic simulation is performed on the assumption that the second semiconductor layers (32) of the two-dimensional models (36, 37) have the same potential. The characteristic simulation is performed on the assumption that the second semiconductor layers (32) of the two-dimensional models (36, 37) are connected to each other via a first resistor (43). Item 5. A semiconductor device characteristic simulation method according to Item 4. When the two-dimensional models are connected to each other, the second resistors (44, 45) in which the second semiconductor layer (32) of the two-dimensional model located at the end has a resistance value equivalent to infinity. 6. The characteristic simulation method for a semiconductor device according to claim 4, wherein characteristic simulation is performed assuming that the semiconductor device is grounded through the semiconductor device. The two-dimensional model (36, 37)
A collector region (31) corresponding to the first semiconductor layer;
A buffer layer (32) corresponding to the second semiconductor layer;
A third semiconductor layer (2) of the first conductivity type formed on the second semiconductor layer (32) and having a lower concentration than the second semiconductor layer (32);
A second conductivity type channel layer (3) formed on the third semiconductor layer (2);
A gate insulating film (6) formed on the surface of the groove (5) formed to reach the third semiconductor layer (2) from the surface of the channel layer (3), and the gate insulating film (6) A gate electrode (7) formed thereon;
A first conductivity type emitter region (33) formed in contact with one side surface of the groove (5) of the surface layer of the channel layer (3);
An emitter electrode (34) electrically connected to the channel layer (3) and the emitter region (33);
The semiconductor device characteristic simulation method according to claim 6, further comprising a collector electrode (35) electrically connected to the first semiconductor layer (31). A device design is performed using a simulation result of the semiconductor device characteristic simulation method according to claim 1, and a semiconductor element is formed based on the device design. Production method.

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