JPH06303542A - Video signal processor - Google Patents

Abstract

PURPOSE:To obtain a video signal processor capable of generating a character video signal with small amount of turbulence in display. CONSTITUTION:This processor is equipped with a vertical address counter 5, a false horizontal synchronizing signal generation circuit 103 which generates a false horizontal synchronizing signal E' at the reference frequency of a horizontal synchronizing signal setting a vertical synchronizing signal D as reference, and a switching circuit 104 which sets either a horizontal synchronizing signal E or the false horizontal synchronizing signal E' as the clock CLK of the vertical address counter 5 selectively. Thereby, the false horizontal synchronizing signal E' is selected as the clock CLK in a state where the horizontal synchronizing signal E is set in an unstable state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing device, and more particularly to a video signal processing device such as a so-called television, VTR, laser disk or the like.

[0002]

2. Description of the Related Art FIG. 2 shows a block diagram of a conventional VTR (video tape recorder). This comprises a character video signal generation circuit 10 in addition to the processing circuit for the original video signal A. The character video signal generation circuit 10 receives the vertical synchronization signal D separated from the original video signal A by the synchronization separation circuit 1 as a timing signal. Further, the horizontal synchronizing signal C separated in the same manner and the horizontal synchronizing signal E which is subjected to automatic frequency control by the AFC circuit 2 are also received as a timing signal.
Then, the character video signal H is generated at a timing corresponding to the vertical synchronizing signal D and the horizontal synchronizing signal E.

More specifically, the vertical address counter 5 is
In order to generate the vertical address G indicating the vertical position of the screen display, the vertical synchronization signal D is reset and the horizontal synchronization signal E is counted.
Output as. The horizontal address counter 4 is reset by the horizontal synchronizing signal E to generate the horizontal address F indicating the horizontal scanning position of the screen display, counts the dot clock from the dot clock generating circuit 3, and sets this count value as the horizontal address F. Output. The vertical address G is the upper bit of the read address of the display data RAM 7, and the horizontal address F is the lower bit of the read address of the display data RAM 7.

The reading & converting circuit 6 reads data from the corresponding address of the display data RAM 7 which stores the code data of the character displayed by the character video signal H,
On the other hand, processing such as character pattern conversion processing and parallel / serial conversion processing is performed. In this way, the character video signal H is generated. The synthesizing circuit 8 synthesizes the character video signal H and the analog video signal B to generate a video signal I. When the video signal I obtained in this way is displayed on the screen, a character image such as various kinds of guidance information, device status, error message, etc. is also displayed by being superimposed on the analog image.

[0005]

In such a conventional video signal processing device, a vertical address and a horizontal address for generating a character video signal are generated on the basis of the vertical synchronizing signal and the horizontal synchronizing signal. Therefore, in order to generate a stable character image signal for display, it is necessary that these sync signals are stable. However, while the vertical synchronizing signal obtained by the integrating circuit is relatively stable, the horizontal synchronizing signal obtained by the differentiating circuit is in an unstable state such as a missing pulse or fluctuating period. It is easy to become. Therefore, the horizontal synchronizing signal is rarely used as it is, and is usually used after automatic frequency control is performed by an AFC circuit to perform a stabilizing process such as supplementation of a missing pulse or correction of a period.

However, even if an expensive AFC circuit of PLL system or synthesizer system is used, perfect processing cannot always be expected. In particular, in the case of a VTR search, special reproduction such as stills, or reception of a television broadcast in a poor environment under a weak electric field, it is difficult to stabilize the horizontal synchronizing signal even by the AFC circuit. . If the horizontal synchronizing signal is disturbed, the screen display is disturbed, which is inconvenient. In particular, the display of a digital / binary character image compared to the display of an analog image is a problem because even a slight disturbance gives a great discomfort to the viewer. SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems of the prior art, and to realize a video signal processing device capable of generating a character video signal with little display disturbance.

[0007]

In order to achieve this object, a video signal processing device according to the present invention has a structure in which a vertical address indicating a display position in the vertical direction and a horizontal address indicating a display position in the horizontal direction are displayed for a display character. In a video signal processing device that generates a character video signal in accordance with these addresses and is reset by a vertical synchronizing signal, counts a clock, outputs a count value as the vertical address, and a horizontal synchronizing signal. Reset by the horizontal address counter that counts the dot clock of the oscillation signal that is synchronized with this horizontal synchronizing signal and outputs the count value as the horizontal address, and the standard of the horizontal synchronizing signal based on the timing when the vertical synchronizing signal is received. Generate a pulse at a frequency and simulate this generated pulse A pseudo horizontal synchronizing signal generating circuit for outputting as a flat synchronizing signal, and outputs one of the horizontal synchronizing signal and the pseudo horizontal synchronizing signal to the vertical address counter as a clock of the vertical address counter according to the received selection signal. A switching circuit, and is an operating state of the device under the condition that the horizontal synchronizing signal is detected to be in an unstable state such as a pulse missing state or the horizontal synchronizing signal is likely to be unstable. Correspondingly, the selection signal is for selecting the pseudo horizontal synchronization signal.

[0008]

In the video signal processing device of the present invention having such a configuration, the pseudo horizontal synchronizing signal is used as the clock of the vertical address counter instead of the horizontal synchronizing signal in response to the unstable state of the horizontal synchronizing signal. As a result, even if the horizontal synchronizing signal becomes unstable and a pulse fluctuates drastically, the fluctuation affects only the horizontal address and does not extend to the vertical address. Therefore, at least with respect to the vertical position of the character display, display disturbance due to fluctuation of the horizontal synchronizing signal is prevented. Therefore, the video signal processing device of the present invention can generate a character video signal with little display disturbance even under severe operating conditions such that the horizontal synchronizing signal becomes unstable.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 1 shows a VTR as an example.
The block diagram of is shown. Character video signal generation circuit 10
0 is shown as the center. Character video signal generation circuit 10
0 is common to the conventional character video signal generating circuit 10 in that it has a vertical address counter 5 for generating a vertical address G and the like to generate a character video signal H, but in addition to that, a pseudo horizontal synchronizing signal is also provided. It differs from the conventional character video signal generation circuit 10 in that it also has a counter circuit 103 as a generation circuit and a switching circuit 104. Hereinafter, these differences will be mainly described.

The counter circuit 103 is mainly composed of a 445-ary counter, generates a pulse at a timing according to the reset of the counter, and outputs this pulse to the switching circuit 104 as a pseudo horizontal synchronizing signal E '. The 445-ary counter counts an oscillation signal of about 7 MHz and resets itself when it reaches 445. This allows
The pulse E'is output at about 15.7 KHz which is the standard frequency of the horizontal synchronizing signal. The 445-ary counter is also reset by the vertical synchronizing signal D. This allows
The pulse E'is generated at the timing based on the vertical synchronizing signal D.

Therefore, the counter circuit 103 can generate a pulse at the standard frequency (about 15.7 KHz) of the horizontal synchronizing signal with reference to the timing of receiving the vertical synchronizing signal D. The 7 MHz oscillation signal is obtained by diverting the output signal of the oscillation circuit 102 for processing the subcarrier of the color signal in order to suppress an increase in the circuit scale, and the oscillation signal frequency is originally 7 MHz. It is not limited. In short, it suffices if the frequency is constant and stable and is sufficiently higher than the standard frequency of the horizontal synchronizing signal. However, in that case, the base number of the counter in the counter circuit 103 is not 445, but a base number of another value corresponding thereto. Specifically, the product of the standard frequency of the horizontal synchronizing signal and the decimal number of the counter may match the frequency of the oscillation signal.

The switching circuit 104 is a NAND circuit which is equivalent to a switch for selectively switching and outputting two inputs.
It is composed of a logic circuit such as a gate. When the selection signal J has the logical value "0", the logical value of the horizontal synchronizing signal E is input, and a signal of the same logical value level is output to the vertical address counter 5 as the clock CLK of the vertical address counter 5. When the selection signal J has the logical value “1”, the logical value of the pseudo horizontal synchronizing signal E ′ is input, and the signal of the same logical value level is output to the vertical address counter 5 as the clock CLK of the vertical address counter 5. . As a result, either the horizontal synchronizing signal E or the pseudo horizontal synchronizing signal E ′ is output to the vertical address counter 5 as the clock CLK of the vertical address counter 5 according to the selection signal J.

Here, the selection signal J is output from the MPU 101, which is a microprocessor for monitoring and controlling the operation of the entire VTR. this is,
By the program processing, the operating state of the device according to the viewer's operation is grasped. Therefore, it is known in advance that the horizontal synchronizing signal E obtained by reproduction or the like tends to be stable when the operating state of the VTR is a normal state such as a normal reproduction mode. The value "0" is output. That is, the selection signal J selects the horizontal synchronizing signal E. On the other hand, when the operation state of the VTR is in the special reproduction mode such as search or still, that is, the special state, it is known in advance that the horizontal synchronizing signal obtained by the reproduction is easily destabilized. Then, a logical value "1" is output as the selection signal J. That is, the selection signal J selects the pseudo horizontal synchronizing signal E '.

In response to this selection signal J, the switching circuit 104 causes the clock CLK of the vertical address counter 5 as described above.
Therefore, in the operating state of the device under the condition that the horizontal synchronizing signal E is easily stabilized, the vertical address G is initialized by the vertical synchronizing signal D and thereafter updated with the actual frequency of the horizontal synchronizing signal E. Further, in the operating state of the device under the condition that the horizontal synchronizing signal E easily becomes unstable, the vertical address G is also initialized by the vertical synchronizing signal D, but thereafter it is updated at the standard frequency of the horizontal synchronizing signal.

The operation under such a configuration will be described.
First, when the VTR is in the normal reproduction mode, the vertical address G is updated according to the actual horizontal synchronizing signal E, so that the operation is the same as that of the conventional circuit. That is, the vertical address counter 5 is reset by the vertical synchronizing signal D to count the horizontal synchronizing signal E to generate the vertical address G, and the horizontal address counter 4
Is reset by the horizontal synchronizing signal E to count the dot clocks to generate a horizontal address F. From the vertical address G and the horizontal address F, the display data RAM 7
Read addresses are configured. And the display data R
Character code data is read from the corresponding address of AM7, and a character video signal H is generated.

In this state, the horizontal synchronizing signal E is relatively stable, and there are almost no missing pulses in the horizontal synchronizing signal E. Therefore, the vertical address G updated by counting the horizontal synchronizing signal E indicates an accurate vertical position. However, the horizontal synchronizing signal E has a slight frequency variation. In rare cases, the fluctuation of the horizontal synchronizing signal may exceed the blanking period in horizontal scanning. In such a case, if the vertical address is updated at a fixed cycle regardless of the horizontal synchronizing signal E, the vertical address is updated during the horizontal scanning display, and the display is changed due to an undesired change in the vertical position. It may be disturbed vertically. On the other hand, in the circuit of this embodiment, since the vertical address G is generated by counting the actual horizontal synchronizing signal E, the update of the vertical address G is limited to the horizontal blanking period. Thereby, the above-mentioned inconvenience can be prevented.

Next, when the VTR is in the special reproduction mode, the vertical address G is updated at the standard frequency of the horizontal synchronizing signal unlike the conventional case. That is, the vertical address counter 5 is reset by the vertical synchronizing signal D and counts the pseudo horizontal synchronizing signal E ′ to generate the vertical address G. The horizontal address counter 4 is reset by the horizontal synchronizing signal E and counts the dot clock. Then, a horizontal address F is generated, and the vertical address G and the horizontal address F form a read address of the display data RAM 7. Then, the character code data is read from the corresponding address of the display data RAM 7 and the character video signal H is generated.

In this state, the horizontal synchronizing signal E is likely to be in an unstable state, and even the horizontal synchronizing signal E after the automatic frequency control often lacks a pulse. Therefore, if the vertical address is updated by the horizontal synchronizing signal E, the vertical address is insufficiently updated due to the missing pulse. Then, the vertical position of the character display fluctuates by that amount, and the display is disturbed in the vertical direction. On the other hand, in the circuit of this embodiment, since the vertical address G is generated by counting the pseudo horizontal synchronizing signal E ′ having a fixed cycle, the update of the vertical address G is not affected by the pulse loss of the horizontal synchronizing signal E. .

However, in this state, as described above, undesired disturbance in the vertical direction of the display may occur due to the update of the vertical address during the horizontal scanning display. However, this turbulence has the characteristic that it tends to concentrate on the edge of the screen. On the other hand, the undesired disturbance of the display in the vertical direction due to the lack of a pulse of the horizontal synchronizing signal has a characteristic that the influence thereof affects the entire screen. Therefore, the degree of display disorder based on these characteristics is weighed and compared, and in this case, the horizontal synchronizing signal E is likely to be in an unstable state. In this case, the vertical address G that is not affected by the missing pulse is updated. The method was selected.

Thus, even when the horizontal synchronizing signal tends to be unstable and unstable, the vertical disturbance of the character display can be reduced. When the character video signal H thus generated is displayed on the screen together with the analog video signal B, the character video such as various guide information is also displayed by being superimposed on the analog video. The display state of the character is not disturbed when the horizontal synchronizing signal is stable, and is less disturbed when the horizontal synchronizing signal is unstable.

Although the VTR has been described above as an example, the present invention can be applied to a television, a laser disk device, and the like. In short, as long as it is a device that generates a character video signal according to a vertical synchronizing signal or a horizontal synchronizing signal, the present invention can be applied in substantially the same manner, and the same effects can be exhibited. The horizontal synchronizing signal received by the address counters 4 and 5 is AF
Although the horizontal synchronizing signal E after the automatic frequency control by the C circuit is used, it is theoretically possible to use the horizontal synchronizing signal C before the automatic frequency control. In this case as well, it is possible to obtain a character video signal with less display disturbance in comparison with the character video signal generated according to the horizontal synchronizing signal C by the conventional character video signal generation circuit.

The generation of the selection signal J is not limited to that by the MPU. It may be generated by a logic circuit or a decoder that detects similar conditions. In addition, the selection signal J
Is not only generated in accordance with the operating state of the device, but may be detected by detecting that the horizontal synchronizing signal is actually in an unstable state. Such detection can be done by monitoring the frequency of the horizontal sync signal and seeing it significantly fluctuate from the standard frequency.

[0023]

As can be understood from the above description, in the video signal processing device of the present invention, the pseudo horizontal sync signal is generated at the standard frequency of the vertical address counter and the horizontal sync signal with the vertical sync signal as a reference. And a switching circuit that selectively uses one of the horizontal synchronization signal and the pseudo horizontal synchronization signal as the clock of the vertical address counter. When the horizontal synchronization signal is unstable, the vertical address counter is provided. The pseudo horizontal synchronizing signal is selected as the clock of. As a result, in the case of special reproduction such as search in VTR or still or in the case of receiving television broadcasting in a bad environment under a weak electric field, the horizontal synchronizing signal becomes unstable so that the pulse is lost. Even under severe operating conditions, it is possible to generate a character video signal with little display disturbance.

[Brief description of drawings]

FIG. 1 is a block diagram centering on a character video signal generating circuit of a VTR as an embodiment of a video signal processing device having a configuration of the present invention.

FIG. 2 is a block diagram of a conventional VTR.

[Description of Codes] 1 sync separation circuit 2 AFC circuit 3 dot clock generation circuit 4 horizontal address counter 5 vertical address counter 6 read & conversion circuit 7 display data RAM 8 synthesis circuit 10 character video signal generation circuit 100 character video signal generation circuit 101 MPU 102 Oscillation circuit 103 Counter circuit 104 Switching circuit

Claims (1)

[Claims] 1. A video signal processing device for generating a vertical address indicating a vertical display position and a horizontal address indicating a horizontal display position for a display character and generating a character video signal in accordance with these addresses. A vertical address counter that is reset by a sync signal and counts a clock and outputs the count value as the vertical address, and a dot clock of an oscillation signal that is reset by a horizontal sync signal and that is synchronized with this horizontal sync signal, and counts the count value by the horizontal address. A horizontal address counter, a pseudo horizontal sync signal generation circuit for generating a pulse at the standard frequency of the horizontal sync signal with reference to the timing of receiving the vertical sync signal, and outputting the pulse as a pseudo horizontal sync signal, and the received selection Depending on the signal, the horizontal sync signal and the previous A switching circuit that outputs one of the pseudo horizontal synchronization signals to the vertical address counter as a clock of the vertical address counter, and detects that the horizontal synchronization signal is in an unstable state such as a missing pulse state. Image signal processing, wherein the selection signal selects the pseudo horizontal synchronization signal in response to the operating state of the device under the condition that the horizontal synchronization signal is likely to be unstable. apparatus.