JPH0630344B2 - Pattern deformation measuring element - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a pattern deformation amount measuring element, and more particularly, to a semiconductor substrate for non-destructively measuring pattern deformation that occurs during epitaxial growth in a semiconductor element manufacturing process. And a measuring element formed in.

<Prior Art> Generally, in the case of a bipolar transistor, a buried layer is formed on a semiconductor substrate, an epitaxial layer is grown on the surface of the semiconductor substrate including the buried layer, and various diffusion regions are formed in the epitaxial layer. However, in the mask process for defining such a diffusion region, mask alignment is performed using the pattern of the buried layer. However, during the growth of the epitaxial layer, the growth rate depends on the plane orientation, and this plane orientation dependency appears remarkably. If so-called pattern deformation occurs, the mask alignment becomes defective. The bipolar transistor does not work properly.
Therefore, if the pattern deformation amount is grasped in advance and the mask alignment is performed in consideration of the pattern deformation amount, such a problem can be avoided.

Therefore, it is indispensable in the manufacturing process of the semiconductor device to quantitatively grasp the pattern deformation amount, and conventionally, a sample is periodically extracted from the wafer after the manufacturing process and cleaved to obtain a semiconductor. The displacement between, for example, a buried layer formed on a substrate and, for example, a diffusion layer for separation, which is mask-matched using the pattern of the buried layer, is measured using a microscope.

<Problems to be Solved by the Invention> However, in the above-described conventional pattern deformation amount measuring method, since it is necessary to cleave the wafer after the manufacturing process, it is possible to measure only a limited sample,
It was not possible to continuously grasp the pattern deformation amount and reflect this in the control of the manufacturing process. Further, a large number of semiconductor elements or integrated circuits are formed on the wafer cleaved as a sample, and these are discarded after the measurement, which is uneconomical. In addition, the measurement results of microscopes differed depending on the skill of the measurer, and the reliability of the measurement results was also low.

Therefore, in view of the above conventional problems, it is an object of the present invention to provide an economical and highly reliable pattern deformation amount measuring element without breaking a wafer.

<Means for Solving the Problems> The present invention is a measuring element for measuring the deformation amount of pattern deformation that occurs during growth of an epitaxial layer, and is capable of applying a first predetermined voltage formed on the surface portion of a semiconductor substrate. A first impurity region of the first conductivity type, a first conductivity type epitaxial layer grown on the surface of the semiconductor substrate, and a first conductivity formed on the surface of the epitaxial layer and capable of applying a second predetermined voltage. And a second impurity region of a mold, wherein the first impurity region and the second impurity region are formed simultaneously with the corresponding impurity regions of the semiconductor element formed in the product region.

<Operation and Effect> In the measuring element according to the present invention, since the first impurity region and the second impurity region are opposed to each other with the epitaxial layer sandwiched therebetween, a first predetermined voltage and a second impurity region are applied to these impurity regions. When a predetermined voltage is applied, a current path is formed in the epitaxial layer. The resistance of the current flowing through the current path in the epitaxial layer is obtained from the resistivity of the epitaxial layer, the cross-sectional area of the current path and the flow rate of the current path. In general, the resistivity of the epitaxial layer can be accurately measured or calculated, so that when the relative positional relationship between the first impurity region and the second impurity region changes and the cross-sectional area or length of the current passage changes, Impurity region and second
The voltage drop generated between the impurity region and the impurity region also changes. Therefore, if this voltage drop value is measured for each lot, it is possible to monitor the change in the pattern deformation amount during the epitaxial growth of each wafer, and to directly feed it back to the manufacturing process.

In addition, since the voltage drop value can be measured nondestructively, the semiconductor element formed in the product area of the semiconductor substrate used for the measurement can be used as a product as it is, and the cost required for the measurement can be reduced. .

Further, since the pattern deformation amount is obtained as the voltage drop value, the measurement accuracy is high and the reliability of the measurement result can be improved.

<Embodiment> FIG. 1 is a sectional view showing an embodiment of the present invention, FIG. 2 is a plan view of the embodiment, and FIG. 3 is an equivalent circuit diagram of the embodiment. In the figure, reference numeral 1 denotes a p-type semiconductor substrate having a plane orientation (1, 1, 1). In this semiconductor substrate 1, a monitor region in which various monitor patterns are formed is a bipolar transistor forming an integrated circuit. It is defined by being mixed with the product chip area to be formed. 1 and 2 show a part of the monitor region, in which a high-concentration n-type impurity region 3 is formed when the buried layer of the bipolar transistor is formed. After the formation of the impurity region 3, the low-concentration n-type epitaxial layer 5 is grown on the surface of the semiconductor substrate 1, and the high-concentration n-type impurity regions 7, 9, 11, 13, and 15 are formed at the same time as the emitter region of the bipolar transistor. In the manufacturing process of a bipolar transistor, masking is performed based on the pattern of the buried layer in the lithography step that defines the emitter region, or masking is performed on another pattern that has already been masked based on the buried layer. Therefore, the deviation due to the pattern deformation is directly reflected in the impurity region 3 formed at the same time as the buried layer and the impurity regions 7, 9, 11, 13, 15 formed at the same time as the emitter region.

In this embodiment, the impurity region 3 has a regular cross shape, and one side of the impurity region 3 extends in the <1,1,1> direction. Further, the impurity regions 7, 11, 13, and 15 are opposed to the vicinity of the four ends of the impurity region 3, and the impurity region 9 is opposed to the vicinity of the center of the impurity region 3 (see FIG. 2).
Therefore, the electric resistance generated in the current path between the impurity region 9 and the impurity region 3 is constant irrespective of the deviation due to the pattern deformation, and its value R1 is set to the specific resistance value of the epitaxial layer 5 and the thickness of the epitaxial layer 5. Required based on On the other hand, the electric resistance of the current path formed between the impurity regions 7, 11, 13, 15 and the impurity region 3 changes in the area overlapping with the impurity region 3 according to the deviation due to the pattern deformation. Value of R3, R5, R
7, R9 change according to the amount of deviation. On the other hand, since the impurity region 9 also moves with the displacement of the impurity regions 7, 11, 13, and 15, the impurity region 9 and the impurity regions 7, 11, and 1 are
The electric resistance of the impurity region 3 interposed between 3 and 15 also changes, and their values R11, R13, R15, and R17 also change corresponding to the shift amount.

Therefore, when a current is passed between the impurity regions 7 and 9,
The resistance value TR1 = (R1 + R11) between the impurity regions 7 and 9.
A voltage drop occurs in proportion to + R3). As described above, the resistance values R3 and R11 change corresponding to the shift amount based on the pattern deformation. Therefore, if the voltage drop between the impurity regions 7 and 9 is measured, the shift amount based on the pattern deformation can be calculated. You can Similarly, the impurity regions 9 and 11
The amount of deviation can be obtained from the voltage drop between the impurity regions 9 and 13, and the voltage drop between the impurity regions 9 and 15, respectively, and the direction of the deviation can be calculated from the amount of deviation.

In the above embodiment, the impurity region 9 is provided to supply the voltage to the impurity region 3, so that the power supply to the impurity region 3 can be facilitated. However, the impurity region 9 can be directly supplied without passing through the impurity region 9. A voltage may be applied to the impurity region 3 to form current paths only between the impurity region 3 and the impurity regions 7, 11, 13, and 15. In addition, the impurity region 7,
Since a plurality of 11, 13, 15 are provided, the reliability of the deviation measurement result can be improved, but the deviation amount can be measured even if only the impurity region 7 is formed.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of the present invention, and FIG.
FIG. 3 is a plan view of the measuring element according to the embodiment shown in FIG. 3, and FIG. 3 is an equivalent circuit diagram of the measuring element according to the embodiment shown in FIG. 1 ... Semiconductor substrate, 3 ... 1st impurity region, 5 ... Epitaxial layer, 7, 11, 13, 15 ... 2nd impurity region.

Claims (1)

[Claims] 1. A first conductivity type first impurity region formed on a surface portion of a semiconductor substrate and capable of applying a first predetermined voltage as a measuring element for measuring a deformation amount of pattern deformation generated during growth of an epitaxial layer. And a first-conductivity-type epitaxial layer grown on the surface of the semiconductor substrate, and a first-conductivity-type second impurity region formed on the surface of the epitaxial layer and capable of applying a second predetermined voltage. A pattern deformation amount measuring element having the first impurity region and the second impurity region formed simultaneously with the corresponding impurity regions of the semiconductor element formed in the product region.