JPH06302736A - Manufacture of lead frame for semiconductor device and semiconductor device - Google Patents
Manufacture of lead frame for semiconductor device and semiconductor deviceInfo
- Publication number
- JPH06302736A JPH06302736A JP8661193A JP8661193A JPH06302736A JP H06302736 A JPH06302736 A JP H06302736A JP 8661193 A JP8661193 A JP 8661193A JP 8661193 A JP8661193 A JP 8661193A JP H06302736 A JPH06302736 A JP H06302736A
- Authority
- JP
- Japan
- Prior art keywords
- island portion
- die
- semiconductor device
- lead frame
- side wall
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置用リードフレ
ームの製造方法および半導体装置に係わり、特に樹脂モ
ールドされる半導体装置用リードフレームの製造方法お
よび半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a lead frame for a semiconductor device and a semiconductor device, and more particularly to a method of manufacturing a resin-molded lead frame for a semiconductor device and a semiconductor device.
【０００２】[0002]
【従来の技術】リードフレームのアイランド部の半導体
ペレットを搭載した面（表面）と反対の面（裏面）を露
出させて樹脂モールドする半導体装置は、アイランド部
が放熱板としての機能を有するために、特に高出力の半
導体装置に用いられている。2. Description of the Related Art In a semiconductor device in which a surface (back surface) opposite to a surface (front surface) on which a semiconductor pellet of a lead frame is mounted is exposed and resin-molded, the island portion has a function as a heat sink. In particular, it is used for high-power semiconductor devices.
【０００３】しかしながら放熱板としてのアイランド部
には１μｍ以下の微小な凹凸があるために、図５に示す
ように、封入金型４５を用いた樹脂封入工程で樹脂４７
がアイランド部１１の露出面１３上に流れ込みこれが樹
脂バリ５１となり、外装メッキ前処理工程の例えば、水
と研磨材による樹脂バリ工程でもその除去が困難である
という問題があった。However, since the island portion as the heat dissipation plate has minute unevenness of 1 μm or less, as shown in FIG. 5, resin 47 is used in the resin encapsulation process using the encapsulation mold 45.
Has flowed onto the exposed surface 13 of the island portion 11 to form a resin burr 51, which is difficult to remove even in the external plating pretreatment step, for example, a resin burr step using water and an abrasive.
【０００４】そこで実開平２−１３６３３１号には、図
６に示すように、アイランド部１１と樹脂４７との境界
付近のアイランド部に境界に沿って突起（ダム）５３を
形成する溝５２を設け、この突起５３が封入金型と密着
して樹脂の流入をなくし樹脂バリの形成を防止する技術
が開示されている。Therefore, in Japanese Utility Model Laid-Open No. 2-136331, as shown in FIG. 6, a groove 52 is formed in the island portion near the boundary between the island portion 11 and the resin 47 to form a protrusion (dam) 53 along the boundary. A technique is disclosed in which the protrusion 53 is in close contact with the enclosed mold to prevent the inflow of resin and prevent the formation of resin burr.
【０００５】また、実開昭５８−１２２４４３号には、
図７に示すように、アイランド部５４を変形させて形成
した突起（ダム）５５により樹脂の流入による樹脂バリ
の形成を防止する技術が開示されている。In addition, Japanese Utility Model Publication No. 58-122443,
As shown in FIG. 7, a technique is disclosed in which a protrusion (dam) 55 formed by deforming the island portion 54 prevents the formation of resin burr due to the inflow of resin.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら図６に示
す方法は、アイランド部１１の側壁１４から０．１〜
０．５ｍｍ内部に離間した位置に溝５２を形成しそれに
よる突起５３を形成するものである。このように側壁か
らある一定の間隔をとって突起を形成するから、特にア
イランド部の面積が小さい半導体装置への適用が困難と
なる。However, the method shown in FIG.
The groove 52 is formed at a position spaced apart by 0.5 mm, and the projection 53 is formed by the groove 52. Since the protrusions are formed at a certain distance from the side wall as described above, it is difficult to apply the method to a semiconductor device having a small area of the island portion.
【０００７】一方、図７に示す方法では、アイランド部
５４の周辺を曲げ加工して突起５５を形成しているか
ら、アイランド部５４の中央が大きく浮いた状態とな
る。したがって外部の放熱器もしくは基板に実装した場
合に放熱性が悪くなる。さらにアイランド部に搭載でき
る半導体ペレットのサイズが小さくなるという問題を生
じる。On the other hand, in the method shown in FIG. 7, since the periphery of the island portion 54 is bent to form the protrusion 55, the center of the island portion 54 is largely floated. Therefore, when mounted on an external radiator or board, the heat dissipation becomes poor. Further, there arises a problem that the size of the semiconductor pellet that can be mounted on the island portion becomes small.
【０００８】さらに図６および図７の両技術ともに、リ
ードフレームのプレス加工工程が複雑となり、かつ所望
の幅の突起を容易に形成することが困難となる。Further, in both the techniques shown in FIGS. 6 and 7, the lead frame pressing process becomes complicated, and it becomes difficult to easily form a protrusion having a desired width.
【０００９】[0009]
【課題を解決するための手段】本発明の特徴は、放熱板
となりかつその一主面（表面）上に半導体ペレットを搭
載するアイランド部と、前記アイランド部の側壁に対向
して位置する電極リードと、前記アイランド部の前記側
壁から前記アイランド部より薄い厚さとなって前記電極
リードの方向に突出するエラ部とを有する半導体装置用
リードフレームの製造方法において、前記エラ部をプレ
ス加工により形状形成する際に同時に、前記アイランド
部の他主面（裏面）より前記アイランド部の前記側壁と
連続せる外辺を有して垂直に突出する微小な突起を形成
する半導体装置用リードフレームの製造方法にある。こ
のプレス加工において、上型プレス金型と、下型プレス
金型および該下型プレス金型から所定の間隙を有するノ
ックアウト金型との間にリードフレームを載置し、前記
上型プレス金型に対して前記下型プレス金型および前記
ノックアウト金型を同時に圧縮し、これにより前記薄い
厚さのエラ部および前記アイランド部の側壁の形状形成
を前記上型プレス金型と前記下型プレス金型との間で行
ない、前記アイランド部の平坦化を前記上型プレス金型
と前記ノックアウト金型との間で行ない、同時に、前記
下型プレス金型と前記ノックアウト金型との間の前記間
隙に前記微小な突起を形成することが好ましい。A feature of the present invention is that an island portion serving as a heat sink and having semiconductor pellets mounted on one main surface (front surface) thereof, and an electrode lead located opposite a side wall of the island portion. A lead frame for a semiconductor device having a thickness thinner than the island portion from the side wall of the island portion and protruding in the direction of the electrode lead. At the same time, a method for manufacturing a lead frame for a semiconductor device, in which a minute protrusion that vertically protrudes from the other main surface (back surface) of the island portion and has an outer side that is continuous with the side wall of the island portion is formed, is there. In this press work, a lead frame is placed between the upper die press die, the lower die die and the knockout die having a predetermined gap from the lower die die, and the upper die die is pressed. Against the lower die press die and the knockout die at the same time, thereby forming the shape of the side wall of the thin thickness gills and the island portion to the upper die die and the lower die die. Between the upper die press die and the knockout die, and at the same time, the gap between the lower die press die and the knockout die is performed. It is preferable to form the minute protrusions.
【００１０】本発明の他の特徴は、放熱板となるアイラ
ンド部と、前記アイランド部の側壁に対向して位置する
電極リードと、前記アイランド部の一主面（表面）上に
搭載された半導体ペレットと、前記半導体ぺレットと前
記電極リードを接続するボンディングワイヤーと、前記
アイランド部の他主面（裏面）を露出させかつ該他主面
と略同一の面を有するモールド樹脂とを有する半導体装
置において、前記露出したアイランド部の他主面から前
記アイランド部の側壁と連続せる外辺を有して垂直に突
出する微小な突起が形成が前記モールド樹脂との境界に
形成されている半導体装置にある。Another feature of the present invention is that an island portion serving as a heat sink, an electrode lead located opposite a side wall of the island portion, and a semiconductor mounted on one main surface (front surface) of the island portion. A semiconductor device having a pellet, a bonding wire connecting the semiconductor pellet and the electrode lead, and a mold resin exposing the other main surface (back surface) of the island portion and having a surface substantially the same as the other main surface. In the semiconductor device, in which a minute protrusion that vertically protrudes from the other main surface of the exposed island portion and has an outer side that is continuous with the side wall of the island portion is formed at the boundary with the mold resin. is there.
【００１１】[0011]
【実施例】次に図面を参照して本発明を説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.
【００１２】図１は本発明の実施例の半導体装置を示す
図面であり、（Ａ）は底面図、（Ｂ）は（Ａ）のＢ−Ｂ
部の断面図、（Ｃ）は（Ｂ）の丸１００で示した部分の
拡大図である。1A and 1B are views showing a semiconductor device according to an embodiment of the present invention. FIG. 1A is a bottom view and FIG. 1B is a BB of FIG.
A sectional view of the portion, (C) is an enlarged view of a portion indicated by a circle 100 in (B).
【００１３】放熱板となるアイランド部１１の両側にそ
の側壁１４から所定の間隔を維持してそれぞれ電極リー
ド１５が設けられ、アイランド部１１の一主面（表面）
１２上に搭載された半導体ペレット２１の電極パッドと
電極リード１５をボンディングワイヤー１６で接続して
いる。また、アイランド部１１の側壁１４からアイラン
ド部１１の厚さより薄い厚さとなって電極リード１５の
方向にそれぞれエラ部２０が突出している。そしてエラ
部２０の上面２０’はアイランド部１１の表面１２と連
続的に形成され両者は同一の高さレベルとなっており、
一方、エラ部２０の下面はアイランド部１１の他主面
（裏面）１３と両者の厚さの違いだけ階段状になってい
る。このエラ部２０は樹脂封止後に樹脂とアイランド部
との剥れを防止するためのものである。また、外部の放
熱器もしくは基板と熱抵抗を小にして実装できるように
アイランド部の裏面１３を露出させ、この裏面１３と略
同一の面１９を有するモールド樹脂１８により全体的に
封止されている。そして露出した裏面１３の端辺部か
ら、モールド樹脂１８との境界に幅ｗが１〜３μｍの微
小な突起（ダム）１７が裏面１３より垂直に突出しアイ
ランド部１１の露出する裏面１３を包囲して形成されて
いる。すなわちこの突起１７は、図１（Ｃ）に示すよう
に、アイランド部１１の側壁１４から下方向に連続して
形成された外辺１７’を有している。Electrode leads 15 are provided on both sides of the island portion 11 serving as a heat radiating plate while maintaining a predetermined distance from the side wall 14, and one main surface (front surface) of the island portion 11 is provided.
The electrode pad of the semiconductor pellet 21 mounted on the electrode 12 and the electrode lead 15 are connected by the bonding wire 16. In addition, the elastic portions 20 project from the side wall 14 of the island portion 11 in the direction of the electrode leads 15 so as to have a thickness smaller than that of the island portion 11. The upper surface 20 'of the gills 20 is continuously formed with the surface 12 of the island 11, and both have the same height level.
On the other hand, the lower surface of the gills 20 has a step shape corresponding to the other main surface (back surface) 13 of the island 11 and the difference in thickness between the two. The elastic portion 20 is for preventing the resin and the island portion from peeling off after the resin is sealed. Also, the back surface 13 of the island portion is exposed so that it can be mounted with a small thermal resistance with an external radiator or substrate, and is entirely sealed by a mold resin 18 having a surface 19 substantially the same as the back surface 13. There is. Then, a minute projection (dam) 17 having a width w of 1 to 3 μm projects vertically from the back surface 13 from the edge of the exposed back surface 13 and surrounds the exposed back surface 13 of the island portion 11. Is formed. That is, as shown in FIG. 1C, the protrusion 17 has an outer side 17 ′ continuously formed downward from the side wall 14 of the island portion 11.
【００１４】図２に本発明の実施例のリードフレームの
プレス加工の方法を示す。尚、同図において、（Ａ）は
リードフレームから下型プレス金型方向を視た平面図、
（Ｂ）は（Ａ）のＢ−Ｂ部の断面図、（Ｃ）は（Ｂ）の
微小突起の近傍を拡大して示した断面図である。FIG. 2 shows a method of pressing the lead frame according to the embodiment of the present invention. In the figure, (A) is a plan view in which the lower die pressing die direction is viewed from the lead frame,
(B) is a cross-sectional view of the BB portion of (A), and (C) is a cross-sectional view showing the vicinity of the minute protrusion of (B) in an enlarged manner.
【００１５】放熱板となりかつその表面１２上に半導体
ペレットを搭載するアイランド部１１がその電極リード
１１’となる部分により支持部２３に接続され、またア
イランド部の両側にそれぞれ位置する電極リード１５も
支持部２３に接続されてＣｕ−Ｎｉ合金の半導体装置用
リードフレーム３０を構成している。The island portion 11 serving as a heat sink and having the semiconductor pellets mounted on the surface 12 thereof is connected to the support portion 23 by the portion serving as the electrode lead 11 ', and the electrode leads 15 respectively located on both sides of the island portion are also connected. It is connected to the support portion 23 to form a lead frame 30 for a semiconductor device of Cu—Ni alloy.
【００１６】そしてこのリードフレーム３０を上型プレ
ス金型４１と、下型プレス金型４２およびノックアウト
金型４３との間に載置し、上型プレス金型に対して下型
プレス金型およびノックアウト金型を同時に圧縮して、
アイランド部１１の表面１２からアイランド部より薄い
厚さとなり、かつアイランド部１１の表面１２と連続し
た上面を上型プレス金型４１の平坦面により維持して電
極リード１５の方向にそれぞれ突出するエラ部２０を形
状形成し、電極リード１５の曲げ加工を行ない、アイラ
ンド部１１の平坦化を行ない、アイランド部１１の端辺
部の側壁１４の形状形成を行なうと同時に、アイランド
部１１の裏面１３の端辺部より裏面１３に対して垂直に
突出する本発明の微小な突起（ダム）１７を形成する。The lead frame 30 is placed between the upper die pressing die 41, the lower die pressing die 42 and the knockout die 43, and the lower die die and the lower die die are pressed against the upper die die. Compress the knockout mold at the same time,
An elastic layer which has a thickness smaller than that of the island portion 11 and which is continuous with the surface 12 of the island portion 11 is maintained by the flat surface of the upper press die 41 to project toward the electrode leads 15. The portion 20 is formed into a shape, the electrode lead 15 is bent, the island portion 11 is flattened, and the side wall 14 of the end portion of the island portion 11 is formed into a shape. The minute protrusions (dams) 17 of the present invention that project perpendicularly to the back surface 13 from the edge portions are formed.
【００１７】すなわち、エラ部２０の形状形成、電極リ
ード１５の曲げ加工は上型プレス金型４１と下型プレス
金型４２との間で行ない、アイランド部１１の側壁１４
の形状形成は下型プレス金型４２の垂直な側壁４２’に
より行ない、アイランド部１１の平坦化は上型プレス金
型４１とノックアウト金型４３との間で行ない、同時に
微小な突起１７の形成を下型プレス金型４２の垂直な側
壁４２’とノックアウト金型４３の垂直な側壁４３’と
の間の間隙ｗにより行なう。ここで下型プレス金型４２
の連続的に垂直な側壁４２’により、突起１７はアイラ
ンド部１１の側壁１４から下方向に連続して形成され
た、樹脂１８と当接する、外辺１７’を有することにな
る。そして、この間隙ｗを１〜３μｍとすることによ
り、幅が１〜３μｍで高さ（アイランド部１１の裏面１
３からの高さ）が３〜５μｍの樹脂流れ防止用の突起１
７が形成される。That is, the shape of the gills 20 and the bending of the electrode leads 15 are performed between the upper die 41 and the lower die 42 to form the sidewall 14 of the island 11.
Is formed by the vertical side wall 42 'of the lower press die 42, and the island portion 11 is flattened between the upper press die 41 and the knockout die 43, and at the same time the minute protrusions 17 are formed. Is performed by the gap w between the vertical side wall 42 ′ of the lower press die 42 and the vertical side wall 43 ′ of the knockout die 43. Here, the lower die 42
Due to the continuously vertical side walls 42 ', the protrusion 17 has an outer side 17' formed continuously from the side wall 14 of the island portion 11 in a downward direction and in contact with the resin 18. Then, by setting the gap w to be 1 to 3 μm, the width is 1 to 3 μm and the height (the back surface 1 of the island portion 11 is
3 to 5 μm in height) 3 to prevent resin flow
7 is formed.
【００１８】このように加工されたリードフレームのア
イランド部１１の表面１２上に半導体ペレットを搭載し
その電極パッドと電極リード１５をボンディングワイヤ
ーで接続し、アイランド部１１の裏面１３が露出するよ
うに樹脂封止される。A semiconductor pellet is mounted on the surface 12 of the island portion 11 of the lead frame thus processed, and its electrode pad and electrode lead 15 are connected by a bonding wire so that the back surface 13 of the island portion 11 is exposed. It is resin-sealed.
【００１９】図３は樹脂封止の状態をアイランド部１１
の裏面１３側から視た平面図である。封止金型４５の流
入口４６から樹脂１８が流入して樹脂モ−ルドされる
が、突起１７の存在により樹脂の露出裏面１３への侵入
による樹脂バリの問題は発生しない。FIG. 3 shows the state of resin sealing in the island portion 11
It is the top view seen from the back surface 13 side. The resin 18 flows in through the inflow port 46 of the sealing mold 45 and is resin-molded, but the presence of the protrusion 17 does not cause the problem of resin burr due to the resin entering the exposed back surface 13.
【００２０】なお、図１では樹脂１８との境界の全ての
部分にわたって突起１７が形成された場合を例示したの
に対して、図２および図３ではアイランド部１１の放熱
板としての幅広の本体と樹脂１８との境界に突起１７を
形成し幅広の本体から幅狭のリード部１１’にいたる部
分には突起１７が形成していない場合を例示した。しか
しながら図２および図３において周囲に突起１７が形成
されていない部分はアイランド部全体からみて小面積の
部分であるから、たとえわずかな樹脂の侵入がこの小面
積の部分にあってもそれによるわずかな樹脂バリは外装
メッキ前処理で簡単に除去できるから問題は生じない。
また、樹脂モールド工程後の外装メッキにより突起１７
間のアイランド部１１の裏面１３上にメッキ膜が形成さ
れるから、リードフレーム３０の電極リード１５、１
１’をその支持部２３から切り離して得られた最終的な
製品として突起１７が存在していても半導体装置から実
装基板への熱伝導に支障を生じない。While FIG. 1 illustrates the case where the protrusions 17 are formed over the entire portion of the boundary with the resin 18, in FIGS. 2 and 3, a wide main body as a heat sink of the island portion 11 is illustrated. An example is shown in which the protrusion 17 is formed at the boundary between the resin 18 and the resin 18 and the protrusion 17 is not formed in the portion from the wide body to the narrow lead portion 11 ′. However, in FIG. 2 and FIG. 3, the portion where the protrusions 17 are not formed on the periphery is a small area as viewed from the entire island portion. Since such resin burrs can be easily removed by pretreatment for exterior plating, no problem occurs.
In addition, the protrusion 17 is formed by the exterior plating after the resin molding process.
Since the plating film is formed on the back surface 13 of the island portion 11 between the electrode portions 15 and 1 of the lead frame 30,
Even if the protrusions 17 are present as a final product obtained by separating 1 ′ from the supporting portion 23, heat conduction from the semiconductor device to the mounting substrate is not hindered.
【００２１】図４は本発明の上記実施例の一部を変更し
た半導体装置として、多ピン小信号半導体装置に本発明
を適用した樹脂モールドの状態を示す平面図である。同
図において、図１および図２と同一もしくは類似の機能
の箇所は同じ符号で示してあるから重複する説明は省略
する。この半導体装置ではリードフレームのアイランド
部の裏面の露出部が２箇所存在する。この場合も図１、
図２に示した効果と同様の効果を有する。FIG. 4 is a plan view showing a state of a resin mold in which the present invention is applied to a multi-pin small signal semiconductor device as a semiconductor device obtained by modifying a part of the above embodiment of the present invention. In the figure, the portions having the same or similar functions as those in FIGS. 1 and 2 are denoted by the same reference numerals, and the duplicated description will be omitted. In this semiconductor device, there are two exposed portions on the back surface of the island portion of the lead frame. In this case also,
It has the same effect as that shown in FIG.
【００２２】[0022]
【発明の効果】以上説明したように本発明は、リードフ
レームのエラ部の形状形成と樹脂流れ防止用の突起の形
成とを同一のプレス工程で行なうから工程が簡素化され
た能率的な半導体装置用リードフレームの製造方法とな
る。As described above, according to the present invention, the shape of the elastic portion of the lead frame and the protrusion for preventing resin flow are formed in the same pressing step, so that the process is simplified and efficient. This is a method for manufacturing a lead frame for a device.
【００２３】また本発明は、アイランド部の露出した裏
面からアイランド部の側壁と連続せる外辺を有して垂直
に突出する微小な突起が形成されているから、アイラン
ド部の面積が小さい場合でも突起の形成が可能となり、
かつ良好な放熱性を維持したアイランド部となる。Further, according to the present invention, since minute protrusions are formed which vertically project from the exposed back surface of the island portion so as to have outer edges continuous with the sidewalls of the island portion, even when the area of the island portion is small. It is possible to form protrusions,
In addition, it becomes an island portion that maintains good heat dissipation.
【図１】本発明の実施例の半導体装置を示す図面であ
り、（Ａ）は底面図、（Ｂ）は（Ａ）のＢ−Ｂ部の断面
図、（Ｃ）は（Ｂ）の丸１００で示した部分を拡大して
示した断面図である。1A and 1B are drawings showing a semiconductor device of an embodiment of the present invention, in which FIG. 1A is a bottom view, FIG. 1B is a cross-sectional view taken along the line BB in FIG. 1A, and FIG. It is sectional drawing which expanded and showed the part shown by 100.
【図２】本発明の実施例の半導体装置用リードフレーム
の製造方法を示す図面であり、（Ａ）はリードフレーム
から下型プレス金型方向を視た平面図、（Ｂ）は（Ａ）
のＢ−Ｂ部の断面図、（Ｃ）は（Ｂ）の微小突起の近傍
を拡大して示した断面図である。2A and 2B are diagrams showing a method for manufacturing a lead frame for a semiconductor device according to an embodiment of the present invention, FIG. 2A is a plan view of the lead frame as seen from the lower die pressing die direction, and FIG.
2B is a cross-sectional view of the B-B part, and FIG. 6C is an enlarged cross-sectional view of the vicinity of the minute protrusion of FIG.
【図３】図２によるリードフレームを用いて樹脂封止を
する状態をアイランド部の露出する裏面側から視た平面
図である。FIG. 3 is a plan view of a state where resin sealing is performed using the lead frame shown in FIG. 2 as viewed from the back surface side where the island portion is exposed.
【図４】本発明の図１、図２に示した実施例の一部を変
更した半導体装置の樹脂モールドの状態を示す平面図で
ある。FIG. 4 is a plan view showing a state of a resin mold of a semiconductor device obtained by partially modifying the embodiment shown in FIGS. 1 and 2 of the present invention.
【図５】樹脂封入における不都合な樹脂流れを示す底面
図である。FIG. 5 is a bottom view showing an inconvenient resin flow in resin encapsulation.
【図６】樹脂封入における樹脂流れに対する従来技術を
示す断面図である。FIG. 6 is a cross-sectional view showing a conventional technique for resin flow in resin encapsulation.
【図７】樹脂封入における樹脂流れに対する他の従来技
術を示す断面図である。FIG. 7 is a cross-sectional view showing another conventional technique for resin flow in resin encapsulation.
１１ アイランド部 １１’ アイランド部１１に接続する電極リード １２ アイランド部の表面 １３ アイランド部の裏面 １４ アイランド部の側壁 １５ 電極リード １６ ボンディングワイヤー １７ 微小な突起（ダム） １７’ 突起１７の外辺 １８ モールド樹脂 １９ モールド樹脂の面 ２０ エラ部 ２０’ エラ部２０の上面 ２１ 半導体ペレット ２３ 支持部 ３０ 半導体装置用リードフレーム ４１ 上型プレス金型 ４２ 下型プレス金型 ４２’ 下型プレス金型の側壁 ４３ ノックアウト金型 ４５ 封止金型 ４６ 樹脂流入口 ５１ 樹脂バリ ５２ 溝 ５３ 突起 ５４ アイランド部 ５５ 突起 11 Island Part 11 'Electrode Leads Connected to Island Part 11 12 Surface of Island Part 13 Backside of Island Part 14 Sidewall of Island Part 15 Electrode Lead 16 Bonding Wire 17 Minute Protrusion (Dam) 17' Outer Side of Protrusion 17 18 Mold Resin 19 Mold resin surface 20 Error part 20 'Upper surface of error part 20 Semiconductor pellet 23 Support part 30 Semiconductor device lead frame 41 Upper die press die 42 Lower die die 42' Lower die die side wall 43 Knockout mold 45 Sealing mold 46 Resin inlet 51 Resin burr 52 Groove 53 Projection 54 Island part 55 Projection
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 23/28 Ａ 8617−4Ｍ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location H01L 23/28 A 8617-4M
Claims (5)
ペレットを搭載するアイランド部と、前記アイランド部
の側壁に対向して位置する電極リードと、前記アイラン
ド部の前記側壁から前記アイランド部より薄い厚さとな
って前記電極リードの方向に突出するエラ部とを有する
半導体装置用リードフレームの製造方法において、前記
エラ部をプレス加工により形状形成する際に同時に、前
記アイランド部の他主面より前記アイランド部の前記側
壁と連続せる外辺を有して垂直に突出する微小な突起を
形成することを特徴とする半導体装置用リードフレーム
の製造方法。1. An island portion serving as a heat sink and having semiconductor pellets mounted on one main surface thereof, an electrode lead located opposite a side wall of the island portion, and the island portion extending from the side wall to the island portion. In a method for manufacturing a lead frame for a semiconductor device having a thin thickness and an elastic portion projecting in the direction of the electrode lead, at the same time when the elastic portion is formed by press working, at the same time from the other main surface of the island portion. A method of manufacturing a lead frame for a semiconductor device, comprising forming a minute protrusion that has an outer periphery continuous with the side wall of the island portion and vertically protrudes.
型と、下型プレス金型および該下型プレス金型から所定
の間隙を有するノックアウト金型との間にリードフレー
ムを載置し、前記上型プレス金型に対して前記下型プレ
ス金型および前記ノックアウト金型を同時に圧縮し、こ
れにより前記薄い厚さのエラ部および前記アイランド部
の側壁の形状形成を前記上型プレス金型と前記下型プレ
ス金型との間で行ない、前記アイランド部の平坦化を前
記上型プレス金型と前記ノックアウト金型との間で行な
い、同時に、前記下型プレス金型と前記ノックアウト金
型との間の前記間隙に前記微小な突起を形成することを
特徴とする請求項１に記載の半導体装置用リードフレー
ムの製造方法。2. In the press working, a lead frame is placed between an upper die and a lower die and a knockout die having a predetermined gap from the lower die, and Simultaneously compressing the lower press die and the knockout die with respect to the upper die, thereby forming the shape of the side wall of the thin thickness gills and the island with the upper die. Performed between the lower die and the lower die, flattening the island portion between the upper die and the knockout die, and at the same time, the lower die and the knockout die. The method for manufacturing a lead frame for a semiconductor device according to claim 1, wherein the minute protrusions are formed in the gaps between them.
前記微小な突起の幅を１〜３μｍにしたことを特徴とす
る請求項１もしくは請求項２に記載の半導体装置用リー
ドフレームの製造方法。3. The method of manufacturing a lead frame for a semiconductor device according to claim 1, wherein the width of the minute protrusion is set to 1 to 3 μm by setting the gap to 1 to 3 μm. .
ランド部の側壁に対向して位置する電極リードと、前記
アイランド部の一主面上に搭載された半導体ペレット
と、前記半導体ぺレットと前記電極リードを接続するボ
ンディングワイヤーと、前記アイランド部の他主面を露
出させかつ該他主面と略同一の面を有するモールド樹脂
とを有する半導体装置において、前記露出したアイラン
ド部の他主面から前記アイランド部の側壁と連続せる外
辺を有して垂直に突出する微小な突起が形成が前記モー
ルド樹脂との境界に形成されていることを特徴とする半
導体装置。4. An island portion serving as a heat sink, an electrode lead located opposite to a side wall of the island portion, a semiconductor pellet mounted on one main surface of the island portion, the semiconductor pellet and the semiconductor pellet. In a semiconductor device having a bonding wire connecting an electrode lead and a mold resin exposing the other main surface of the island portion and having a surface substantially the same as the other main surface, from the exposed other main surface of the island portion A semiconductor device, wherein minute protrusions having an outer side continuous with a side wall of the island portion and protruding vertically are formed at a boundary with the mold resin.
ことを特徴とする請求項４に記載の半導体装置。5. The semiconductor device according to claim 4, wherein the width of the minute protrusion is 1 to 3 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5086611A JP2546129B2 (en) | 1993-04-14 | 1993-04-14 | Method for manufacturing lead frame for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5086611A JP2546129B2 (en) | 1993-04-14 | 1993-04-14 | Method for manufacturing lead frame for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06302736A true JPH06302736A (en) | 1994-10-28 |
| JP2546129B2 JP2546129B2 (en) | 1996-10-23 |
Family
ID=13891819
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5086611A Expired - Fee Related JP2546129B2 (en) | 1993-04-14 | 1993-04-14 | Method for manufacturing lead frame for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2546129B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008270661A (en) * | 2007-04-24 | 2008-11-06 | Mitsui High Tec Inc | Lead frame, lead frame manufacturing method, semiconductor device, and semiconductor device manufacturing method |
| JP2012004605A (en) * | 2011-10-05 | 2012-01-05 | Mitsui High Tec Inc | Lead frame, lead frame manufacturing method, semiconductor device, and semiconductor device manufacturing method |
| JP2013175795A (en) * | 2013-06-12 | 2013-09-05 | Mitsui High Tec Inc | Manufacturing method of lead frame |
| JP2017034130A (en) * | 2015-08-03 | 2017-02-09 | エスアイアイ・セミコンダクタ株式会社 | Semiconductor device and manufacturing method of the same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05226532A (en) * | 1992-02-17 | 1993-09-03 | Apitsuku Yamada Kk | Manufacture of lead frame for power transistor |
-
1993
- 1993-04-14 JP JP5086611A patent/JP2546129B2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05226532A (en) * | 1992-02-17 | 1993-09-03 | Apitsuku Yamada Kk | Manufacture of lead frame for power transistor |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008270661A (en) * | 2007-04-24 | 2008-11-06 | Mitsui High Tec Inc | Lead frame, lead frame manufacturing method, semiconductor device, and semiconductor device manufacturing method |
| JP2012004605A (en) * | 2011-10-05 | 2012-01-05 | Mitsui High Tec Inc | Lead frame, lead frame manufacturing method, semiconductor device, and semiconductor device manufacturing method |
| JP2013175795A (en) * | 2013-06-12 | 2013-09-05 | Mitsui High Tec Inc | Manufacturing method of lead frame |
| JP2017034130A (en) * | 2015-08-03 | 2017-02-09 | エスアイアイ・セミコンダクタ株式会社 | Semiconductor device and manufacturing method of the same |
| CN106409694A (en) * | 2015-08-03 | 2017-02-15 | 精工半导体有限公司 | Semiconductor device and method of manufacturing the same |
| CN106409694B (en) * | 2015-08-03 | 2020-08-25 | 艾普凌科有限公司 | Semiconductor device and method for manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2546129B2 (en) | 1996-10-23 |
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