JPH06302667A - Chamber system - Google Patents

Abstract

PURPOSE:To operate a system without being affected by the failure of at least one of wafer transport chambers. CONSTITUTION:A plurality of multi-chambers which are constituted by connecting process chambers 13 and 14 for performing each kind of treatment to a semiconductor wafer to a wafer transport chamber 1 are connected in ring shape, at the same time process chambers 7 and 12 are provided at the connection part between the multi-chambers, and the process chambers are also used for transport chambers. In the similar manner, process chambers 8, 9, 10, 11, and 12 are provided between other wafer transport chambers.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for constructing a chamber system used in semiconductor manufacturing, and more particularly to a technique effectively used for integrated automated production of semiconductor devices using multiple chambers.

[0002]

2. Description of the Related Art A chamber is a device for forming a space isolated from an indoor atmosphere in order to perform processes such as cleaning, film deposition, and processing of semiconductor wafers. A mechanism for making a vacuum, a mechanism for introducing / exhausting a processing gas, and the like are provided as needed.

In recent years, for the purpose of efficient production of semiconductor devices and reduction of installation space, a multi-chamber system in which a plurality of chambers are formed as one device and a plurality of processes can be performed by one device is proposed and manufactured. Has been done. Regarding this kind of technology, for example, monthly publication “Semiconductor World” 199.
0.9, P105 to P139.

A typical structure thereof is that a transfer chamber is provided at the center for carrying in and out semiconductor wafers, and a plurality of chambers (process chambers, load chambers) are provided on the circumference of the transfer chamber so as to surround the chamber. A lock chamber or the like is arranged, and a semiconductor wafer is loaded into or unloaded from each chamber via the transfer chamber.

Such a multi-chamber system has the following features.

(1) In the multi-chamber system, integrated processing can be performed in a vacuum or in an inert gas atmosphere, and when a layer is formed, contamination or the like can be prevented from entering from the outside and quality can be improved. . In addition, it is possible to stabilize the film formation.

(2) Since consistent processing can be performed in the multi-chamber system, the time required for wafer transfer can be reduced and the overall process can be shortened.

(3) When adapting to a new process, only the chamber of the process can be newly manufactured, and conventional wafer transfer robot parts, load lock chambers, etc. can be used. Can be reduced.

[0009]

According to the study by the present inventor, a conventional multi-chamber system having a transfer chamber as a center and a plurality of chambers arranged around the transfer chamber is a process for connecting one wafer transfer chamber. Since the number of chambers is limited to several or less, there is a problem that the process to which the consistent processing can be applied is short.

Further, if the number of process chambers is increased, the wafer transfer chamber must be added, and the docking chamber needs to be added accordingly, which requires a large installation space. Furthermore, since there is only one wafer transfer port, there is also a problem that if this fails, it will not be possible to carry in / out the semiconductor wafer from / to the chamber.

Therefore, an object of the present invention is to provide a technique capable of operating a system without being affected by at least one of the wafer transfer chambers, even if one of them fails.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0013]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, a chamber system using a multi-chamber having a structure in which a plurality of process chambers for performing various processes on a semiconductor wafer are connected to a wafer transfer chamber, and a plurality of the multi-chambers are connected and connected. , Arranging a process chamber at its connection,
Moreover, this process chamber is also used as a transfer chamber.

[0015]

According to the above-mentioned means, the process chamber provided between the wafer transfer chambers is provided with two wafer transfer ports, so that even if a certain wafer transfer chamber fails and cannot be used, another process transfer port can be used. It is possible to carry the wafer into another adjacent wafer transfer chamber through one wafer transfer port. Therefore, even if the semiconductor wafer comes to be interposed in the process chamber adjacent to the wafer transfer chamber where the failure or the like occurs, the semiconductor wafer can be transferred without delay.

[0016]

Embodiment 1 FIG. 1 is a plan view showing an embodiment of the chamber system according to the present invention.

As shown in FIG. 1, each of the wafer transfer chambers 1, 2, 3, 4, 5 and 6 whose side walls are formed in a hexagonal shape is arranged on one circumferential line, and the chambers have transfer ports. Process chambers 7, 8, 9, 10, 1 having two
It is connected so as to make one round through each of 1 and 12. Since there are two transfer ports in this way, the semiconductor wafer can be transferred clockwise or counterclockwise to the adjacent chamber. In the wafer transfer chamber 1, process chambers 13 and 14 are connected to the respective wall surfaces. Incidentally, in the conventional case, the process chambers 7, 8,
Each of 9, 10, 11, 12 was a docking chamber.

Similarly, process chambers 15 and 16 are connected to the wafer transfer chamber 2, process chambers 17 and 18 to the wafer transfer chamber 3, process chamber 19 to the wafer transfer chamber 4, and wafer transfer chamber 5 respectively.
Are connected to the process chambers 20 and 21, and the wafer transfer chamber 6 is connected to the process chambers 22, 23 and 24. Each of the process chambers 13 to 24 has one transfer port, and semiconductor wafers are loaded and unloaded through the connected wafer transfer chambers. The hollow portion at the center of this system is vacant and used as a working space.

FIG. 2 is a sectional view taken along the line AA in FIG.

In FIG. 2, a wafer transfer arm 26 for transferring a semiconductor wafer 25 to be processed is horizontally arranged in the wafer transfer chamber 1, and similarly, a wafer transfer arm 27 is horizontally set in the wafer transfer chamber 2. It is arranged. The wafer transfer arm 26 is arranged so as to face a wafer transfer port 28 that connects the wafer transfer chamber 1 and the process chamber 7, and connects the wafer transfer chamber 2 and the process chamber 7. The wafer transfer port 29 is arranged so as to face it.

Further, a sample table 30 is installed in the center of the process chamber 7, and a semiconductor wafer 25 is provided on the upper surface thereof.
Is placed. When carrying the semiconductor wafer 25 in the process chamber 7 into the wafer transfer chamber 1 or the wafer transfer chamber 2, the wafer transfer arm 26 or the wafer transfer arm 27 is expanded and contracted to move the semiconductor wafer 25.

FIG. 3 is a block diagram showing the software configuration of the control system of the chamber system according to the present invention. Here, for convenience of explanation, only six chambers are shown and the others are omitted, but in reality, all the chambers shown in FIG. 1 are connected.

The control unit 31 is mainly composed of a higher-level management unit 32. The higher-level management unit 32 has a device usage status monitoring program 33 for monitoring the usage status of each chamber, which of the chambers is combined with which one. A chamber configuration file 34 for determining and a wafer progress management file 35 for managing the progress of the semiconductor wafer to be processed are connected to each other.

The upper management unit 32 is configured to include a memory such as a ROM and a RAM in addition to a CPU and peripheral circuits, and an interface circuit, etc., and determines the shortest path from one process chamber to a specific process chamber, The semiconductor wafer 25 can be transferred to the specified chamber. At this time, the device usage status monitoring program 3
3 checks the use status of each chamber, and sets the flag to "1" if it is in use and sets the flag to "0" if it is not used. In the example of FIG. 3, only the wafer transfer chamber 2 is in use.

Here, an example of the process processing will be described with reference to FIG. First, the semiconductor wafer 25 is carried into the process chamber 13 from the wafer transfer chamber 1, where a predetermined process is performed, and then the semiconductor wafer 25 is carried into the wafer transfer chamber 14 via the wafer transfer chamber 1.
When the processing here is completed, the wafer is carried into the process chamber 15 through the wafer transfer chamber 1-> process chamber 7-> wafer transfer chamber 2 in that order.

Further, the wafer is carried into the adjacent process chamber 16 via the wafer transfer chamber 2, and when the processing here is completed, it is carried into the process chamber 17 via the process chamber 8 and the wafer transfer chamber 3. Thereafter, in the same manner, the semiconductor wafer 25 is formed in each chamber as shown in FIG.
As shown in FIG. 3, the wafers are sequentially transferred to the process chamber 12 and returned to the wafer transfer chamber 1.

Although the semiconductor wafer 25 is processed by sequentially passing through the wafer transfer chamber and the process chamber, it is not necessary to pass through all of the wafer transfer chamber 1 to the wafer transfer chamber 6, and the process is short. In processing, it may be carried out from a chamber on the way.

FIG. 5 shows an example of processing steps. First, cleaning (step 501) is performed, and then film formation (step 502) → resist coating (step 503) → resist development (mask pattern formation) (step 504). )-> Etching (step 505)-> resist removal (step 506)-> post-treatment (step 507)-> cleaning (step 508), and thereafter, the process shown in FIG. 5 is repeatedly executed. For example, when applied to FIG. 1, if the process chambers 13 and 14 are cleaning, the process chamber 15 is thin film deposition, the process chamber 16 is metal film deposition, and the process chamber 8 is mask formation (for the process chamber 17 and thereafter). Is omitted).

[0029]

Second Embodiment FIG. 6 is a plan view showing another embodiment of the present invention. Note that, in FIG. 6, the same reference numerals are used for the same elements as those in FIG. 1, and thus redundant description will be omitted below.

In the present embodiment, the process chamber 3 is provided in the circular space at the center so as to be in contact with each of the wafer transfer chambers 1, 2, 3, 4, 5, 6 in FIG.
5, 36, 37, 38, 39, 40 are respectively arranged, and the wafer carrying chamber 34 is provided at the center of these.

A case where the semiconductor wafer 25 is transferred to the wafer transfer chamber 1 in such a configuration will be described. In this case, those processed in the process chambers 7, 35, 12 have two wafer outlets, and therefore, the contents of the next process processing and the wafers in the wafer transfer chambers 1, 2, 34, 6 The wafer is transferred to an appropriate wafer transfer chamber according to the transfer state.

For example, when transferring from the wafer transfer chamber 1 to the wafer transfer chamber 2, even if the process chamber 7 fails, it can be transferred to the wafer transfer chamber 2 via the process chambers 35 and 36. Therefore, the process processing is not affected by the failure of the wafer transfer chamber. For example, 1
Even if the wafer transfer chamber of the table fails and cannot be used, it can be used as a multi-chamber system.

The invention made by the inventor of the present invention has been specifically described above based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, in the above-described embodiment, the semiconductor wafer to be processed is conveyed in the clockwise direction, but it may be conveyed in the opposite direction (counterclockwise).

[0035]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.

That is, a chamber system using a multi-chamber having a structure in which a plurality of process chambers for performing various processes on a semiconductor wafer are connected to a wafer transfer chamber, and a plurality of the multi-chambers are connected and connected. , Arranging a process chamber at its connection,
In addition, since this process chamber is also used as the transfer chamber, the transfer of the semiconductor wafer can be performed smoothly even if the semiconductor wafer intervenes in the process chamber adjacent to the wafer transfer chamber where the failure or the like occurs. It becomes possible to improve processing efficiency.

[Brief description of drawings]

FIG. 1 is a plan view showing an embodiment of a chamber system according to the present invention.

FIG. 2 is a sectional view taken along the line AA in FIG.

FIG. 3 is a block diagram showing a software configuration of a control system of the chamber system according to the present invention.

FIG. 4 is an explanatory view showing a combination example of the process chamber of the present invention with respect to a certain process.

FIG. 5 is a flowchart showing the contents and procedure of processing steps in the present invention.

FIG. 6 is a plan view showing another embodiment of the present invention.

[Explanation of symbols]

 1, 2, 3 Wafer transfer chambers 4, 5, 6 Wafer transfer chambers 7, 8, 9 Process chambers 10, 11, 12 Process chambers 13, 14, 15 Process chambers 16, 17, 18 Process chambers 19, 20, 21 Processes Chamber 22, 23, 24 Process chamber 25 Semiconductor wafer 26, 27 Wafer transfer arm 28, 29 Wafer transfer port 30 Sample stage 31 Control unit 32 Upper management unit 33 Device usage monitoring program 34 Chamber configuration file 35, 36, 37 Process chamber 38, 39, 40 process chambers

Claims (4)

[Claims] 1. A chamber system using a multi-chamber having a structure in which a plurality of process chambers for performing various processes on a semiconductor wafer are connected to a wafer transfer chamber, and the plurality of multi-chambers are connected and connected. A chamber system in which a process chamber is arranged at the connection portion thereof, and the process chamber is also used as a transfer chamber. 2. The chamber system according to claim 1, wherein the chambers for both transfer and process and the wafer transfer chambers are connected alternately and in a ring shape. 3. The chamber system according to claim 1, further comprising a process chamber which communicates with an adjacent or another arbitrary wafer transfer chamber, in addition to the chamber for both transfer and process. 4. When transferring a semiconductor wafer, if there is a wafer transfer chamber already in use, a control means for selecting a path for transfer using the chamber for both transfer and process or another wafer transfer chamber. The chamber system according to claim 1, further comprising: