JPH0950948A - System coping with failure of semiconductor manufacturing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To continue a substrate treatment even if a failure is produced in one of processing systems by using the remaining normal processing systems and improve the production efficiency as a whole. SOLUTION: In a semiconductor manufacturing apparatus, substrates are separately treated by a plurality of process systems (PM1/PM2 and PM4/PM3). If a failure is produced in one (PM1/PM2) of the process systems, an integrated controller detects the failure and substrates which are to be treated by the process system in which the failure is produced are transferred to the other normal process system (PM4/PM3) and the treatment of substrates is continued. By continuing the substrate treatment as above described, the production efficiency as a whole can be improved in comparison with the conventional constitution wherein the treatment is interrupted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing apparatus in which a plurality of process systems are constituted by a plurality of process modules, and a substrate to be processed is distributed and processed in each process system. The present invention relates to a failure coping system that allows an integrated controller to continue substrate processing in the remaining process system when an error occurs.

[0002]

2. Description of the Related Art A semiconductor manufacturing apparatus for subjecting a substrate to be processed such as a silicon wafer to process processing such as etching, ashing, film formation, etc. has a module for accommodating the substrate for loading and unloading and a module for transporting the substrate. It is known that a module for performing a predetermined process on a substrate is connected via a gate valve to automatically and continuously perform the above process and substrate transfer.

FIG. 1 shows an example of the structure of a single-wafer cluster type semiconductor manufacturing apparatus as an example of such a semiconductor manufacturing apparatus. This semiconductor manufacturing apparatus includes four process modules PM1 to PM4 and two cassette modules C.
M1 and CM2, transport module TM,
The transport module TM includes process modules PM1 to PM4 and a cassette module C.
Each of M1 and CM2 is airtightly connected via a gate valve (not shown).

The process modules PM1 to PM4 are modules for performing a predetermined process on a wafer to be processed. In this example, the process modules PM1 to PM4 are processed.
The PM4 is divided into two systems to disperse the wafer. That is, the process modules PM1 and PM4,
Then, the process modules PM2 and PM3 execute the same wafer processing, and the process modules PM1 and PM3
2 and a process module PM4
The wafer is subjected to a series of processes by the process system including the PM3 and PM3.

Further, cassette modules CM1 and CM2
Is a module that accommodates a plurality of (for example, 10) wafers. In this example, the cassette module CM1 is set as a carry-in module (load module) that accommodates unprocessed wafers, and the cassette module CM2 is processed by a process system. It is set as a carry-out module (unload module) that accommodates the processed wafer. Further, the transport module TM accommodates the robot arm R for transferring the wafer, and the cassette module CM
1 and the process modules PM1 and PM4, between the process modules PM1 and PM2 and PM4 and PM3, and between the process modules PM2 and PM3 and the cassette module CM2. During the wafer transfer, the gate valve that closes the passage between the modules is opened and closed.

The operation by the process modules PM1 to PM4, the cassette modules CM1 and CM2, and the transport module TM is performed by the controllers PC1 to PC4, CC1 and CC2 attached to the respective modules.
Directly controlled by TC. Then, as shown in FIG. 2, these controllers PC1 to PC4, CC1,
CC2 and TC are connected to an integrated control controller GC via a network N such as a LAN, and control of each module PM1 to PM4, CM1, CM2, TM by each controller PC1 to PC4, CC1, CC2, TC is integrated. The controller GC integrally controls.

The integrated controller GC is provided with a wafer transfer table T having the contents shown in FIG.
The integrated control controller GC controls according to the contents of the table T, so that the wafer has two process system PMs.
1 and PM2 and PM4 and PM3 are distributed and transported,
Process processing is carried out in each system. In the example shown in FIG. 3, the wafers housed in the cassette module CM1 are divided into odd-numbered wafers and even-numbered wafers, and the odd-numbered wafers are formed by modules CM1, PM1, PM2, and CM2. The first wafer is each module CM1,
Processing is performed in a distributed manner by a path including PM4, PM3, and CM2.

That is, as shown in FIG. 4, the first wafer is transferred from the cassette module CM1 to the process module PM1 for processing, further transferred to the process module PM2 for processing, and then the cassette module CM2. Be transported to. Further, the second wafer is transferred by the robot arm R to the process module PM4 from the cassette module CM1 and processed for a short waiting time so that the second module is processed. After being transported to PM3 and processed, it is transported to the cassette module CM2. The third and fourth and subsequent wafers are similarly processed after the processing for the previous wafer is completed.

[0009]

Here, in semiconductor manufacturing, various troubles occur, for example, process conditions in a process module change due to external factors, a processing error occurs in a controller of each module, and the like. There are cases. With respect to the occurrence of such a failure, in the above-described conventional semiconductor manufacturing apparatus, the integrated control controller interrupts all processing operations even if the failure location is a part of the process system. Therefore, even when the number of unprocessed wafers is small, the processing of these wafers is not continued, and as a result, the wafer processing is significantly delayed.

The present invention has been made in view of the above conventional circumstances, and when a failure occurs in a part of the process system, the substrate (wafer) processing is continued in the remaining normal process system, and the overall production efficiency is improved. It is an object of the present invention to provide a failure coping system for a semiconductor manufacturing apparatus that improves the performance.

[0011]

In order to achieve the above object, a failure coping system for a semiconductor manufacturing apparatus according to the present invention includes a carry-in module for accommodating a plurality of substrates to be processed, and a predetermined process for the substrates. In a semiconductor manufacturing apparatus in which a process module and a carry-out module that accommodates a processed substrate are connected via a transport module that transports the substrate between the modules, a plurality of the process modules are provided and the transport module is used. The board from the carry-in module is distributed to each process module and transported, the boards are distributed to each of the multiple process systems, and the integrated controller that controls each module centrally controls the failure in any process system. To control each module and remove the remaining Characterized in that to continue the substrate treated with processes based.

[0012]

According to the present invention, when a failure occurs in any one of the process systems while the substrate is distributed and processed by the plurality of process systems, the integrated controller detects the occurrence of the failure. Then, the integrated control controller transfers the substrate to be processed in the failed process system to the remaining normal process system, and continues the processing of these substrates. Therefore, although the processing is delayed by the amount of the process system in which the failure has occurred, by continuing the substrate processing, it is possible to improve the production efficiency as a whole, as compared with the case where all the processing is interrupted.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A fault coping system for a semiconductor manufacturing apparatus according to an embodiment of the present invention will be described with reference to the drawings. The present embodiment is one in which the present invention is applied to the semiconductor manufacturing apparatus shown in FIGS. 1 and 2, and the same reference numerals are given to the parts already described and the duplicated description will be omitted. Process module P
In a state in which both the process system including M1 and PM2 and the process system including process modules PM4 and PM3 are operating normally without any failure, the integrated controller GC in FIG. Controllers PC1 to PC4, C according to the table contents shown in
C1, CC2, and TC are collectively controlled, and as shown in FIG. 4, wafers are divided into odd-numbered wafers and even-numbered wafers and dispersed in respective process systems.

The integrated controller GC of this embodiment is
Upon receiving an error signal from each process module controller PC1 to PC4, each process module controller PC1 to PC4 and each process module PC1 to
It has means for detecting the occurrence of a failure in the PC 4, and this failure occurrence is constantly detected during system operation. Further, the integrated control controller GC of the present embodiment has means for rewriting the contents of the wafer transfer table T, and when a failure is detected, the contents of the table T are rewritten by this rewriting means, and the process in which the failure has occurred. Degenerate operation is performed in which wafers to be processed by the system are transferred to the remaining normal process system and processing is continued. In the present embodiment, the operator can operate the operation panel of the integrated controller GC to instruct the operator to select whether or not to perform the degenerate operation, and only when the instruction is issued,
The integrated controller GC carries out degenerate operation.

Next, the operation of the system of this embodiment when a failure occurs in the process module controllers PC1 to PC4 and the process modules PC1 to PC4 forming each process system will be described with reference to FIGS. . First, when the system is started, the integrated control controller GC causes the process module controllers PC1 to P
Start monitoring the error signal from C4 (step SS
1), process module controllers PC1 to PC4
Alternatively, a failure occurs in any of the process modules PC1 to PC4, and the integrated controller GC causes the process module controllers PC1 to PC4 related to the failure.
When the error signal from is received, it is determined whether or not an instruction to execute the degenerate operation is given (step S2).

As a result, when the execution of the degenerate operation is not instructed, the processing of all process systems is suspended as in the conventional case (step S3). In this embodiment, it is also possible to operate the operation panel of the integrated controller GC to give a selection instruction to operate only the normal process system as it is without performing degenerate operation. In this case, the normal process system continues to process only the wafer to be processed by itself in accordance with the table L T as shown in FIG. 3 (step S3). on the other hand,
As a result of the above judgment, if the degeneration operation is instructed, based on the error signal and the contents of the table in FIG. 3, is the process system in which the fault has occurred processed the odd number of wafers? Is determined by the integrated control controller GC (step S4).

As a result, when a failure occurs in the system for processing odd-numbered wafers (that is, the system of PM1 and PM2), the schedule relating to the odd-numbered wafers of the wafer transfer table T is rewritten ( Step S
5), a system for processing even-numbered wafers (that is, PM
4 and PM3 system), the schedule for the even numbered wafers in the wafer transfer table T is rewritten (step S6).

This rewriting process is performed by the rewriting means of the integrated control controller GC. For example, as indicated by a mark X in FIGS. 3 and 5, during the process processing of the first (odd number) wafer. When a failure occurs, the schedule relating to the odd-numbered wafers after the relevant wafer in the wafer transfer table T is rewritten, as indicated by * in FIG. That is, the third wafer, the fifth wafer, the seventh wafer, and the ninth wafer are processed modules PM1 and PM2 during normal processing.
Is scheduled to be processed by the process system consisting of (see FIG. 3), but due to the failure of this process system, process modules PM4 and PM3 are processed.
It is rewritten to be processed by a normal process system consisting of.

After the table T is rewritten in this way, the integrated controller GC controls according to the contents of the table T (step S7). As a result, as shown in FIG. 5, the process modules PM4 and PM3 are
In the normal process system consisting of, the subsequent (third and subsequent) wafers are processed. Therefore, the processing is continued even for the wafer to be processed in the process system in which the failure has occurred, and the predetermined processing such as thin film formation is performed on the wafer.

In this degenerate operation process, since the number of process systems is reduced and the overlap of wafer transfer is reduced, the integrated controller GC waits for the third and subsequent wafers as shown in FIG. The time is adjusted, and control is performed so that what was processed by two paths is processed by one path. Therefore, even if a failure occurs in the process system, all the wafers can be processed without stopping the apparatus.

In the above embodiment, the integrated control controller GC detects the failure occurrence by the error signal from the controllers PC1 to PC4, but each controller PC1 to PC4 and each process module PC1 to PC.
4 may be directly monitored to detect the occurrence of a failure. Further, in the semiconductor manufacturing apparatus of the above-described embodiment, the cassette modules CM1 and CM2 for loading and unloading are respectively provided, but it is also possible to use one cassette module for both loading and unloading.

Further, in the present invention, the semiconductor manufacturing apparatus may have two or more process systems, and each process system may be composed of one or more process modules. Further, the present invention can be applied to a semiconductor manufacturing apparatus other than the cluster type. In short, the present invention can be applied to any semiconductor manufacturing apparatus that dispersively processes substrates to be processed in two or more process systems. can do.

[0023]

As described above, according to the fault handling system of the present invention, when a fault occurs in any of the process systems in a semiconductor manufacturing apparatus that disperses and processes substrates in a plurality of process systems. In addition, the integrated controller transfers the board to be processed in the failed process system to the remaining normal process system to continue processing, so that the predetermined processing of the board to be processed can be performed with a minimum delay. Therefore, the efficiency of semiconductor manufacturing can be improved as compared with the conventional case.

[Brief description of drawings]

FIG. 1 is a plan view showing a configuration example of a semiconductor manufacturing apparatus according to an embodiment of the present invention.

FIG. 2 is a configuration diagram showing a control system according to an embodiment of the present invention.

FIG. 3 is an explanatory diagram showing contents of a wafer transfer table at a normal time.

FIG. 4 is a time chart of processing when the semiconductor manufacturing apparatus is normal.

FIG. 5 is a time chart of processing when a failure occurs in the semiconductor manufacturing apparatus.

FIG. 6 is an explanatory diagram showing contents when a failure occurs in the wafer transfer table.

FIG. 7 is a flowchart of a coping process when a failure occurs in the semiconductor manufacturing apparatus.

[Explanation of symbols]

PM1, PM2, PM3, PM4 process module, CM1, CM2 cassette module, TM transport module, GC integrated control controller, PC1, PC2, PC3, PC4 process module controller, CC1, CC2 cassette module controller, TC transport module controller,

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masatoshi Kama 3-14-20 Higashi-Nakano, Nakano-ku, Tokyo Inside Kokusai Electric Inc.

Claims (1)

[Claims] 1. A substrate is transferred between modules by a carry-in module that accommodates a plurality of substrates to be processed, a process module that performs a predetermined process on the substrates, and a carry-out module that houses the processed substrates. In a semiconductor manufacturing apparatus connected via a transport module, a plurality of the process modules are provided, and the transport module disperses and transports the substrate from the carry-in module to each process module, and the substrate is transported by each of the plurality of process systems. An integrated controller that performs distributed processing and controls each module in a centralized manner detects a failure that occurred in one of the process systems and controls each module to control the board in the remaining process system excluding the system in which the failure occurred. A failure coping system for a semiconductor manufacturing apparatus, characterized by continuing processing.