JPH06302658A - Integrated circuit element - Google Patents

Abstract

PURPOSE:To detect the output enable state of an output terminal of a three-state signal externally by providing a monitor terminal for outputting an output enable signal for controlling the output of the three-stage signal to the outside. CONSTITUTION:The title element which is provided with an output terminal 3 for outputting one or a plurality of three-state signals 1 to the outside and controls the output of the three-state signal 1 to the output terminal 3 according to an output enable signal 2 has a monitor terminal 4 for outputting one or a plurality of output enable signals to the outside corresponding to each output enable signal 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit device, and more particularly to an integrated circuit device such as an LSI having a three-state output terminal.

[0002]

2. Description of the Related Art In recent years, computer devices in various fields have been miniaturized, and electronic circuits on a printed circuit board in these devices have been highly integrated and made into LSI.

If a collision of three-state outputs occurs during a hardware operation test of a circuit, such as a common bus, on which a plurality of signal lines capable of taking three-state states are connected, on this board. It has to be pursued which buffer or LSI is driving the signal. General-purpose three-state buffer IC (L
S244, etc.), the output state can be determined by hitting the state of the output enable signal with a logic probe or the like. However, in the case of an LSI that outputs three-state, which LSI has an adverse effect because the output enable signal is not output to the terminal. It is not possible to immediately determine whether or not it is affecting.

Conventionally, when it is considered that the LSI causes the collision of three-state output signals of a common bus such as a data bus, the terminal of the LSI which is considered to be the cause is removed from the board, and The cause was pursued one by one by examining the output state of the terminal.

Further, for hardware testing, LSI
A three-state control buffer is provided inside the LSI, and a floating terminal in which a plurality of three-state output enable signals are combined is provided in the LSI to create a floating state of the output terminal.
There is also a method of checking the output operation without removing I (Japanese Patent Laid-Open No. 3-225845).

Further, there is also a method in which a buffer such as LS244 is provided outside the LSI for a hardware test, and by controlling the enable signal terminal, a floating state is created without removing the terminal of the LSI to check the output operation. is there.

[0007]

In such a conventional technique, when checking each wiring of the common bus connected to the LSI at the time of the hardware test of the LSI, the It took time and labor to remove each terminal, and it took a lot of time and labor to check the operation.

Also, as in the above-mentioned Japanese Patent Laid-Open No. 3-225845, when the three-state buffer is provided inside or outside the LSI to check the operation without removing the LSI, the circuit scale inside the LSI is large. However, there is a problem in that a new circuit for operation check must be added.

The present invention has been made in consideration of the above circumstances, and in an integrated circuit element such as an LSI, a monitor terminal for outputting an output enable signal for controlling the output of a three-state signal is provided. The purpose of this is to confirm the output enable state of the output terminal of the three-state signal from the outside and to further reduce the labor in the operation test of the hardware of the printed circuit board.

[0010]

FIG. 1 shows a block diagram of the basic configuration of the present invention. In the figure, the present invention is
An integrated circuit device having an output terminal 3 for outputting one or a plurality of three-state signals 1 to the outside and controlling the output of the three-state signal 1 to the output terminal 3 by an output enable signal 2 The present invention provides an integrated circuit device characterized in that a monitor terminal 4 for outputting a plurality of output enable signals 2 to the outside is provided corresponding to each output enable signal 2.

Further, as shown in the basic block diagram of FIG. 2, an output terminal 3 for outputting the output enable signal 2 to the outside is provided, and the output enable signal 2 controls the output of the three-state signal 1 to the output terminal 3. In the integrated circuit element to be provided, a designation signal is provided which has one monitor terminal 4 for outputting the one or more output enable signals 2 to the outside, and designates only one output enable signal 2 to be output to the monitor element 4. And an output enable signal 2 for outputting a plurality of output enable signals 2. Of these output enable signals 2, only one output enable signal 2 specified by the specified signal is output to the monitor terminal 4. The selection means 6 may be provided.

Here, in FIG. 1, one output enable signal corresponds to one three-state signal 1, and the same number of monitor terminals as the output terminals 3 of the three-state signal 1 whose output enable state is to be confirmed. 4 is provided. In FIGS. 1 and 2, a three-state output buffer is normally used to control the output of the three-state signal 1 to the output terminal 3 by the output enable signal 2.

In FIG. 2, enable signal designating means 5
Is the output enable signal 2 that you want to output to the monitor terminal 4.
It is preferable to use a register that temporarily stores a value that specifies The selection means 6 is the enable signal designating means 5
It is a selector that selects the corresponding output enable signal 2 according to the signal output from, and is configured by a logic circuit such as an AND element or an OR element.

[0014]

In FIG. 1, the output enable signal 2 is directly output to the monitor terminal 4. Further, when the output enable signal 2 is in a state of enabling the output of the three-state signal 1, the three-state signal is output to the output terminal 3 as it is, and the output enable signal 2 makes the output of the three-state signal 1 disable. In the state, the output terminal 3 is in a high impedance state. Therefore, in the integrated circuit device, the output enable state of the output terminal 3 of the three-state signal 1 can be known by confirming the output of the monitor enable terminal 4 of the output enable signal 2 corresponding to the three-state signal 1.

In FIG. 2, enable signal designating means 5
And outputs a designation signal that designates one output enable signal. The selection means 6 outputs only the output of the output enable signal designated by this designation signal to only one monitor terminal 4. Therefore, in the integrated circuit element, since only the output enable signal corresponding to the three-state signal 1 to be confirmed is selected and connected to the monitor terminal 4, the output of the plurality of output enable signals can be confirmed by one monitor terminal. Further, even if the number of output enable signals to be checked is large, it is not necessary to provide monitor terminals for the number of output enable signals, and the number of output terminals can be reduced.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the embodiments shown in the drawings. The present invention is not limited to this. FIG. 3 shows a first embodiment of the present invention.
FIG. 3 is a diagram showing only a portion that outputs a three-state signal inside the LSI 20 to the outside of the LSI. Although not shown in the figure, in addition to this, in addition to this, there is a circuit block that realizes the LSI function.

In the figure, reference numeral 11 designates three-step data transmission.
Signal (S₁, S₂…… S_n) Output data
Data generator, 12 is the three-state signal (S₁, S₂…
... S _n) Output enable signal (e₁,
e₂...... e_n) Is output from the output enable control section.
It Also, b₁, b₂...... b_nIs the output enable signal
(E₁, e₂...... e_n) Corresponding to each three
State signal (S₁, S₂…… S_n) Output terminal (a₁, a
₂...... a_n) To open and close the output to
It is fa. m₁, m₂…… m_nAre the features of this invention.
Monitor terminal, and the output enable signal e₁, e₂
...... e_nIs output as it is to the outside of the LSI 20.
is there.

In the figure, for example, when the output enable signal e ₁ is at the low level, the three-state buffer b ₁ is opened and the data generated by the output data generator 11 is output as the three-state signal S ₁ at the output terminal a.
Output to ₁ .

Further, the output enable signal e ₁ is High.
When it is at the level, the three-state buffer b ₁ closes the output, and the output terminal a ₁ is in a high impedance state and no data is output. Also, the output enable signal e
Whether ₁ takes the value of Low or High,
The output enable signal e ₁ is directly output from the monitor terminal m ₁ .

FIG. 4 shows a second embodiment of the present invention. This figure also shows only the portion of the LSI 20 that outputs a three-state signal to the outside of the LSI.

In the figure, 15 is a monitor terminal,
Only one is provided. Reference numeral 13 is a register in which setting data designating an output enable signal for a three-state signal whose output state is desired to be written is temporarily stored. WR is a write control signal. 14 is
Monitor terminal 1 according to the signal output from register 13
5 is a selector for selecting an output enable signal to be output to the output terminal 5.

In FIG. 4, for example, in order to know the output state of the three-state signal S ₂ , it is assumed that the setting data designating the output enable signal e ₂ is input to the register 13. At this time, the register 13 outputs a signal designating the output enable signal e ₂ to the selector 14.
Based on this designation signal, the selector 14 selects only the output enable signal e ₂ and connects it to the monitor terminal 15.

FIG. 5 shows an example of a circuit of the selector section which realizes the above functions. In the figure, the register 13 is
It consists of D flip-flops 131, 132, 133,
The setting data D ₁ , D ₂ , D _n and WR are input. However, in this example, only one of the setting data D ₁ , D ₂ , and D _n is set to the high level. Also,
The selector 14 is composed of a logical circuit of AND elements 141, 142, 143 and an OR element 144.

For example, in order to know the output state of the three-state signal S ₂ , when only the setting data D ₂ is input at the high level, the selector 14 outputs the output enable signal e ₂ through the AND element 142 only to the monitor terminal 15. Is output to.

As described above, in general, when it is desired to know the output state of the three-state signal S _n , by setting only the setting data D _n designating the output enable signal e _n corresponding to the three-state signal, it is possible to output the output enable signal e _n to the monitor terminal 15.

FIG. 6 is a block diagram of a printed circuit board according to an embodiment of the present invention. In the figure, MPU3
Reference numeral 0 controls the operation of the entire printed circuit board including the LSIs 1, 2, and 3. A and B are common bus signal lines for three-state control, and show an example in which the output from each LSI is an input signal of the MPU. Where 1-A, 1-
B, 2-A, 2-B, 3-A and 3-B are monitor terminals that output an output enable signal for the three-state signal in each LSI.

The signal lines A and B are connected to the LSI1, LSI2 and LSI3, and are normally in a high impedance state, or the three-state signal of any one of the LSI1, LSI2 and LSI3 is at a high level or It is in the state of outputting the Low level.

Next, FIG. 7 shows an investigation flow for detecting where an inconvenient part is when a collision of three-state outputs occurs in a hardware test of a printed circuit board.

When a hardware operation test detects that a bus collision of three-state output occurs on a bus signal line (step S1), first, the connection destination of the signal of the bus in which the collision occurs. Where is is extracted on the circuit diagram (step S2).

Next, it is determined whether the connection destination is a general-purpose three-state control buffer such as the LSI 25 or the LSI (step S3), and if it is the three-state control buffer, the terminal of the output enable signal thereof. The output state of is checked (step S4).

When the connection destination is an LSI, a monitor terminal (1-A, 1 for outputting an output enable signal of the LSI)
The output state of -B, 2-A, 2-B, 3-A or 3-B) is checked (step S5).

As a result of the above check, it is determined whether or not some outputs are enabled (step S6). If the monitor terminal is enabled, the three-state signal corresponding to the output enable signal is output. Since it has been output, appropriate processing is performed as necessary (step S7). For example, when it is found that a plurality of three-state signals are being output at the same time, a process of masking any one of the colliding three-state signals is performed.

As described above, by checking the output state of the monitor terminal, the hardware operation test can be performed without removing the LSI and without providing an additional circuit for the test.

Further, when a collision of three-state signals occurs, it is possible to easily find the collision point and reduce the labor in the operation test of the hardware of the printed circuit board.

[0035]

According to the present invention, since the monitor terminal for outputting the output enable signal to the outside is provided in the integrated circuit element, the output enable state of the output terminal of the three-state signal can be known from the outside, and the printed circuit board is further provided. It is possible to reduce the trouble in the hardware operation test.

Further, when only one monitor terminal is provided and only the output of the designated output enable signal of the plurality of output enable signals is output to this monitor terminal, the number of output enable signals to be checked is Even if the number is large, it is not necessary to provide monitor terminals for the number of output enable signals, and the number of output terminals can be reduced.

[Brief description of drawings]

FIG. 1 is a basic configuration block diagram relating to claim 1 of the present invention.

FIG. 2 is a basic configuration block diagram relating to claim 2 of the present invention.

FIG. 3 is a configuration diagram in the first embodiment of the present invention.

FIG. 4 is a configuration diagram of a second embodiment of the present invention.

FIG. 5 is a circuit diagram of a selector section in the second embodiment of the present invention.

FIG. 6 is a configuration diagram of a printed circuit board that is an embodiment of the present invention.

FIG. 7 is an investigation flow when a collision of three-state outputs of the present invention occurs.

[Explanation of symbols]

 1 three-state signal 2 output enable signal 3 output terminal 4 monitor terminal 5 enable signal designating means 6 selecting means 11 output data generation section 12 output enable control section 13 register 14 selector 15 monitor terminal 20 LSI

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical indication H03K 19/0175

Claims (2)

[Claims] 1. An output terminal (3) for outputting one or a plurality of three-state signals (1) to the outside, the three-state signal (1) according to an output enable signal (2).
In the integrated circuit device for controlling the output to the output terminal (3), the monitor terminal (4) for outputting the above-mentioned one or more output enable signals (2) to each output enable signal (2). An integrated circuit device characterized by being provided correspondingly. 2. An output terminal (3) for outputting one or a plurality of three-state signals (1) to the outside, and a three-state signal (1) according to an output enable signal (2).
In the integrated circuit device for controlling the output to the output terminal (3), one monitor terminal (4) for outputting the above-mentioned one or more output enable signals (2) to the outside,
An enable signal designating means (5) for outputting a designating signal for designating only one output enable signal (2) to be outputted to the monitor element (4) and a plurality of output enable signals (2) are inputted, and these outputs are outputted. Enable signal (2)
An integrated circuit element comprising selection means (6) for outputting only one output enable signal (2) designated by the designation signal to the monitor terminal (4).