JPH06302199A - Memory test circuit device - Google Patents

Abstract

PURPOSE:To provide a memory test circuit device with high test efficiency and suitable for high integration. CONSTITUTION:In the memory test circuit device of a scanning system, a register connected to the terminal of a memory is constituted of a scanning flip-flop having a scanning chain shifting the data in order of an address register 4, an input data register 3, an output data register 10. Then, the time required for the tests of write and read and the size of a test pattern are reduced remarkably by discriminating whether the input data and the read data of the memory are in the relation of the complement of one or not by a comparator 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory test circuit device having a high test efficiency suitable for an integrated circuit.

[0002]

2. Description of the Related Art FIG. 11 shows a scan type memory test circuit device proposed by the present inventor. In FIG. 11, 67,74
Is an address register, 66, 73 is an input data register, 71,
78 is an output data register, 69,76 are memories, 68,70,72,7
5, 77 are multiplexers, and 79, 80 are control circuits. FIG. 7 is a write operation timing chart of the circuit device of FIG. 11, and FIG. 8 is FIG.
FIG. 6 is a timing chart of a read operation of the circuit device of FIG.

In FIG. 11, in the test mode, the input data register 66, the address register 67 and the output data register 71 operate as a shift register, and the data of the SCAN_IN terminal is input bit by bit via the multiplexer 68. Are stored in the address register 67. With the address register 67 and the data register 66 determined by the above procedure, one word can be written in the RAM 69 by enabling the write control signal TEST_WE.
Next, the SCAN_CTL signal is validated and the data of the SCAN_IN terminal is stored in the address register by the shift operation. At this time, the input data register holds the previous value. In this state, enable the write control signal TEST_WE
You can write the word. After the second word, data is sequentially written by repeating the setting of the address register for the number of words to be written and enabling the write control signal TEST_WE until the data is updated. FIG. 7 shows the RAM write operation timing in this test mode. FIG. 7 shows the timing of the write operation of the 0th address, the 2nd address, the 4th address, the 6th address, the 8th address, the 10th address and the 12th address of a RAM having 3 bits of data and 2 bits of address. It can be seen that writing 1 word requires 5 clocks for the first word and 2 clocks for the second word and thereafter.

Similarly, in the test mode, the data of the SCAN_IN terminal is stored in the address register 67 via the multiplexer 68 bit by bit. When the address register 67 is fixed, the output data of RAM69 is fetched into the output data register 71, and the output data register 71 operates as a shift register, so that the output data is output to the SCAN_OUT pin via the multiplexer 72 bit by bit. It is possible to read one word. FIG. 8 shows the timing of the RAM read operation in the test mode. FIG. 8 shows the read operation timing of the 0th address, the 1st address, the 2nd address, the 3rd address and the 4th address of the RAM of 3 bits of data and 2 bits of address. 1
It can be seen that it takes 3 clocks to read the word. By switching between the multiplexers 68 and 75, the multiplexers 70 and 77, and the multiplexer 72, either the RAM 69 or the RAM 76 is selected and the writing and reading tests are sequentially performed.

[0005]

[Problems to be Solved by the Invention]
Since the RAM test circuit device controls or observes the states of the RAM address register, input data register, and output data register for each word in a scan operation, there is a problem that the test takes a long time and the test pattern becomes huge. It was

It is an object of the present invention to provide a RAM test circuit device suitable for an integrated circuit, which has a short test time and a short test pattern while suppressing an increase in circuit scale and facilitates failure diagnosis of RAM.

[0007]

A RAM test circuit device according to the present invention is a memory test circuit device, wherein the memory has an input data register, an output data register, and an address register. The register and the address register are composed of scan flip-flops, and the scan flip-flop has a scan chain for shifting data in the order of address register, input data register, output data register,
Control circuit that holds the data in the input data register during the scan operation depending on the state of test terminal 1, control circuit that holds the data in the address register during the scan operation depending on the state of test terminal 2, and inputs the input data signal and output data signal of the memory And a selector for storing the output signal of the comparison circuit in the output data register.

The RAM test circuit device of the present invention is a memory test circuit device, wherein the memory has an input data register, an output data register and an address register, and the input data register, the output data register and the address register of the memory are scanned. The scan flip-flop includes a scan chain that shifts data in the order of an address register, an input data register, and an output data register, a memory output data holding circuit, a memory input data signal, and the holding circuit. And a selector that stores the output signal of the comparison circuit in the output data register.

[0009]

According to the present invention, in the write operation of the RAM test mode, the data of the same address is read before the write operation and the read data is compared with the write data of the input data register in the write operation of the RAM test mode. At this time, the read data is compressed by utilizing the fact that the read data and the write data have a one's complement relationship. By the above operation, the write and read tests are simultaneously executed in parallel to reduce the time and test pattern required for the RAM test.

[0010]

FIG. 1 is a block diagram showing an embodiment of a RAM test circuit device according to the present invention.
The circuit diagram of FIG. 2, the circuit diagram of FIG. 2, the circuit diagram of FIG. 4, the circuit diagram of FIG. 6, the operation explanatory diagram of FIG. 9, and the operation explanatory diagram of FIG.

The RAM test circuit device of the present invention is basically the same as a general scan type RAM test circuit device, but as shown in the RAM test circuit device of FIG. And output data register 1
0, 11 and an address register 4, the input data register 3 of the memory, the output data register 10, 11 and the address register 4 are composed of scan flip-flops, and the scan flip-flops are address registers, input data registers, output data. It has a scan chain that shifts data in the order of registers, and test terminal 1
The control circuit 1 holds the data of the input data register during the scan operation depending on the state of the control terminal, the control circuit 2 holds the data of the address register during the scan operation depending on the state of the test terminal 2, the input data signal and the output data signal of the memory are input. The comparison circuit 6 differs from the conventional one in that the comparison circuit 6 and the selector 9 for storing the output signal of the comparison circuit in the output data register are provided.

Further, the RAM test circuit device of the present invention is the same as a general scan type RAM test circuit device in its basic part, but as shown in the RAM test circuit device of FIG. It has a register 24, output data registers 32 and 33, and an address register 25, and the input data register, output data register, and address register of the memory are constituted by scan flip-flops, and the scan flip-flops are address registers, input data registers, The output data register has a scan chain that shifts data in order, and a holding circuit 27 for holding the output data of the memory, a comparator circuit 28 for receiving the input data signal of the memory and the output signal of the holding circuit, and an output signal of the comparing circuit. Of the prior art in that it has a selector 31 for storing The different.

By the way, the conventional scan type RA shown in FIG.
M test circuit device, SCAN_IN
The terminal data is stored in the address register and the input data register by the shift operation. The input data register holds the previous value by enabling the SCAN_CTL signal when the input data register is fixed. Write control signal with address register and input data register confirmed
One word can be written by enabling TEST_WE. Next, the data of the SCAN_IN terminal is stored in the address register by the shift operation. In this state, the second word can be written by enabling the write control signal TEST_WE. After the second word, data is sequentially written by repeating the setting of the address register for the number of words to be written and enabling the write control signal TEST_WE until the data is updated. In order to write all the words of RAM, it is necessary to repeat the above operation for the number of words. During the RAM read test, the data of the SCAN_IN pin is stored in the address register by the shift operation. When the state of the address register is fixed, the RAM data is fetched to the output data register by the normal operation, and the data of the output data register is output to the SCAN_OUT pin by the shift operation. In order to read all the words in RAM, it is necessary to repeat the above operation for the number of words. Therefore, there is a problem that the time required for testing the RAM is long and the test pattern becomes huge. , The number of clocks for writing one word is the sum of the number of bits of the address register and the number of bits of the input data register, while the number of clocks for reading one word is the number of bits of the address register. And the larger number of bits in the output data register.

By the way, checker boats and marching are examples of physical patterns of RAM test patterns. The test method is shown using a 4-bit 8-word RAM as an example. The conventional method of the checker boat test is shown below.

Focusing on the checkerboard pattern,
Patterns can be classified into two types, "0 1 0 1" and "1 0 1 0". In a general method, this pattern is written alternately in the RAM address order during the write test. In contrast,
The checker boat pattern patterns are "0 1 0 1" and "1.
Focusing on the fact that there are two types of 0 1 0 ", the following method for shortening the write cycle has been devised.

1) Writing a checker boat pattern 2) Reading the checker boat pattern 3) Writing the inverted checker boat pattern 4) Readout of checkerboard pattern A conventional method of marching test is shown below.

[0017] Therefore, in the 4-bit 8-word RAM, in the checkerboard pattern, the data update in the write test may be performed in units of 4 words instead of in units of 1 word. Further, in the marching pattern, the data may be updated in the writing test not in units of one word but in units of eight words. That is, in the checkerboard pattern, the data update in the write test may be performed in (word number / 2) units, and in the marching pattern, the data update in the write test may be performed in word number units.

Here, regarding both the checkerboard and the marching, focusing on the pattern of writing the same address and the pattern before writing, it can be understood that there is a one's complement relationship. Somehow, if you can run read tests concurrently during write tests,
The time required for the test and the test pattern can be significantly reduced, and the present invention focuses on this point.

In the circuit of the present invention shown in FIG. 1, the data of the SCAN_IN terminal is stored in the address register and the input data register by the shift operation during the RAM write test. The input data register holds the previous value by enabling the SCAN_CTL1 signal when the input data register is fixed.
In addition, by enabling the SCAN_CTL2 signal for one clock only after the address register and the input data register are fixed, the address register holds the previous value for the next one clock.

On the other hand, the write data of the input data register and the read data from the RAM are input to the comparator, and this read data is the data before the writing at the same address as the writing. The output of the comparator is SCAN
Since the _CTL2 signal is valid, it is connected to the output register 11 via the multiplexer 9 and stored in the output register 11 at the next clock. The output register 11 is connected to the external terminal SCAN_OUT via the multiplexer 9. At this time, note that there is a one's complement relationship between the read data and the write data. The comparator determines whether or not the above-described one's complement relationship holds. If it is confirmed in advance that the data can be normally set in the input data register by the scan operation, it is possible to determine whether the read data is normal by observing the output of the comparator at the external terminal SCAN_OUT. You can do it. That is,
This means that the read data is compressed to 1 bit.

Next, the SCAN_CTL2 signal is invalidated and the write control signal TWE is validated to write the first word data. From the second word onward, until the data is updated, the setting of the address register is repeated for the number of words to be written, and the data is sequentially written in the same procedure as the writing operation of the first word. Through the above operation, reading can be simultaneously executed in parallel during the writing operation.

In the circuit of the present invention shown in FIG. 2, the RAM uses the Read Modified Write type which performs reading and writing in one clock. First, at the write test of RAM, the data of the SCAN_IN terminal is stored in the address register and the input data register by the shift operation. Enable the SCAN_CTL signal for one clock only after the address register and input data register are fixed. On the other hand, data is read in the first half of this one clock and written in the latter half. In the first half of the clock, the read data is held by the data holding circuit 27 for one clock. The comparator 28 has an input data register 24
Write data and read data of the data holding circuit 27 are input, and this read data is data before writing at the same address as writing. Since the SCAN_CTL signal is valid, the output of the comparator is connected to the output register 33 via the multiplexer 31 and stored in the output register 33 at the next clock. The output register 33 is connected to the external terminal SCAN_OUT via the multiplexer 34. At this time, between read data and write data
Note that there is a one's complement relationship. The comparator determines whether or not the above-described one's complement relationship holds. If it is confirmed in advance that the data can be normally set in the input data register by the scan operation, it is possible to determine whether the read data is normal by observing the output of the comparator at the external terminal SCAN_OUT. You can do it. That is, the read data is compressed to 1 bit.

Next, the SCAN_CTL signal is invalidated and the write control signal TWE is validated to write the first word data. From the second word onward, until the data is updated, the setting of the address register is repeated for the number of words to be written, and the data is sequentially written in the same procedure as the writing operation of the first word. The number of clocks for write operation can be shortened by 1 clock per write cycle with respect to the circuit of FIG.

FIG. 4 shows an address data holding circuit. FIG. 6 shows a SCAN data switching control circuit of the output data register.

In FIG. 4, when the SCAN_CTL2 signal is "L", it is logically equivalent to the conventional circuit of FIG. When the SCAN_CTL2 signal becomes "H" during the scan operation, each scan flip-flop takes in the state of its output, and as a result, the scan flip-flop holds the previous value.

In FIG. 6, when the SCAN_CTL2 signal is "L", it is logically equivalent to the conventional circuit of FIG. When the SCAN_CTL2 signal becomes "H" during the scan operation, the scan-in terminal of the flip-flop 65 of the output data register is connected to the output of the comparator.

FIG. 9 shows the operation timing at the time of writing of the circuit of the present invention shown in FIG. FIG. 9 shows addresses 0, 2, 4, 6 of a 3-bit data, 2-bit address RAM,
This is the timing of the write operation at address 8. Only the first word requires 5 clocks, but it can be seen that 3 bits are sufficient for the second and subsequent words. RAM with 5 bits of data and 3 bits of address
In the checkerboard pattern, the number of clocks required for the write test in the conventional circuit is ((3 + 5) x1 + 3
x3) x2 = 34 clocks. The number of clocks required for the read test is 5x8 = 40 clocks. The total number of clocks for reading and writing is 74.

In the circuit of the present invention shown in FIG. 1, reading and writing are performed simultaneously, and the number of clocks becomes (5+ (3 + 1) x3) x2 = 34, which is a 54% reduction in the number of clocks. In the marching pattern, the number of clocks required for the write test in the conventional circuit is (3 + 5) x1 + 3x7 = 29 clocks. The number of clocks required for the read test is 5x8 = 40 clocks. The total number of clocks for reading and writing is 69. In the circuit of the present invention, reading and writing are simultaneously performed, and the number of clocks is 5+ (3 + 1) x7 = 33, which is a 52% reduction in the number of clocks. Generally, the larger the value of (bit length of data / bit length of address), the greater the reduction rate.

FIG. 10 shows the operation timing at the time of writing of the circuit of the present invention shown in FIG. Figure 10 shows 0, 2, 4, and 6 of RAM with 3 bits of data and 2 bits of address.
It is the timing of the write operation at addresses 8 and 10. 1
It takes 5 clocks only for the second word, but it is clear that 2 bits are enough for the second word and thereafter. In the checkerboard pattern, the number of clocks for reading and writing in the conventional circuit is 74 for the RAM of 5 bits of data and 3 bits of address.

In the circuit of the present invention, reading and writing are simultaneously performed, and the number of clocks is (5 + 3x3) x2 = 28, which is 62%.
The number of clocks will be reduced. In the marching pattern, the number of clocks for reading and writing in the conventional circuit is 69. In the circuit of the present invention in FIG. 1, reading and writing are simultaneously performed, and the number of clocks is 5 + 3x7 = 26, which is a 62% reduction in the number of clocks. Generally, the larger the value of (bit length of data / bit length of address), the greater the reduction rate.

A method and operation of further shortening the address setting of the address register in the circuit of the present invention shown in FIGS. 1 and 2 will be described. Assuming that the address register has 3 bits, it is said that it takes 3 bits from SCAN_IN to set one address. However, the number of bits required for setting can be reduced by rearranging the order of address setting.
In general, there is a method using a linear feedback shift register as a method for obtaining all patterns by bit-shifting a register having an arbitrary bit length. According to this method, for a register having a bit length n, all patterns can be created by bit shift of n ** 2. If you use this method to set the address register,
Setting one address only requires a 1-bit shift from SCAN_IN. Therefore, the reduction rate of the number of clocks can be further increased.

By the way, the present embodiment shown in FIG.
Compared with the data holding circuit of the input data register,
Although the address holding circuit of the address register, the comparator and the multiplexer are required, the above circuits can be constructed by a very small scale circuit. Further, the SCAN_CTL1 terminal and the SCAN_CTL2 terminal can be shared with a normal external terminal, and it is not necessary to add an external terminal for testing. In addition, SCAN_CTL1 pin and S
It goes without saying that the address and data combinations can be set arbitrarily by disabling the CAN_CTL2 pin. Therefore, the combination of the address and the data is not limited by the circuit of the present invention, and the failure diagnosis of the RAM can be easily performed.

Further, the present embodiment of FIG. 2 requires a data holding circuit for read data, a comparator and a multiplexer, as compared with the conventional FIG. 11, but the above circuit can be constructed by an extremely small scale circuit. . Also, the SCAN_CTL terminal can be shared with a normal external terminal, and it is not necessary to add an external terminal for testing. Furthermore, it goes without saying that the address and data combination can be set arbitrarily by disabling the SCAN_CTL terminal. Therefore, the combination of the address and the data is not limited by the circuit of the present invention, and the failure diagnosis of the RAM can be easily performed.

Further, as shown in FIGS. 1 and 2, two or more SRAs are used.
A common scan control signal can be used for M to perform write tests in parallel at the same time.

[0035]

According to the RAM test circuit device of the present invention,
The test time of the scan type RAM test circuit device and the size of the test pattern can be significantly reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a RAM test circuit device of the present invention.

FIG. 2 is a circuit diagram of a RAM test circuit device of the present invention.

FIG. 3 is a circuit diagram of a conventional address register.

FIG. 4 is a circuit diagram of an address register of the present invention.

FIG. 5 is a circuit diagram of a conventional output data register.

FIG. 6 is a circuit diagram of an output data register of the present invention.

FIG. 7 is an operation explanatory diagram of a conventional RAM test circuit device at the time of writing.

FIG. 8 is an operation explanatory diagram of a conventional RAM test circuit device at the time of reading.

9 is an explanatory diagram of a write operation of the RAM test circuit device of FIG. 1 of the present invention.

10 is a diagram illustrating a write operation of the RAM test circuit device of FIG. 2 of the present invention.

FIG. 11 is a circuit diagram of a RAM test circuit device previously proposed by the present inventor.

[Explanation of symbols]

 6,18 Comparison circuit 27,38 Data holding circuit

Claims (2)

[Claims] 1. A test circuit device for a memory, wherein the memory has an input data register, an output data register and an address register, and the input data register, the output data register and the address register of the memory are composed of scan flip-flops. The scan flip-flop has a scan chain that shifts data in the order of an address register, an input data register, and an output data register, and a control circuit and a test terminal that hold the data of the input data register during a scan operation depending on the state of test terminal 1.
It is provided with a control circuit that holds the data of the address register during the scan operation depending on the state of 2, a comparison circuit that inputs the memory input data signal and the output data signal, and a selector that stores the output signal of the comparison circuit in the output data register. Scan type memory test circuit device. 2. A test circuit device for a memory, wherein the memory has an input data register, an output data register and an address register, and the input data register, the output data register and the address register of the memory are constituted by scan flip-flops. The scan flip-flop has a scan chain that shifts data in the order of an address register, an input data register, and an output data register, and receives a memory output data holding circuit, a memory input data signal, and the holding circuit output signal as an input. A scan type memory test circuit device comprising a comparison circuit and a selector for storing an output signal of the comparison circuit in an output data register.