JPH06301571A - Cpu mounted integrated circuit chip and emulator pod - Google Patents

Abstract

PURPOSE:To improve the emulation efficiency by outputting a memory access manifesting signal and an I/O access manifesting signal to the outside of the CPU mounted integrated circuit chip. CONSTITUTION:At the time of emultaion mode, an access from an in-chip bus 30 of an internal memory 14 is inhibited uniformly. An internal resources access manifesting circuit 36 generates an internal address manisfesting signal for showing a fact that one of the internal memories 14 is subjected to address designation, in accordance with an access selecting signal outputted from an address decoder part 34. Also, in accordance with a prescribed bus use permitting signal for showing a fact that a DMA controller 16 obtains a bus use permission, an internal access I/O access manifesting signal for showing a fact that one of internal I/O circuit 18 is subjected to address designation or becomes an access object of the DMA controller is generated. In accordance with these two signals, an input and an output of data can be controlled correctly even at the time of DMA.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a CPU (central proc
essing unit) and an internal memory and an internal I / O circuit which are accessed by the CPU via a predetermined in-chip bus, and the internal memory is accessed via the in-chip bus without passing through the CPU. Memory and internal I / O
Direct access to the circuit DMA (direct
memory access) CPU with controller
On-board integrated circuit chip (hereinafter, such CPU and DM
A mounted with an A controller together is referred to as a CPU mounted integrated circuit chip), or such a CPU
On-board integrated circuit chip is mounted, in order to debug the target system using the one corresponding to the chip,
The present invention relates to an emulator pod used when emulating a device corresponding to the chip connected to an external bus in the target system, and in particular, it can emulate the operation of the DMA controller more effectively.
The present invention relates to a PU-equipped integrated circuit chip and an emulator pod.

[0002]

2. Description of the Related Art Integrating an electronic device into an integrated circuit has many advantages such as improving the reliability of the electronic device and reducing power consumption, as well as reducing the size of the entire electronic device. There is. When designing an integrated circuit, an extremely large number of design steps are required. Therefore, the ratio of the design cost is extremely high, and the TAT (turn around time) becomes long. Therefore, it is difficult to customize. There is. In order to solve the problems (1) to (3) of customizing the integrated circuit, there is a technique in which at least a part of the design process or the manufacturing process is shared and prepared in advance, and the other processes are customized.

An integrated circuit based on such a technique is called a semi-custom type integrated circuit, and includes a standard cell type integrated circuit and a gate array type integrated circuit.
The standard cell type integrated circuit is an integrated circuit based on a design method in which registered cells (functional blocks) are arranged according to a circuit to be incorporated in the integrated circuit and interconnected. In the gate array type integrated circuit, a group of cells arranged in a matrix which is processed before the wiring process is shared,
This is an integrated circuit of a type in which subsequent wiring steps are performed according to a circuit incorporated in the integrated circuit. According to such a semi-custom type integrated circuit, it is possible to reduce TAT and cost at the time of designing and manufacturing, and it is possible to provide an integrated circuit designed according to the customer.

In recent years, in such a semi-custom type integrated circuit, a CPU (central processing unit) is used.
t: central processing unit) or R accessed by the CPU
AM (random access memory) and ROM (read only me)
For example, some macro libraries of peripheral circuits such as I / O (input / output) are provided. According to the semi-custom type integrated circuit in which such a macro library is prepared, an integrated circuit (hereinafter referred to as a CPU-incorporated custom integrated circuit) incorporating a microcomputer system having a customized configuration including a CPU is also available. It is possible to provide.

Various techniques have conventionally been disclosed and used for emulating a system using a microprocessor, including such a CPU-incorporated custom integrated circuit.

FIG. 11 is a block diagram showing the configuration of a first example of a conventional emulator.

The emulator shown in FIG. 11 emulates the CPU-installed custom integrated circuit. In addition, the emulator includes the CP that is mounted on the user target system and is an emulation target.
It is used by connecting it to a mounting position of a U-mounted custom integrated circuit (hereinafter also referred to as a target integrated circuit) or a predetermined connecting position in the vicinity thereof with an emulator connecting plug 90. For example, the emulator connection plug 90 is mounted and used in an integrated circuit socket in which the target integrated circuit on the user target system is mounted. The emulator is mainly used for ICE (in circuit emulato).
r) Main body 80, pod 92, breadboard 94
And an emulator connection plug 90.

In the breadboard 94, the circuit incorporated in the target integrated circuit to be emulated is composed of a discrete circuit. For example, a CPU chip 60, an I / O chip 62, a ROM chip 64, a RAM chip 66, etc. are mounted on the breadboard 94, and a circuit incorporated in the target integrated circuit is reproduced. In addition, with respect to such a bullet board 94, the CP mounted on the bread board 94 by the ICE main body 80 and the pod 92.
It can be said that the emulator of the U chip 60 is configured.

The pod 92 has the same specifications as the CPU chip 60 to be emulated. Further, the CPU mounted on the pod 92
The operating state of the ICE can be observed on the ICE main body 80. During the emulation, the CPU mounted on the pod 92 operates, and the operation of the breadboard 94 can be confirmed by observing the operation of the CPU on the ICE main body 80.

According to the emulator as shown in FIG. 11, the circuit is realized by the bullet board 94 even before the target integrated circuit is made, and the circuit is incorporated in the target integrated circuit. Can emulate. Further, since the circuit incorporated in the target integrated circuit is a discrete circuit, the logic state of each wiring can be easily observed.
For example, the logical state of the bus used when the CPU chip 60 accesses another RAM chip 66 or the like can be relatively easily observed.

FIG. 12 is a block diagram showing the configuration of a second example of the conventional emulator.

In the emulator shown in FIG. 12, the target integrated circuit of the user target system, for example, the target integrated circuit is mounted on the emulator connecting plug 90, as in the emulator of the first example described with reference to FIG. And is used as an emulator for the target integrated circuit. The emulator mainly includes an ICE body 80, a pod 76,
It is composed of an emulator connection plug 90.

In the pod 76, the user end chip 70 of the target integrated circuit having the same or the same form as that mounted on the user target system is provided.
Is installed. In addition, the pod 76 has a circuit for connecting the user end chip 70 to the user target system through the emulator connection plug 90 and uses the circuit for operating the user end chip 70.
An ICE circuit 74 for observing the E body 80 is incorporated. The user end chip 70 includes, for example, a CPU section 82, an I / O section 84, and a ROM.
The unit 86 is incorporated and connected by the internal bus 72.

According to the second example of the conventional emulator shown in FIG. 12, the final user end chip 70 (the target integrated circuit) is actually mounted in the user target system and operated. State
It can be reproduced more accurately and emulated. Therefore, the emulation accuracy in the final state of the hardware configuration of the user target system can be improved.

FIG. 13 is a block diagram showing the configuration of an emulator pod used in the third example of the conventional emulator.

FIG. 13 shows the configuration of an emulator pod used between a predetermined ICE main body and a predetermined target system. The target system is mounted with an integrated circuit having a CPU and its peripheral circuits incorporated therein and having a customized circuit portion.

The emulator pod is mainly composed of a CP.
U-mounted chip 10, EVA chip 44, emulation memory 46, internal bidirectional data bus buffer 4
8, an emulator circuit 74, and an internal bus 50 connecting them.

Further, it is connected to the ICE main body through the emulator circuit 74. On the other hand, the target system is connected via the internal bidirectional data bus buffer 48.

The CPU mounting chip 10 corresponds to an integrated circuit to be emulated, which is mounted on the target system. The CPU mounted chip 10
Is equipped with a CPU and a memory accessed by the CPU via a predetermined in-chip bus. Further, the CPU mounting chip 10 is mounted with a DMA controller capable of directly accessing the memory via the in-chip bus without going through the CPU.
After the test by emulation or the like is completed, the CPU-equipped chip 10 is finally connected to the target system connection point, which is connected from the internal bidirectional data bus buffer 48 with a predetermined emulator connection plug, It is installed directly.

The EVA chip 44 is used to emulate the CPU mounted chip 10.
This is a chip on which the same CPU as the CPU mounted on the CPU mounting chip 10 is mounted.

The emulation memory 46 stores the C data during emulation of the CPU-equipped chip 10.
It emulates a memory built in the PU mounted chip 10. By emulating the built-in memory with the emulation memory 46, it is possible to more easily refer to or change the setting of the memory data being emulated. This is the CPU
This is because the emulation memory 46 is externally attached and is relatively easy to access as compared with the memory built in the mounting chip 10.

Further, the emulation memory 46 stores the C data during emulation of the CPU-equipped chip 10.
The ROM built in the PU mounted chip 10 is also emulated.

A target system using the CPU-mounted chip 10 often does not include an external storage device such as a hard disk device for storing application programs and the like. When the external storage device is not provided, not only the basic software but also the application program is stored in the ROM on the target system. In addition, for convenience of integration degree and the like, generally, the application program including the basic software is stored in the ROM in the CPU mounting chip 10.

By the user's operation on the ICE body,
By emulating the ROM in the CPU mounted chip 10 by the emulation memory 46, which is a RAM whose contents can be changed relatively easily, I
It is possible to achieve various conveniences for CE users. For example, when the application program as described above is debugged, a program defect confirmed can be dealt with immediately and relatively easily by changing the data in the emulation memory 46. In addition, it is possible to immediately continue debugging with the program modified by such data change.

The internal bidirectional data bus buffer 48
Is used when connecting the internal bus 50 and the final mounting position of the CPU mounting chip 10 of the target system. The internal bidirectional data bus buffer 48
And a predetermined emulator connection plug and a predetermined connection cable related thereto.

The emulator circuit 74 incorporates a circuit for connecting the ICE body 80 and the emulator pod. With a predetermined cable connected to the emulator circuit 74 and the ICE main body, the operating state of the CPU-mounted chip 10 can be operated and the operating state can be observed.

According to the third example of such a conventional emulator, as in the case of the second example, the state in which the CPU-equipped chip 10 is actually mounted in the target system and operated is more accurate. It can be reproduced and emulated. Therefore, it is possible to emulate in a state closer to the final state of the hardware configuration of the target system, and improve the emulation accuracy. Further, according to the third example, the operation of the CPU-equipped chip 10 is operated during the emulation,
The memory accessed to observe the operation is the emulation memory 46 outside the CPU-equipped chip 10, so that more precise access can be performed as compared with the second example. Therefore, this third
According to the example, the emulation work efficiency can be further improved as compared with the second example.

The integrated circuit to be emulated in the third example is equipped with the DMA controller as described above. Various techniques relating to emulation and debugging of an integrated circuit equipped with such a DMA controller that directly accesses a memory without going through a CPU have been disclosed.

For example, in Japanese Patent Laid-Open No. 62-239242,
A technique related to a debug device having an emulation CPU, a supervisor CPU and an emulation memory is disclosed. This takes advantage of the free cycles of the emulation CPU's bus during emulation,
The means for accessing the emulation memory is provided. According to the Japanese Patent Laid-Open No. 62-239242, the emulation memory access by the supervisor CPU can be made possible without interrupting the emulation processing by the emulation CPU.

In Japanese Patent Laid-Open No. 3-136143, a DMA is used.
A technique relating to an ICE including an emulator CPU having a function and a function of notifying the state of the DMA to the outside and a CPU for system management is disclosed. The ICE disclosed in this technique includes a DMA transfer buffer memory shared by the emulator CPU and the system management CPU. In addition, D of the emulator CPU
An MA transfer control program storage memory and a DMA transfer control circuit are provided. In the prior art for JP-A-3-136143, the emulator CPU executes a predetermined object program downloaded by the system management CPU in order to perform DMA processing and the like. According to the Japanese Patent Laid-Open No. 3-136143, it is possible to solve the above-mentioned problem regarding downloading, which takes time especially for a large-capacity object program.

Further, in Japanese Patent Laid-Open No. 3-242734, ICE
And a technique relating to a debug device having both the functions of a PROM (programmable readonly memory) emulator. This is done by issuing an ICE that contains an emulation memory and a bus request to the ICE.
And a control means for setting the ICE in the DMA state and switching to the function of the PROM emulator. Further, it is provided with a connecting means connectable to the PROM socket of the target board and a transmitting means for enabling the target system to access the emulation memory through the control means under the control of the control means. According to the Japanese Patent Laid-Open No. 3-242734 having such a configuration, it is possible to provide a debug device which can exhibit the function of the ICE and the function of the PROM emulator with a single device, which is advantageous in terms of equipment cost and operation. Can be provided.

Further, Japanese Patent Laid-Open No. 25945/1992 discloses a technique relating to ICE used in a system using a microcomputer and having a DMA function. this is,
It is provided with a microcomputer having a built-in DMA function, a signal indicating that supervisor interrupt processing is being performed, and a circuit for detecting that DMA transfer has occurred during the supervisor interrupt processing. Further, there are provided means for interrupting the supervisor interrupt processing by the detection signal, a circuit for detecting the end of the DMA transfer, and means for performing the supervisor interrupt processing. According to the technique disclosed in Japanese Patent Laid-Open No. 25945/1992, it is possible to solve the problem when a DMA occurs during the supervisor interrupt process. For example, when such a DMA occurs, the DMA between the memory originally in the user program area and the I / O.
F / W memory and I
It is possible to solve the problem that the data in the F / W memory is destroyed by performing the DMA transfer with the / O.

In Japanese Patent Laid-Open No. 4-111136, a CPU
And a DMA control circuit that executes data transfer between various devices without the intervention of the CPU, and a technology relating to a control LSI including a signal terminal to which an emulator is connected. First, as an operation mode, a normal mode in which various operations are executed under the control of the CPU,
It has an emulation mode that executes various operations under the control of an emulator connected to the signal terminal instead of the CPU. Further, when the DMA control circuit transfers data in the emulation mode, it is provided with data monitor means for sending the data transferred between the various devices to the emulator in parallel. The above-mentioned configuration of JP-A-4-11113
According to 6, when executing the DMA transfer by the program on the ICE side, which is conventionally used, the ICE is the LS for control.
It is possible to solve the problem that the data signal cannot be received from the I CPU and the data transferred between the devices cannot be monitored.

[0034]

However, in the above-mentioned conventional techniques relating to emulation, debugging, etc., when performing emulation or debugging of the integrated circuit chip with CPU, the above-mentioned Japanese Patent Laid-Open No. 4-259 is required.
45 and the above-mentioned Japanese Unexamined Patent Publication (Kokai) No. 4-111136. That is, there is a problem that the data transferred by DMA cannot be monitored or set. Further, these Japanese Patent Laid-Open Nos. 4-25945 and 4-111136 also have problems.

For example, in the above-mentioned JP-A-4-25945,
When the DMA transfer occurs, the supervisor interrupt process is suspended. Therefore, due to such a limitation, there is a possibility that the target system cannot be accurately emulated.

Also, in Japanese Patent Laid-Open No. 4-111136,
As described above, when DMA data transfer is performed, various restrictions are imposed on the structure of the target system to be emulated due to the structure of transferring data to the emulator in parallel with this. JP-A-4-111
In the target system to which 136 can be applied, the input / output device relating to the data to be DMA-transferred needs to be an external circuit of the control LSI having the DMA control circuit. That is, Japanese Patent Application Laid-Open No. 4-111136 cannot be applied to a DMA control circuit in which a DMA memory and an input / output device are integrated in one control LSI.

The present invention has been made to solve the above-mentioned conventional problems, and is mounted together with a CPU and an internal memory and an internal I / O circuit which are accessed by the CPU via a predetermined in-chip bus. It is possible to more effectively emulate the operation of the DMA controller used to directly access the internal memory or the internal I / O circuit via the in-chip bus.
An object is to provide a U-mounted integrated circuit chip and an emulator pod.

[0038]

A CPU according to the first invention of the present application
The mounted integrated circuit chip is mounted with a CPU and an internal memory and an internal I / O circuit which are accessed by the CPU via a predetermined in-chip bus, and also via the in-chip bus without passing through the CPU. In a CPU-equipped integrated circuit chip equipped with a DMA controller used to directly access the internal memory or the internal I / O circuit, the normal mode is transmitted by an emulation mode signal input from outside the chip. The internal memory that is operating normally,
When the emulation mode is transmitted by the signal, an emulation mode control circuit for prohibiting access to the internal memory from the in-chip bus, and detection that the internal memory and the internal I / O circuit are addressed However, each of the internal memories and the internal I
An address decoder unit for outputting an access selection signal for each of the / O circuits, and an internal memory access assertion signal indicating that any one of the internal memories is addressed in accordance with at least the access selection signal, and at least the above Access selection signal and the DMA
An internal I indicating that any one of the internal I / O circuits has been addressed or has become an access target of the DMA controller according to a predetermined bus use permission signal indicating that the controller has acquired the bus permission. /
And an internal resource access assertion circuit for independently generating these two signals, namely, generating an O access assertion signal,
The internal memory access assertion signal and the internal I / O access assertion signal are output to the outside of the CPU integrated circuit chip, thereby achieving the above object.

Further, in the integrated circuit chip equipped with CPU according to the first aspect of the present invention, the emulation mode control circuit operates normally when the normal mode is transmitted by a debug mode signal input from outside the chip. With respect to the CPU and the internal memory, when the debug mode is transmitted by the signal, the operation of the CPU is stopped and the access to the internal memory from the in-chip bus is prohibited, thereby achieving the above object. In addition, while in the debug mode, the external CPU
It is designed to be emulated by.

The emulator pod of the second invention of the present application is equipped with a CPU and an internal memory and an internal I / O circuit which are accessed by the CPU via a predetermined in-chip bus. A CPU-equipped integrated circuit chip equipped with a DMA controller used to directly access the internal memory or the internal I / O circuit via the in-chip bus without the intervention of the chip; or In order to debug a target system using the one corresponding to the chip, an emulator pod used for emulating the chip connected to the external bus in the target system or the one corresponding to the chip Both inside the chip to the in-chip bus and both inside the chip An internal bus connected via a data bus buffer connected to said chip bus,
In addition, with respect to a predetermined circuit mounted in the chip, at least an emulation peripheral circuit that is replaced during emulation and an internal memory output from the chip that indicates that one of the internal memories is addressed. A memory access assertion signal and whether any one of the internal I / O circuits has been addressed or the DMA
Internal I indicating that the controller has been targeted for access
/ O access assertion signal, and a direction control circuit which inputs at least these two signals and generates a signal for transmitting the presence / absence of data input / output between the internal bus and the external bus and the input / output direction thereof. And an internal bidirectional data bus buffer that operates according to a signal generated by the direction control circuit and inputs / outputs data between the internal bus and the external bus. is there.

Further, in the emulator pod of the second invention, the emulation peripheral circuit is provided with an EVA chip having a CPU function, which is replaced at least during emulation with respect to the CPU in the chip. In addition, in the debug mode, the CPU function of the EVA chip is used.

[0042]

According to the present invention, an integrated circuit equipped with a CPU and a memory accessed by the CPU, particularly, an integrated circuit further equipped with a DMA controller in order to improve data transfer efficiency, is used more and more. This is done by focusing on the point of improving the emulation efficiency.

In the CPU-equipped integrated circuit chip, the program of the built-in CPU is debugged.
For such a CPU-equipped integrated circuit chip having, for example, a customized circuit portion, it is necessary to verify the hardware design contents of the customized circuit portion. For these tasks, it is necessary to emulate the CPU-mounted integrated circuit chip.
In such emulation, the DMA
There is a need to more effectively emulate the operation of controllers. The present invention has been made based on these points.

FIG. 1 is a block diagram showing the gist of the present invention.

The CPU-mounted integrated circuit chip 10 shown in FIG. 1 is according to the first invention. The emulator pod 1 is according to the second aspect of the invention.

First, the CPU-mounted integrated circuit chip 10
Is at least the CPU 12, the internal memory 14, and the DM.
An A controller 16, an internal I / O circuit 18, an in-chip bus 30, an address decoder unit 34, and an internal resource access assertion circuit 36 are provided. An in-chip bidirectional data bus buffer 28 is provided as needed. Also for the internal memory 14, the internal I / O circuit 16
Also, as for each, a plurality may be provided.

The emulator pod 1 is equipped with the integrated circuit chip 10 having the CPU as described above, emulation peripheral circuits such as the emulation memory 46, the direction control circuit 45, and the internal bidirectional data bus buffer 48. 2, an internal bus 50, and an emulator circuit 74, for example.

The emulation mode control circuit,
That is, when the normal mode is transmitted by the emulation mode signal input from the outside of the chip, for the internal memory that is normally operating, when the emulation mode is transmitted by the signal, the internal memory is An emulation mode control circuit for prohibiting access to the internal memory is provided in each part of the CPU-equipped integrated circuit chip 10, and particularly, the internal memory 1
It is provided around 4 etc. The emulation mode signal is generated in the emulator pod 1 according to the setting operation performed by the user by the emulator circuit 74 or the like. The setting operation is to set a “normal mode”, an “emulation mode”, or the like.

First, the CPU integrated circuit chip 10
In the normal mode, the CPU 12 causes the internal memory 1 to pass through the predetermined in-chip bus 30.
Access peripheral circuits such as 4. Such an access target of the CPU 12 also includes, for example, an internal I / O circuit.

On the other hand, also in the DMA controller 16, in the normal mode, as shown by the chain line of the DMA controller 16 in FIG. 2, the internal memory 14 and the internal memory 14 are routed via the in-chip bus 30. I
Used to directly access the / O circuit 18.
That is, the DMA controller 16 directly uses the internal memory 14, the internal I / O circuit 18, the in-chip bus 30 and the like without using the CPU 12, and
It is also used when directly accessing a memory or I / O circuit outside the U-mounted integrated circuit chip 10. The DMA controller 16 exclusively performs data transfer via the in-chip bus 30, and can perform this more efficiently than data transfer via the CPU 12.

The address decoder section 34 detects that the internal memory 14 or the internal I / O circuit 18 has been addressed, and selects access to the internal memory 14 or the internal I / O circuit 18. Output a signal. The access selection signal corresponds to a so-called chip select signal. In the present invention, since the internal memory 14 and the internal I / O circuit 18 are integrated into one and are not independent chips, the signal as described above is not called a chip select signal but an access select signal. .

The internal resource access assertion circuit 36 is responsive to the access selection signal and a predetermined bus use permission signal indicating that the DMA controller 16 has obtained the bus use permission, and the internal memory access assertion signal and the internal I access signal.
/ O access assertion signal is independently generated.

The internal memory access assertion signal indicates that any one of the internal memories 14 has been addressed. The internal I / O access assertion signal indicates that any one of the internal I / O circuits 18 has been addressed or has been accessed by the DMA controller. The internal memory access assertion signal and the internal I / O access assertion signal are both the CPU
It is output to the outside of the on-chip integrated circuit chip.

On-chip bidirectional data bus buffer 2
When the CPU-equipped integrated circuit chip 10 is mounted on the emulator pod 1, the reference numeral 8 indicates the in-chip bus 30 on the CPU-mounted integrated circuit chip and the internal bus 50 in the emulator pod 1. Connecting.
Further, the in-chip bidirectional data bus buffer 28, when the CPU-equipped integrated circuit chip 10 is directly mounted in the target system, the in-chip bus 30 in the CPU-mounted integrated circuit chip 10 and A bus of the target system, for example a bus of the target system,
For example, it is connected to the external bus of the target system.

Next, regarding the configuration of the emulator pod 1, first, the emulation memory 46 is
As one of the emulation peripheral circuits, in the emulation mode, the internal memory 14 in the CPU mounted integrated circuit chip 10 is emulated. That is, in such an emulation mode, the C
When accessing the internal memory 14, the PU 12 accesses the emulation memory 46 instead of accessing the internal memory 14.

The direction control circuit 45 outputs an internal memory access assertion signal output by the CPU integrated circuit chip 10 indicating that one of the internal memories 14 is addressed, and the internal I / O circuit. Internal I / E indicating that any one of 18 has been addressed or has been accessed by the DMA controller 16.
Two signals, an O access assertion signal, are input. or,
The direction control circuit 45 communicates with the internal bus based on at least these two signals and by using, for example, a writing signal or a reading signal output from the CPU 12 or the DMA controller 16 as necessary. A signal for transmitting the presence / absence of data input / output to / from the external bus and the input / output direction is generated.

The internal bidirectional data bus buffer 48
Operates according to the signal generated by the direction control circuit 45, and inputs / outputs data between the internal bus 50 and the external bus. The internal bidirectional data bus buffer 48
May use, for example, a writing signal or a reading signal output from the CPU 12 or the DMA controller 16 as necessary.

The internal bidirectional data bus buffer 4
8 and the direction control circuit 45 can use such an in-writing signal and an in-reading signal, for example, an in-reading signal R / (W bar) output by a general CPU. Also, the memory read signal MEMR and the memory write signal MEM output from the DMA controller.
The W, I / O reading signal IOR or the I / O write signal IOW may be used.

The emulator circuit 74 is used by the user of the emulator to set and observe the data in the emulation memory 46 accessed by the CPU 12. The internal bidirectional data bus buffer 48 is used when the CPU 12 accesses the target system.

In the normal mode, the CPU-mounted integrated circuit chip 10 having such a configuration and the emulator pod 1 mounting the CPU-mounted integrated circuit chip 10 are
The operation shown by the broken line in FIG. 1 is performed. For example,
The CPU 12 is the CPU-equipped integrated circuit chip 10
The internal memory 14 mounted together is accessed. Regarding the DMA controller 16, data is transferred between the internal memory 14 and the internal I / O circuit under the control of the DMA controller 16 shown by the one-dot chain line in FIG.

On the other hand, in the emulation mode, the operation shown by the solid line in FIG. 1 is performed. For example, the CPU 12 accesses the emulation memory 46 on the emulator pod 1 instead of accessing the internal memory 14.

However, in such an emulation mode, conventionally, the DMA controller 16 has accessed the internal memory 14.

Therefore, in such an emulation mode, conventionally, the CPU 12 accesses the emulation memory 46, while the DMA controller 16 accesses the internal memory 14. Therefore, conventionally, when the DMA controller 16 operates in the emulation mode, a normal operation result cannot be obtained.

In the present invention, in order to solve such a conventional problem, as shown in FIG. 1, the address decoder section 34 and the internal resource access assertion are provided on the CPU mounted integrated circuit chip 10. And a circuit 36. Also, the internal resource access assertion circuit 3
The internal memory access assertion signal and the internal I / O access assertion signal output from the CPU 6 are output to the outside of the CPU integrated circuit chip 10.

As the address decoder section 34, the one conventionally provided on the CPU mounted integrated circuit chip 10 may be diverted. That is, in FIG. 1, for example, the internal memory 14 inside the CPU integrated circuit chip 10 (for each internal memory 14 when a plurality of the internal memories 14 are provided), the internal I / O circuit 1
8 (in the case where a plurality of the internal I / O circuits 18 are provided, for each of the internal I / O circuits 18), it is detected that each is addressed by the CPU 12, and the DMA controller 16
A conventional address decoder provided for detecting that access is performed while being controlled by the above may be used.

Further, in the second invention, the direction control circuit 45 is provided on the emulator pod 1. Further, a predetermined emulation mode signal is input to the CPU mounted integrated circuit chip 10 mounted on the emulator pod 1. The emulation mode signal is a signal for transmitting the "normal mode" or the "emulation mode".

In accordance with such an emulation mode signal, the CPU mounted integrated circuit chip 10 prohibits access to at least the internal memory 14 inside the CPU mounted integrated circuit chip 10 in the emulation mode. Further, in such an emulation mode, the emulator pod replaces the access to the internal memory 14 with the access to the emulation memory 46. The replacement of the internal memory 14 with the emulation memory 46 in the emulation mode is uniformly performed during the operation of the DMA controller 16.

Therefore, the internal memory 14 and the internal I / O controlled by the DMA controller 16 are controlled.
The data transfer with the circuit 18 is replaced with the data transfer between the emulation memory 46 and the internal I / O circuit 18 in the emulation mode. Further, regarding data transfer between the internal memory 14 and a predetermined I / O circuit outside the CPU mounted integrated circuit chip 10 controlled by the DMA controller 16, the emulation memory 46 is used in the emulation mode. And data transfer between the I / O circuit and the external circuit of the CPU mounted integrated circuit chip 10.

In the present invention, even in the normal mode,
Further, in the case of the emulation mode, even if the internal memory 14 is replaced with the emulation memory 46 during the operation of the CPU 12 or during the operation of the DMA controller 16 as described above, the present invention does not. As described above, by using the address decoder unit 34, the internal resource access assertion circuit 36, and the direction control circuit 45, the presence / absence of data input / output in the internal bidirectional data bus buffer and its input / output direction can be correctly controlled. You can do it. Therefore, according to the present invention, the CP
The DMA mounted on the U-mounted integrated circuit chip 10
The operation of the controller 16 can be more effectively emulated.

Although the present invention is not limited to this, when the "emulation mode" is transmitted by the predetermined emulation mode signal input to the CPU mounted integrated circuit chip 10, CP
The CPU 12 in the U-mounted integrated circuit chip 10 may be replaced with an EVA chip having a CPU function provided on the emulator pod 1. Thus, in the emulation mode, the CPU 12
Even if the CPU is replaced with the EVA chip having the CPU function, by using the address decoder unit 34, the internal resource access asserting circuit 36, the direction control circuit 45, and the like as in the present invention, for example, the internal The bidirectional data bus buffer 48 can be controlled correctly.

It should be noted that the present invention does not limit the number of the internal memories 14 and the number of the internal I / O circuits 18 provided in the CPU mounted integrated circuit chip 10. At least one internal memory 14 may be provided.
Further, regarding the internal I / O circuit 18, especially the CP
It may not be provided in the U-mounted integrated circuit chip 10. That is, in this case, the DMA controller 16 controls the predetermined I / O external to the CPU mounted integrated circuit chip 10.
It becomes possible to control the DMA transfer between the circuit and the internal memory 14 in the integrated circuit chip 10 having the CPU. Further, in this case, the internal resource access assertion circuit 36 generates at least the internal memory access assertion signal, and is not necessarily the internal I / O.
The O access assertion signal may not be generated.

It is also conceivable that the conventional output of the address decoder 34 is output to the outside of the CPU mounted integrated circuit chip 10. However, the output of the address decoder unit 34 is
Access selection signal for each internal I / O circuit 18 and the internal memory 14
And the number of the internal I / O circuits 18 increases. Therefore, when such a large number of access selection signals output by the address decoder unit 34 are output to the outside of the CPU mounted integrated circuit chip 10, the input / output pins of the CPU mounted integrated circuit chip 10 are There is a problem that many are needed.
However, in the first aspect of the present invention, only two access selection signals output by the address decoder unit 34 and a predetermined bus use permission signal indicating that the DMA controller 16 has obtained the bus use permission are used. It is possible to independently generate two signals, that is, the internal memory access assertion signal and the internal I / O access assertion signal, and output only these two signals to the outside of the CPU mounted integrated circuit chip 10. This is possible, and the total number of input / output pins required is only two.

The direction control circuit 45 is replaced by the CPU.
It is also conceivable to provide it inside the on-board integrated circuit chip 10. However, as in the embodiment described later, the circuit scale of the direction control circuit 45 tends to increase, and, for example, the number of logic gates used generally increases. Therefore, when the direction control circuit 45 having such a large scale is provided inside the CPU-equipped integrated circuit chip 10, the direction control circuit 45, which is used only at the time of emulation, allows the CPU-mounted integrated circuit chip 10 to operate. There is a problem that the degree of integration is reduced. The circuit configuration of the address decoder section 34 is generally smaller than the circuit scale of the direction control circuit 45, as in the embodiment described later. Therefore, regarding the internal resource access assertion circuit 36,
Even if it is provided in the CPU-mounted integrated circuit chip 10, the degree of integration of the CPU-mounted integrated circuit chip 10 is not significantly reduced.

[0074]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram showing the configuration of the emulator pod of the first embodiment to which the present invention is applied.

FIG. 2 shows the configuration of the emulator pod of the first embodiment to which the second invention is applied. Further, the integrated circuit chip 10 with the CPU shown in FIG.
In, the first invention is applied.

The emulator pod of the first embodiment is
Mainly, the CPU mounted integrated circuit chip 10, the direction control circuit 45, the emulation memory 46, the internal bidirectional data bus buffer 48, the internal address bus buffer 49, the emulator circuit 74, and the data between them are provided. It is configured by an internal bus 50 used for delivery and the like.

Further, in the emulator pod of this embodiment, the signal IMF is generated inside. The signal IMF is not only used in the emulator pod, but is also input to the CPU mounted integrated circuit chip 10. Further, the signal IMEM and the signal IIO are sent from the integrated circuit chip 10 with CPU.
And are output.

The signal IMEM corresponds to an internal memory access assertion signal indicating that any one of the internal memories in the CPU mounted integrated circuit chip 10 has been addressed. Further, the signal IIO is an internal I / O access assertion indicating that any one of the internal I / O circuits in the CPU mounted integrated circuit chip 10 has been addressed or has been accessed by the DMA controller. Corresponds to a signal. These signal IMEM and signal I
IO is used in the internal bidirectional data bus buffer 48.

Note that the signal IMF is not limited to being generated in the emulator pod as described above. For example, the signal IMF may be generated in the ICE body to which the emulator pod is connected. Alternatively, the logic state of the signal IMF may be uniformly set depending on whether or not the CPU mounted integrated circuit chip 10 is mounted on the emulator pod. That is, the CP is sent to the emulator pod.
When the U-mounted integrated circuit chip 10 is mounted, the signal IM
The emulation mode may be transmitted at F. In this case, when not mounted, the normal mode is transmitted by the signal IMF.

First, in FIG. 2, the emulation memory 46 is replaced with an internal memory 14 in the CPU mounted integrated circuit chip 10 which will be described later in the emulation mode. That is, in the emulation mode, the CPU 12 described later and the DM described later in the integrated circuit chip 10 with CPU are described.
The A controller 16 replaces the internal memory 14 with
The emulation memory 46 is accessed.

Further, the direction control circuit 45 causes the signal I
The MEM and the signal IIO are input. Further, the direction control circuit 45, in accordance with these two signals, the internal bus 5
A signal OE and a signal DIR for transmitting the presence / absence of data input / output between 0 and the external bus and its input / output direction are generated. The signal OE is "0" when the external bus side of the internal bidirectional data bus buffer 48 is in a high impedance state, and is "1" when data is output to the external bus side. The signal DIR transmits the data input / output direction in the internal bidirectional data bus buffer 48. That is, when the signal DIR is "0", the data input / output direction is from the external bus to the internal bus 50. When the signal DIR is "1", the direction is from the internal bus 50 to the external bus.

The internal bidirectional data bus buffer 48
Is used to connect the emulator pod to the target system. The CPU 12 (to be described later) and the DMA controller 16 (to be described later) in the CPU-mounted integrated circuit chip 10 access the target system at the time of the emulation mode and at the time of the normal mode. Access via the bus buffer 48. The control of the data input / output direction of the internal bidirectional data bus buffer 48 is performed according to the above-mentioned signal OE and signal DIR.

The signal IMF corresponds to the emulation mode signal of the present invention. Further, the signal DEN corresponds to the data enable signal of the present invention.

FIG. 3 is a block diagram showing the configuration of the CPU-mounted integrated circuit chip used in the first embodiment.

The CPU mounted integrated circuit chip 10 shown in FIG. 3 is applied with the first aspect of the invention, and mainly includes the CPU 12, internal memories 14a and 14b, and D.
MA controller 16 and internal I / O circuits 18a and 1
8b, an address decoder unit 34, an internal resource access assertion circuit 36, an on-chip bidirectional data bus buffer 2
8 and a data bus direction control circuit 26. That is, in the present embodiment, the internal memory 14
The total number of a and 14b is two, and the internal I / O circuit 1
There are a total of two 8a and 18b. These memories 14a and 14b, the CPU 12, the DMA controller 16, and the internal I / O circuits 18a and 18b.
Corresponds to the corresponding one shown in FIG.

The address decoder section 34 inputs an address signal from the in-chip address bus which constitutes the in-chip bus 30. Further, the address decoder unit 34
According to the address signal, detects whether or not each part in the CPU mounted integrated circuit chip 10 is addressed. That is, when the internal memory 14a is addressed, the signal CSM1 is set to "1" and the internal memory 14a
When b is addressed, signal CSM2 is set to "1". The address decoder unit 34 outputs a signal CSDMA when the DMA controller 16 is addressed.
Is set to "1", the signal CSIO1 is set to "1" when the internal I / O circuit 18a is addressed, and the signal CSIO1 is set to "1" when the internal I / O circuit 18b is addressed.
IO2 is set to "1". These signals CSM1, CSM
2, CSDMA, CSIO1 and CSIO2 respectively correspond to these internal memory 14a and internal I / O circuit 1
8a, etc., and also to the internal resource access assertion circuit 36.

When a data input / output request is generated in the internal I / O circuit 18a, a signal input from the internal I / O circuit 18a to the DMA controller 16 for DMA transfer of the data input / output request. DREQ1 becomes "1". On the other hand, when a data input / output request is generated in the internal I / O circuit 18b, a signal DREQ2 input from the internal I / O circuit 18b to the DMA controller 16 in order to perform the DMA transfer accompanying the request. Becomes "1".

As described above, when either the signal DREQ1 or the signal DREQ2 becomes "1", the D
The MA controller 16 is the DMA controller 16
The signal HREQ input from the CPU to the CPU 12 is set to "1". The signal HREQ is a signal for the DMA controller 16 to request the CPU 12 to transfer the bus use right of the in-chip bus 30. That is,
When the signal HREQ is "1", the bus right is requested.

Further, as described above, the signal HREQ is "1".
Then, the CPU 12 stops using the in-chip bus 30. After that, the signal HLDA input from the CPU 12 to the DMA controller 16 is set to "1".

When the signal HLDA becomes "1", the DMA controller 16 performs the signal DACK1 or the signal D so as to perform the DMA transfer using the in-chip bus 30.
Outputs ACK2. That is, when the signal DREQ1 is "1", the signal DACK1 is set to "1". On the other hand, when the signal DREQ2 is "1", the signal DACK2 is set to "1".

The internal I / O circuit 18a receives the signal D
When ACK1 becomes "1", DMA transfer of data to a predetermined memory using the in-chip bus 30 is started. Further, also in the internal I / O circuit 18b, when the signal DACK2 becomes "1", the DMA transfer of the input / output data using the in-chip bus 30 is started. When these signals DACK1 and DACK2 become "1", first, the internal I / O circuit 1
The 8a and the internal I / O circuit 18b perform input / output port settings and the like required for DMA transfer.
The signal DACK1 and the signal DACK2 are also input to the internal resource access assertion circuit 36.

The CPU mounted chip 1 of this embodiment is
0, when applying the first invention, the emulation mode control circuit of the first invention is configured as shown in FIG.
Is provided in the internal memory 14. This prohibits access to the internal memory 14 from the in-chip bus when it is transmitted by the signal IMF that it is in the emulation mode. Specifically, it is based on a predetermined circuit provided in the internal memory 14.

FIG. 4 is a logic circuit diagram of the internal resource access assertion circuit used in this embodiment.

As shown in FIG. 4 and as described above with reference to FIG. 3, the internal resource access assertion circuit 36 is used.
The signal CSM1, the signal CSM2, the signal DACK1, the signal DACK2, and the signal CSDM.
A, the signal CSIO1 and the signal CSIO2 are input. Also, the internal resource access assertion circuit 36 is
According to these signals, the signal IIO and the signal IM
Output EM. As shown in FIG. 4, the output signal IIO includes the signal DACK1 and the signal DA.
The logical sum of CK2, the signal CSDMA, the signal CSIO1, and the signal CSIO2. On the other hand, the signal IME output from the internal resource access assertion circuit 36.
M is the logical sum of the signals CSM1 and CSM2.

5 and 6 are diagrams showing the presence / absence of data input / output and the input / output direction of the internal bidirectional data bus buffer used in this embodiment.

In particular, FIG. 5 shows the case where the CPU 12 has the bus use right. On the other hand, FIG.
This is when the MA controller 16 has the right to use the bus.
Further, in FIGS. 5 and 6, it is shown whether the external bus is an output, an input, or a high impedance state (Hi-Z).

In FIG. 6, "Source"
Indicates the input source of the data transferred by the DMA controller. “Destination” indicates an output destination of data transferred by the DMA controller. “Output” indicates the data direction from the internal bus 50 to the external bus. “Input” indicates the data direction from the external bus to the internal bus 50. "Hi-Z (output)" indicates that the output of the internal bidirectional data bus buffer 48 on the external bus side is in a high impedance state.

FIG. 7 and FIG. 8 are diagrams showing signals output by the internal resource access assertion circuit and signals output by the direction control circuit in this embodiment. In particular, FIG. 7 shows the case where the CPU 12 has the right to use the bus. On the other hand, FIG. 8 shows the case where the DMA controller 16 has the bus use right.

In FIGS. 7 and 8, the CP
The signal IMEM and the signal II output from the internal resource access assertion circuit 36 in the U-mounted integrated circuit chip 10
O is indicated. Further, the signal IOR and the signal IOW transmitted through the in-chip bus 30 and the internal bus 50,
The signal MEMR and the signal MEMW are shown.

These signal IOR, signal IOW, signal ME
The MR and the signal MEMW are the signal R in FIG.
/ W. The signal IOR
And the signal IOW becomes "1" (IOR) at the time of reading from a desired I / O circuit using at least the in-chip bus 30, respectively, or a desired I / O circuit.
It becomes "1" when writing to the / O circuit (IO
W). Meanwhile, the signal MEMR and the signal MEMW
Respectively becomes "1" at the time of reading from a desired memory using at least the in-chip bus 30 (M
EMR) or "1" when writing to a desired memory (MEMW).

7 and 8, the signal IM output from the internal resource access assertion circuit 36 is output.
The signal IO inputted from the in-chip bus 30 or the internal bus 50 in accordance with EM and the signal IIO.
R, the signal IOW, the signal MEMR and the signal M
The signal DIR and the signal OE output by the direction control circuit 45 according to EMW are also shown.

As described above, according to the first embodiment, when the emulation mode is set through the emulator circuit 74, the internal memory 14 in the CPU mounted integrated circuit chip 10 is replaced. The emulation memory 46 is used. Also, during the emulation mode, the DMA controller 1
Even when 6 controls direct access to the internal memory 14, such access is replaced by access to the emulation memory 46. Therefore, according to the first embodiment, the emulation memory 46 is correctly replaced with the internal memory 14 even when the DMA controller 16 operates. Therefore, various operations related to the DMA controller 16, for example, contents of data accessed by the DMA controller 16 and a program executed by the CPU 12 for such data are more effectively emulated. be able to.

FIG. 9 is a block diagram showing the configuration of the emulator pod of the second embodiment to which the present invention is applied.

FIG. 9 shows an emulator pod to which the second invention is applied. Further, in the CPU-mounted chip 10 of FIG. 9, the CPU-mounted integrated circuit chip of the first invention is applied.

The emulator pod shown in FIG. 9 is particularly provided with an EVA chip 44 as compared with the first embodiment. The EVA chip 44 is a CPU 12 which will be described later in the CPU mounted integrated circuit chip 10.
On the other hand, it has a CPU function which is replaced in the emulation mode.

Further, in the second embodiment, the signal IMF of the first embodiment is the signal CMF (coreless mode flag). The signal CMF, like the signal IMF,
"Normal mode" or "Emulation mode"
Is a signal that conveys. The CMF signal is also set in the emulator circuit 74 by a predetermined operation by the emulator user. The signal CM
When F is "0", the normal mode is entered. on the other hand,
When it is "1", the emulation mode is set.

FIG. 10 shows C used in the second embodiment.
It is a block diagram which shows the structure of a PU mounted integrated circuit chip.

As shown in FIG. 10, the CPU-mounted integrated circuit chip 10 used in the second embodiment is different from that of the first embodiment in the portion relating to the signal CMF. That is, in the second embodiment, the signal CMF is input to the internal memory 14 and the CPU 12 as compared with the signal IMF of the first embodiment input to the internal memory 14. . When the signal CMF is "0", the internal memory 14 and the CPU 12 operate normally. That is, a normal data transfer operation via the on-chip bus 30 is performed. On the other hand, when the signal CMF becomes "1", the internal memory 14 and the CPU 12 are uniformly prohibited from accessing the in-chip bus 30.

In applying the first invention to the CPU-mounted chip 10 of the present embodiment, the emulation mode control circuit of the first invention is provided in the CPU 12 and the internal memory 14 of FIG. 10, respectively. Has been. This prohibits access of the CPU 12 and the internal memory 14 from the in-chip bus when it is transmitted by the signal CMF. Specifically, it is based on a predetermined circuit provided in each of the CPU 12 and the internal memory 14.

Also in the second embodiment, the internal resource access assertion circuit 36 is the one shown in FIG. 4 as in the first embodiment. Regarding the operation of the data bus direction control circuit 26 of the second embodiment, the operation state of the in-chip bidirectional data bus buffer 28, etc., the above-mentioned first operation shown in FIGS. It is similar to that of the first embodiment.

As described above, in the second embodiment, the emulation mode is set by the signal CMF in the emulator circuit 74 according to the operation of the user of the emulator including the emulator pod of the second embodiment. Then, the internal memory 14 in the CPU mounted chip 10 is replaced with the emulation memory 46. Further, during such an emulation mode, the CPU 12 is replaced with the CPU function of the EVA chip 44. Also in the emulation mode, the access to the internal memory 14 by the DMA controller 16 is replaced with the access to the emulation memory 46, as in the first embodiment. Therefore, as in the first embodiment, the operation of the DMA controller 16 can be more effectively emulated.

[0113]

As described above, according to the present invention, C
Directly accessing the memory via the in-chip bus, which is mounted together with the memory accessed by the PU and the CPU via a predetermined in-chip bus
The excellent effect that the operation of the MA controller can be more effectively emulated can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing the gist of a first invention and a second invention of the present application.

FIG. 2 is a block diagram showing a configuration of an emulator pod of a first embodiment to which the first invention and the second invention are applied.

FIG. 3 is a block diagram showing a configuration of a CPU-mounted integrated circuit chip used in the first embodiment.

FIG. 4 is a logic circuit diagram of an internal resource access assertion circuit used in the CPU-mounted integrated circuit chip of the first embodiment.

FIG. 5 is a first diagram showing an operating state of the data bus direction control circuit.

FIG. 6 is a second diagram showing an operating state of the data bus direction control circuit.

FIG. 7 is a diagram of a first truth table showing an operation of a data bus direction control circuit and the like used in the CPU-mounted integrated circuit chip of the first embodiment.

FIG. 8 is a diagram of a second truth table showing the operation of the data bus direction control circuit and the like used in the CPU-mounted integrated circuit chip of the first embodiment.

FIG. 9 is a block diagram showing a configuration of an emulator pod of a second embodiment to which the first invention and the second invention are applied.

FIG. 10 is a block diagram showing a configuration of a CPU-mounted integrated circuit chip used in the second embodiment.

FIG. 11 is a block diagram showing a configuration of a first example of a conventional emulator.

FIG. 12 is a block diagram showing a configuration of a second example of a conventional emulator.

FIG. 13 is a block diagram showing a configuration of an emulator pod used in a third example of conventional emulators.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Emulator pod 10 ... CPU integrated circuit chip 12 ... CPU 14 ... Internal memory 16 ... DMA controller 18 ... Internal I / O circuit 22 ... 3-input OR logic gate 24 ... 2-input OR logic gate 26 ... Data bus direction control circuit 28 ... In-chip bidirectional data bus buffer 30 ... In-chip bus 34 ... Address decoder section 36 ... Internal resource access assertion circuit 44 ... EVA chip 45 ... Direction control circuit 46 ... Emulation memory 48 ... Internal bidirectional data bus buffer 50 ... Internal Bus 74 ... Emulator circuit CSM1, CSM2, CSDMA, CSIO1, CSI
O2, IMEM, IIO, IMF, CMF, DREQ
1, DREQ2, DACK1, DACK2, HREQ,
HLDA, OE, DIR, R / E ... signal

Claims (4)

[Claims] 1. A CPU and an internal memory or an internal I / O accessed by the CPU via a predetermined in-chip bus.
A circuit is mounted, and the internal memory and the internal I are passed via the in-chip bus without passing through the CPU.
DMA used to directly access the I / O circuit
When the normal mode is transmitted by the emulation mode signal input from the outside of the integrated circuit chip with the CPU on which the controller is mounted, the emulation mode of the internal memory that is operating normally is indicated by the signal. When transmitted, it detects that the emulation mode control circuit that prohibits access to the internal memory from the bus in the chip and that the internal memory and the internal I / O circuit are addressed, An address decoder unit that outputs an access selection signal for each of the internal I / O circuits, and an internal memory access assertion signal indicating that any one of the internal memories is addressed according to at least the access selection signal. Together with at least the Either one of the internal I / O circuits has been addressed or is to be accessed by the DMA controller according to a process select signal and a predetermined bus use permission signal indicating that the DMA controller has acquired the bus use permission. An internal resource access assertion circuit that independently generates these two signals, that is, an internal I / O access assertion signal indicating that the internal memory access assertion signal and the internal I / O access assertion signal are generated. A CPU-equipped integrated circuit chip, which is output to the outside of the CPU-equipped integrated circuit chip. 2. The C circuit which is operating normally when the normal mode is transmitted to the emulation mode control circuit by a debug mode signal input from outside the chip.
Regarding the PU and the internal memory, an emulation mode control circuit for stopping the operation of the CPU and prohibiting the access to the internal memory from the in-chip bus when the debug mode is transmitted by the signal. An integrated circuit chip equipped with a CPU. 3. A CPU and an internal memory or an internal I / O accessed by the CPU via a predetermined in-chip bus.
A circuit is mounted, and the internal memory and the internal I are passed via the in-chip bus without passing through the CPU.
DMA used to directly access the I / O circuit
In order to debug the target system using the chip or the one corresponding to the chip in which the integrated circuit chip with CPU mounted with the controller is mounted, the chip or the chip connected to the external bus in the target system In an emulator pod used for emulating a device corresponding to the chip, the emulator pod is connected to the in-chip bus inside the chip on the emulator pod via a bidirectional data bus buffer provided inside the chip. An internal bus, an emulation peripheral circuit that is connected to the in-chip bus, and is replaced at least during emulation with respect to a predetermined circuit mounted in the chip; and of the internal memory output by the chip. Internal indicating that any one has been addressed A memory access assertion signal and an internal I / O access assertion signal indicating that one of the internal I / O circuits has been addressed or has been accessed by the DMA controller. A direction control circuit for inputting and generating a signal for transmitting the presence / absence of data input / output between the internal bus and the external bus and its input / output direction; and operating according to the signal generated by the direction control circuit, An emulator pod comprising an internal bidirectional data bus buffer for inputting / outputting data between an internal bus and the external bus. 4. The emulator pod according to claim 3, wherein the emulation peripheral circuit includes an EVA chip having a CPU function, which is replaced with at least the CPU in the chip during emulation.